GB2309841A

GB2309841A - HSYNC pulse synchronisation to local clock without a PLL

Info

Publication number: GB2309841A
Application number: GB9602043A
Authority: GB
Inventors: Heinz Bernhard Maeder
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1996-02-01
Filing date: 1996-02-01
Publication date: 1997-08-06
Anticipated expiration: 2016-02-01
Also published as: GB2309841B; GB9602043D0

Abstract

The frequency of a local high-frequency clock signal 10 is adjusted to match it to a multiple of an incoming horizontal sync. pulse signal 3. The frequencies of the local clock source 10 and the incoming horizontal sync. signal are compared 9 and the result 12 is applied to logic block 8 which selects 6, 7 a sequence (figure 4) of respectively delayed signals produced from the local clock source 10 by the auxiliary clock generator 4, which may be a Johnson ring counter. Hence the frequency of the output clock signal 2 may be increased or decreased with respect to the frequency of the auxiliary clock signals 5, so that no PLL is required to provide an output signal 2 with a frequency which is a multiple of the incoming signal 3.

Description

Circuit and method for generating a clock signal Field of the Invention The invention relates to a circuit and to a method for generating a clock signal based on a reference signal.

Background of the Invention Clock signals are required in a large spectrum of different environments in virtually all fields of electronics.

One particular field of technology where the generation of clock signals is important is the field of video and more specifically computer graphics. Digital video signal processing systems commonly require a stable, television linelocked clock for features such as on-screen display of text and picture-inpicture with both television receiver and video tape recorder signal sources.

From IEEE Transactions on Consumer Electronics, Vol. 39, No. 3, August 1993, pages 496-503, "Full CMOS video line-locked phase-locked loop system" a PLL system for linelocked clock generation for use in large scale CMOS video signal processing integrated circuits is known. This design attempts to meet the requirements of PLL systems which are encountered in the operation with video signals coming from low-cost consumer tape recorders without time-base correction, where the horizontal sync can periodically exhibit large phase changes that the output clock must track.

From US-A-4492979 a synchronising circuit for a matrix television set is known. Signals necessary for horizontal and vertical scanning are obtained by dividing the signal from an oscillator circuit. The frequency of the oscillator circuit does not equal that of the horizontal scanning signal, that is, in the order of 16KHz. Phase comparison is performed on a horizontal synchronising signal and a scanning signal, which is obtained by dividing the signal from the oscillator circuit, to apply negative feedback to the oscillator circuit whereby, synchronisation is performed.

From US-A-5404173 a different approach for synchronisation of the system clock signals to the pixel signals in the video data is known. Video data in the form of successive pixels in each line of a rasterscan is often provided for use in a graphics system. For example, graphics data may be displayed on the face of a video monitor and the video data may be displayed on a window on the face on this video monitor. The pixels are often presented from an external source such as from a tape at a frequency different from the clock in the graphics system in which the video data is to be displayed. According to this prior art reference progressive corrections in the timing of progressive pixels in each line of video data in accordance with the timing of the successive system clock signals in that line are provided.

From US-A-5406386 an image data receiving apparatus is known wherein a video clock signal is supplied from the sync circuit of a controller. A delay amount between the video clock signal and the image data is determined by a phase correcting section and the phase correcting section generates a corrected image area signal based on the delay amount.

This invention seeks to provide an improved circuit and method for generating a clock signal.

Summarv of the Invention According to the present invention there is provided a circuit for generating a clock signal having an average first frequency, said circuit comprising means for generating a number of auxiliary clock signals, each of said auxiliary clock signals having a second frequency, said second frequency being substantially the same for all said auxiliary clock signals, said auxiliary clock signals having different phases, means for comparing a third frequency of a reference clock signal to said second frequency or to an integer multiple of said second frequency, and means for selectively assigning one of said auxiliary clock signals to said clock signal based on an output signal of said means for comparing.

Furthermore the invention provides for a method for generating a clock signal having an average first frequency, said method comprising the steps of generating a number of auxiliary clock signals, each of said auxiliary clock signals having a second frequency, said second frequency being substantially the same for all said auxiliary clock signals, said auxiliary clock signals having different phases, comparing a third frequency of a reference clock signal to said second frequency or to an integer multiple of said second frequency, and selectively assigning one of said auxiliary clock signals to said clock signal based on said step of comparing.

The invention is particularly advantageous since it allows to realise a circuit for generating a clock signal on a single chip without external components. Due to the possibility of monolithic integration production costs are dramatically decreased. This is also due to the fact that the generation of the clock signal is possible without an PLL system. The circuit according to the invention can therefore be designed with a limited number of components and has a relatively low degree of complexity. This makes the invention also suitable for low cost consumer applications. Examples of such applications are when the video signal is delivered by a video recorder or a teletext system. Teletext systems as such are known for example from US-A-4667235, US-A-5177594 and US-A-5010406.

The application of the invention in a multimedia environment is particularly versatile because proper synchronisation of the system clock with incoming video signals is crucial for the display quality and hence the overall performance of the system. A multimedia system for which the invention can be used is known for example from US-A-5406306.

Brief Description of the Drawing An exemplary embodiment of the invention will now be described with reference to the drawing in which: FIG.1 is a schematic block diagram of a circuit for generating a clock signal in accordance with the present invention; FIG. 2 shows signal diagrams of a number of auxiliary clock signals; FIG. 3 shows a circuit which can be used for the generation of auxiliary clock signals according to the invention; FIG. 4 schematically illustrates the composition of the resulting clock signal; FIG. 5 is a flow chart of a method for generating a clock signal according to the invention; FIG. 6 is a diagrammatic illustration of the frequency comparison according to the invention.

Detailed Description of a Preferred Embodiment Referring to FIG.1, there is shown a clock generator 1 which has an output 2 and an input 3. The clock generator 1 comprises an auxiliary clock generator 4 for generating twelve different auxiliary clock signals CO, C1,..., C11. The auxiliary clock signals CO to Cii are coupled via the corresponding twelve lines 5 to a multiplexer 6. One of the auxiliary clock signals CO to Cii is outputted at a time by the multiplexer 6 on the output 2.

The multiplexer 6 is controlled by a logic circuitry 8 which is coupled to a control input of the multiplexer 6 via the signal line 7.

Further, the clock generator 1 has a comparator 9. The comparator 9 is coupled to the input 3 and to a clock generator 10. The clock generator 10 generates a high frequency clock signal CL which is inputted via the signal line 11 into the comparator 9. The comparator 9 is coupled via the signal line 12 to the logic circuitry 8.

The comparator 9 compares the frequency F1 of an input reference signal at the input 3 to the frequency F2 of the clock signal CL. The comparator 9 compares the frequencies F1 and F2 by checking whether the frequency F2 of the clock signal CL is an integral multiple of the frequency F1 of the input reference signal. With other words it is checked in the comparator 9 whether the division of the frequency F2 by the frequency F1 yields an integer number.

If this is the case the comparator 9 does not issue a correction signal on the line 12 to the logic 8.

Otherwise the comparator 9 issues a correction signal as an input for the logic circuitry 8. Based on the correction signal the logic circuitry 8 determines a sequence of auxiliary clock signals to be sequentially selected by the multiplexer 6 for output and issues a number of control signals via the signal line 7 to the multiplexer 6 to control the multiplexer 6 correspondingly. The auxiliary clock signals CO to Cli have the same frequency F3 whereby the frequency F2 is an integral multiple of the frequency F3. In the example considered here the frequency F3 equals the frequency F2 divided by 12. The selection of the sequence of auxiliary clock signals is carried out by the logic circuitry 8 so that the resulting output clock signal has an average frequency F which is an integral multiple of the frequency F1 of the input reference signal.

With other words the average frequency F divided by the frequency F1 is a predetermined integral number N. This adjustment of the average frequency F of the output clock signal to the frequency F1 of the input reference signal is possible due to the phase shifts between the individual auxiliary clock signals CO to C11. This is explained in more detail in the following.

In FIG. 2 signal diagrams of the clock signal CL from the clock generator 10 and of the auxiliary clock signals CO to Cii are shown. The rising edge of the signal CO coincides with the falling edge of the clock signal CL at the time TO on the time axis T. The consecutive rising edge of the clock signal CL at the time T1 coincides with the rising edge of the auxiliary clock signal C1.

Analogously the consecutive falling edge of the clock signal CL coincides with the rising edge of the auxiliary clock signal C2. The same applies analogously to the further auxiliary clock signals C3 to Cii with respect to the clock signal CL.

In the example considered here the clock signal CL has a frequency of 72 MHz whereas the auxiliary clock signals have a frequency of 12 MHz. The individual auxiliary clock signals are phase shifted by 30 towards each other, i.e. the clock signal CO is 30 ahead of C1, the signal C1 is 30 ahead of C2 and so on.

This is also shown in the complex phase diagram of FIG. 2 where each of the clock signals CO to Cii is symbolised by a pointer in a complex plain.

The generation of the auxiliary clock signals CO to Cii can be accomplished by the circuit shown in FIG. 3. This circuit is comprised in the auxiliary clock generator 4 of FIG. 1. The circuit has a shift register 13 comprising the individual shift register latches SO to S5. The output of the shift register 13 is coupled via the inverter 14 and the line 15 back to its input. A circuit of this type is also sometimes referred to as a Johnson Divider.

The shift register 13 is clocked by the clock signal CL. This results in the output of the signals CO and C1 from the slave and the master latches of the shift register latch SO, respectively. The same applies analogously for the further shift register latches S1 to S5 and their respective outputs C2, C3; C4, C5; C6, C7; C8, C9 and C10, C11.

In FIG. 4 the selection of the auxiliary clock signals by the logic circuitry 8 is shown by way of example. The different signals LO to L5 shown in FIG. 4 are different input reference signals which can be inputted at the input 3 and which have slightly different frequencies F1 (LO), F1 (Li), ..., F1 (L5). The frequency Fl slightly increases from the input reference signal LO to the input reference signal L5. This increase is not shown in the drawing, because it is relatively small. In the example considered here the frequencies F1 are about 16 KHz which is the line clock frequency of a video display. The output clock signal at the output 2 has to have an average frequency F which is an integral multiple of the frequency F1 of the input reference signal applied at the input 3. If the clock generator 1 is to be used for a graphics or video system, especially for the clocking of individual pixels within a video line, this is essential to avoid distortions on the display.

In the example considered here the frequency F3 of the auxiliary clock signals CO to Cii is 12 MHz.

In the following it is assumed that the frequency F1 (LO) is exactly 16 HHz.

Then the division of the frequency of the auxiliary clock signals F3 by the frequency F1(LO) equals exactly 750 which is an integer number. As a consequence no correction of the frequency F3 is necessary for the generation of the output signal on the output 2. For the purposes of video and in particular graphics it is advantageous to select an auxiliary clock signal CX of the auxiliary clock signals CO to Cli which has the same phase as the input reference signal - which is LO in the example considered here - at the vertical sync pulse of the input reference signal.

In the following it is assumed that the phase of the auxiliary clock signal C5 is substantially equal to the phase of the signal LO at the vertical sync pulse.

Since the auxiliary clock signal C5 has a frequency F3 which is an integral multiple of the frequency F1 (LO) this is also true for the relationship between the frequency F2 of the clock signal CL and the frequency F1 (LO). As a consequence the comparator 9 does not issue a correction signal via line 12 to the logic circuitry 8 so that the initial selection of the auxiliary clock signal C5 is not changed. The initial selection of an auxiliary clock signal can be performed by means of a phase detector which can be coupled to the logic circuitry 8. A phase detector is known for example from US-A-5426397.

Another possibility would be to reset the auxiliary clock generator 4 with every vertical sync pulse. Then the auxiliary clock signal CO can always be selected as the initial auxiliary clock signal for output via the multiplexer 6 since by resetting of the auxiliary clock generator 4 it is guaranteed that it has the same phase as the input reference signal when the sync pulse occurs.

The input reference signal L1 has a frequency F1(L1) which is slightly higher than 16 KHz. As a consequence the average frequency F of the output signal of the clock generator 1 also has to be increased. Like in the case considered before with respect to the signal LO the first auxiliary clock signal which is selected at the sync pulse of the L1 signal and which is assigned to the output 2 is the clock signal C5. At the time T2 on the time axis T of Fig. 4 the auxiliary clock signal C4 is assigned to the output 2 by means of the multiplexer 6 under control of the logic circuitry 8. This is due to the correction signal which is issued by the comparator 9 via the signal line 12 to the logic circuitry 8 in response to the increased frequency F1 of the input reference signal on the input 3 which in this case is F1 (L1). The resulting signal R is shown in the lower portion of FIG. 5. Due to the phase shift from the auxiliary clock signal C5 to the auxiliary clock signal C4 the first half period P of the resulting signal R is one sixth shorter than the other half periods Q of the resulting signal R.

As a consequence the average frequency F of the resulting signal R between two consecutive sync pulses of the signal L1 is increased. The half period P even though it is shorter than a normal half period Q is still long enough to provide a clocking input for example to a graphics or video system. The change from the assignment of the auxiliary clock signal C5 to the auxiliary clock signal C4 is symbolised in FIG. 5 by the arrow being denoted "C4".

The same principle applies analogously to the further signals L2 to L5: as the frequency F1 of the input reference signal increases from L2 to L5 the average frequency F of the resulting signal which is the output signal of the clock generator 1 has to be increased correspondingly. To accomplish this the shift from the auxiliary clock signal C5 to signal C4 occurs after one fourth of the period of the signal L2 after the vertical sync pulse. After three fourth of the period of the signal L2 a further change of the assignment of the auxiliary clock signals from signal C4 to C3 occurs.

Likewise when the signal L3 is applied to the input 3 of the clock generator 1 the sequence of auxiliary clock signals to be sequentially assigned to the output 2 via the multiplexer 6 under control of the logic circuitry 8 is the signal C5 which is the initial assignment and then in consecutive order the auxiliary clock signals C4, C3 and C2. The signal C4 is assigned after one fourth, the signal C3 after one half and the signal C2 after three fourth of the period of the signal L3 between two consecutive sync pulses.

For the signal L4 which has an even higher frequency than the signal L3 this sequence of signals is C5, C4, C3, C2 and C1. The signal C4 is assigned after one eighth, the signal C3 after three eighth, C2 after five eighth and the signal C1 after seven eighth of the period of the signal L4 between two consecutive sync pulses. Likewise the corresponding sequence of signals is C5, C4, C3, C2, C1 and CO for the signal L5. The additional phase shift occurs in the middle of the period between two consecutive sync pulses of the signal L5 in this case.

In some environments it can be desirable to equally distribute the local variations of the frequency of the output signal due to the phase shifts from one assignment of an auxiliary clock signal to another. In the example considered here the distribution of the selection of different auxiliary clock signals is only an approximation to an ideal equal distribution between two consecutive sync pulses. However, for most applications such an approximation is sufficient and can be realised with much less expenditure in terms of the hardware which is required. For example the above described sequencing of the assignment of the different auxiliary clock signals can be accomplished by means of a state of the art bit rate multiplier within the logic circuitry 8.

FIG. 5 shows one embodiment of a method according to the invention for generating a clock signal. The carrying out of the method is triggered by the reception of a sync pulse of the input reference signal at the input 3 of the clock generator 1 in step 1. In step 2 the input reference signal having the frequency F1 is compared to the frequency F3 of the auxiliary clock signals CO to C11. This comparison implies a comparison of the frequency F2 to the frequency F1 of the input reference signal since the frequency F2 is an integral multiple of the frequency F3 as it appears from FIG. 3.

In the following it is assumed that the frequency comparison is performed between the frequencies F3 and F1. The division of the frequency F3 which equals 12 MHz in this example by the frequency F1 which is in the order of 16 KHz yields an integer I plus a real number K which can be positive or negative.

The integer I has a predetermined value which equals 750 in this example.

As a consequence the real number K is expressive of the deviation of the frequency F1 from the normal frequency which is assumed to be equal to 16 KHz. A positive value of the number K indicates that the actual frequency of the input reference signal F1 is lower than 16 KHz. If the number K is negative this indicates the opposite. The integer number I in this case is always 12 MHz divided by the normal frequency of 16 KHz which is 750.

Each value of the number K has assigned thereto a corresponding sequence of auxiliary clock signals. If the number K is positive this means that the frequency F1 is lower than the nominal frequency of 16 KHz and that the average frequency F of the output signal of the clock generator 1 has to be decreased correspondingly. This is accomplished by selecting a sequence of auxiliary clock signals to be assigned to the output 2 of the clock generator 1 in clockwise order in the phase diagram of FIG. 2. Each selected sequence is to be applied to the output 2 between two consecutive sync pulses.

Possible sequences according to the value of the required frequency correction are the sequences C5, C6; C5, C6, C7; C5, C6, C7, C8 or C5, C6, C7, C8, C9.

The more auxiliary clock signals the sequence contains the lower the resulting average frequency is because each change of one assigned auxiliary clock signal to another results in a half period of the resulting clock signal which is one sixth longer than a normal half period.

If the number K is negative this indicates that the average frequency F has to be higher than the frequency F3 of the auxiliary clock signals. This situation corresponds to the signals L1 to L5 of FIG.4.

If the number K has only a minimum value only one single phase shift is required like in the case of the signal L1. Higher values of K require that the assignments of the auxiliary clock signals be changed more often in order to sufficiently increase the average frequency of the output signal of the clock generator 1. The appropriate sequence of auxiliary clock signals for one period of the input reference signal between two consecutive sync pulses is selected in step 3 of FIG. 6 by the logic circuitry 8. This can be accomplished for example by means of a look up table.

In step 4 of the method illustrated in FIG. 5 the multiplexer 6 is controlled by the logic circuitry 8 according to the selected sequence during the time period between two consecutive sync pulses of the input reference signal. At the end of a horizontal line a line counter is incremented in step 5. In step 6 it is decided whether the value of the counter is lesser than a predetermined value M. If this is the case the control returns to step 4 which is carried out again for the next consecutive horizontal line employing the same selected sequence of auxiliary clock signals again. If the contrary is true the control returns back to the step 2 so that the frequencies F3 and F1 are compared again in the comparator 9 and a sequence of auxiliary clock signals is selected again in step 3.

The repetition of the comparison of the frequencies in step 2 is required if the frequency F1 of the input reference signal varies over time. The frequency F1 of a video signal coming from a television sender is very stable over time so that the number M can be chosen to be relatively big. However, if the input reference signal comes from a video recorder a smaller number has to be chosen for M such as M=4 due to the large frequency variations which are caused by tape stretch.

FIG. 6 shows an alternative method for comparing the frequencies of the input reference signal and the auxiliary clock signals. As stated above a direct comparison of the frequency F1 of the input reference signal to the frequency F3 of the auxiliary clock signals can be substituted by a comparison of F1 to the frequency F2 of the clock signal CL because the clock signal CL forms the basis for the generation of the auxiliary clock signals CO to Cli as it appears from FIG. 3. Such a comparison is carried out according to the alternative method for comparing the frequencies as illustrated in FIG. 6.

In the upper portion of FIG. 6 an input reference signal which is applied at the input 3 of the clock generator 1 is shown. The solid line symbolises the signal LO (cf. FIG. 4) which has a frequency F1 of 16 KHz. The dotted lines symbolise other input reference signals LX and LY. It is assumed that at the time T=O the signals L0, LX and LY have the same phase. The signal LX has a frequency F1 (LX) which is higher and the signal LY has a frequency F1 (LY) which is lower than the frequency F1 (LO) of the input reference signal. Only the sync pulses after four periods of the signals LX and LY are shown in FIG.

6.

According to this method for comparing the frequencies a 12 bit binary counter is used which is clocked by the clock signal CL at the frequency F2 which in this case is 72 MHz. The 12 bit binary counter is used to measure the duration of four line periods of the input reference signal in unit intervals of the 72 MHz clock signal CL. There are 18432 periods of the 72 MHz clock signal CL contained during four line periods of the input reference signal L0 at 64 Rs each. During the measurement time which is four line periods of the input reference signal the 12 bit binary counter overflows four times as illustrated in FIG. 6. When the input reference signal is the signal LO, the 12 bit binary counter reaches its mid position which is hexadecimal 7FF at the end of the measurement time TM. If this is the case no frequency correction is required (cf. FIG. 4).

If however the signal LX is applied to the input 3 of the clock generator 1 then the 12 bit binary counter will not reach its mid position due to the higher frequency F1 of the input reference signal. The deviation of the actual count of the 12 bit binary counter from its mid position is indicative of the deviation of the frequency F1 (LX) of the input reference signal from the nominal 16 KHz frequency. If the signal LY is applied to the input 3 then the count of the 12 bit binary counter after four periods of the signal LY likewise will be higher than the mid position. The deviation from the mid position again indicates the deviation of the frequency F1 (LY) from the nominal 16 KHz frequency.

If the count of the 12 bit binary counter is higher than its mid position, this means that a sequence of auxiliary clock signals has to be selected in counter clockwise order (cf. the phased diagram of FIG. 2); if the count is lesser than the mid position this means that a sequence of auxiliary clock signals to be assigned has to be selected in clockwise order.

According to one implementation of the invention a maximum of 511 assignments of auxiliary clock signals CO to Cii is possible for positive or negative frequency corrections during one period between two sync pulses of the input reference signal. As a consequence the resulting clock frequency which is the average frequency F is varied in 1022 steps. This corresponds to a tolerance band between 14.803 KHz and 16.544 KHz of the input reference signal. The quantization steps within this frequency band are 1.7 Hz.

Claims

1. A circuit for generating a clock signal having an average first frequency, said circuit comprising: - means (4, 10, 13, 14, 15) for generating a number of auxiliary clock signals (CO,C1,C2,...,C11), each of said auxiliary clock signals having a second frequency, said second frequency being substantially the same for all said auxiliary clock signals, said auxiliary clock signals having different phases; - means (9) for comparing a third frequency of a reference clock signal to said second frequency or to an integer multiple of said second frequency, and - means (6, 8) for selectively assigning one of said auxiliary clock signals to said clock signal based on an output signal of said means for comparing.

2. The circuit according to claim 1 said means for generating a number of auxiliary clock signals comprising - means (10) for generating of a further clock signal having a fourth frequency, and - frequency divider means (13, 14, 15) for dividing said fourth frequency of said further clock signal, said frequency divider means comprising a Johnson counter.

3. The circuit according to claim 1 or 2 said means for comparing comprising means for measuring a relative frequency difference between said reference signal and said second frequency or an integer multiple of said second frequency.

4. The circuit according to claim 1, 2 or 3 said means for selectively assigning comprising logic means (8) for determining a sequence of said auxiliary clock signals to be sequentially assigned to said clock signal.

5. A video system comprising a circuit according to any one of the preceding claims, said reference clock signal being a video line clock.

6. The video system according to claim 5, said video system further comprising a teletext unit for receiving a composite video signal and sequentially outputting teletext information for display in synchronism with said clock signal.

7. The video system according to claim 5 or 6 said video system comprising a video recorder which provides for said video line clock.

8. A method for generating a clock signal having an average first frequency, said method comprising the steps of: - generating a number of auxiliary clock signals (CO, C1, C2,..., C11), each of said auxiliary clock signals having a second frequency, said second frequency being substantially the same for all said auxiliary clock signals, said auxiliary clock signals having different phases; - comparing a third frequency of a reference clock signal to said second frequency, and - selectively assigning one of said auxiliary clock signals to said clock signal based on said step of comparing.

9. The method according to claim 8 said step of selectively assigning comprising a step of determining a sequence of said auxiliary clock signals to be sequentially assigned to said clock signal.

10. The method according to claim 9 said step of determining a sequence comprising a step of selecting said sequence from a predefined set of sequences wherein in each of said sequences the phase shift of consecutive auxiliary clock signals is substantially equal.

11. The method according to claim 8, 9 or 10 said step of selectively assigning comprising a step of selecting one of said auxiliary clock signals which has the smallest phase difference to said reference clock signal.

12. A circuit for generating a clock signal having an average first frequency substantially as hereinbefore described with reference to the accompanying drawings.

13. A method for generating a clock signal having an average first frequency substantially as hereinbefore described with reference to the accompanying drawings.