[go: up one dir, main page]

GB2307334A - Electronic component packaging - Google Patents

Electronic component packaging Download PDF

Info

Publication number
GB2307334A
GB2307334A GB9523456A GB9523456A GB2307334A GB 2307334 A GB2307334 A GB 2307334A GB 9523456 A GB9523456 A GB 9523456A GB 9523456 A GB9523456 A GB 9523456A GB 2307334 A GB2307334 A GB 2307334A
Authority
GB
United Kingdom
Prior art keywords
electronic component
array
contacts
component packaging
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9523456A
Other versions
GB9523456D0 (en
Inventor
Stephen Geoffrey Tyler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems Electronics Ltd
Original Assignee
GEC Marconi Ltd
Marconi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GEC Marconi Ltd, Marconi Co Ltd filed Critical GEC Marconi Ltd
Priority to GB9523456A priority Critical patent/GB2307334A/en
Publication of GB9523456D0 publication Critical patent/GB9523456D0/en
Publication of GB2307334A publication Critical patent/GB2307334A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09609—Via grid, i.e. two-dimensional array of vias or holes in a single plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09627—Special connections between adjacent vias, not for grounding vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/041—Solder preforms in the shape of solder balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Electronic component packaging comprises a multi-layer printed circuit board structure defining, on an outer surface of a first substrate (10), a first array of contacts (14) connected to the electronic component (16) and, on an outer surface of a second substrate (12), a second array of contacts (28) for connection to an electronic circuit. The first array of contacts (14) and is connected to conductive tracks (20) also formed on the outer surface of the first substrate (10). The conductive tracks (20) are selectively connected to appropriate contacts (28) of the second array by conductive blind vias (24) extending through the first substrate (10) and connected by conductive tracks (22) arranged between the first (10) and second (12) substrates wherein substantially all of the connections to the electronic component (16) are connected to the first array of contacts (14).

Description

ELECTRONIC COMPONENT PACKAGING The present invention relates to the packaging of electronic components and is especially, although not exclusively, concerned with the packaging of electronic components having a large number of connections.
The trend in the design of electronic components, such as for example microprocessors, is ever more complex circuits requiring an ever-increasing number of connections. For example, it is known to have integrated circuits with 600 or more connections and components with a greater number of connections are contemplated.
Packaging such components requires making appropriate electrical connections between the extremely small contact pads on the component, which are usually situated around the periphery of the component, to a known arrangement of connecting pads, or pins, of the packaging which enable the component to be connected to other circuitry. This everincreasing number of connection pads results in packaging of increasing size, complexity and expense.
It is an object of the present invention to provide a compact packaging suitable for electronic components with a large number of connections.
According to the present invention electronic component packaging comprises a multilayer printed circuit board structure defining, on an outer surface of a first substrate, a first array of contacts connected to the electronic component and, on an outer surface of a second substrate, a second array of contacts for connection to an electronic circuit, the first array of contacts being connected to conductive tracks also formed on the outer surface of the first substrate, and the conductive tracks being selectively connected to appropriate contacts of the second array by conductive blind vias extending through the first substrate and connected by conductive tracks arranged between the first and second substrates, wherein substantially all of the connections of the electronic component are connected to the first array of contact.In this manner an electronic component having a large number of connections can be mounted on the first substrate with all of its connections connected to the first array of contacts thereby avoiding any necessity to have the first array of contacts staggered on separate substrates.
At least one further substrate carrying conductive tracks can be arranged between the first and second substrates.
In a preferred arrangement the electronic component is arranged to be in thermal communication with an area of thermally conducting material defined on the outer surface of the first substrate and, the area is connected by thermally conductive vias to a heat sink. Such an arrangement provides enhanced heat sinking of the component.
An electronic component packaging in accordance with the invention will now be described, by way of example only, with reference to the accompanying drawings, in which: Figure 1 is an exploded view of part of an electronic component packaging in accordance with the present invention; Figure 2 is a vertical section through a portion of the packaging of Figure 1; and Figure 3 is a vertical section through another portion of the packaging of Figure 1 illustrating a heat sinking arrangement.
Referring to Figures 1 and 2 an electronic component packaging comprises a multi-layer printed circuit board which comprises a first dielectric substrate 10 and second dielectric substrate 12. On an outer surface of the first dielectric substrate 10 there is defined an array of component contacts 14 comprising a copper layer. An electronic component 16 is mounted on the outer surface of the substrate 10 and electrical connection between the electronic component 16 and component contacts 14 is effected by means of fine gold wires 18.
Typically the pitch X between the component contacts 14 is less than 200 microns (cm).
We have successfully made electronic compact packaging with the pitch X substantially smaller, for example, less than 150 or 100 microns (pom).
Also defined on the outer surface of the dielectric substrate 10 there are electrically conductive tracks 20 which electrically connect the component contacts 14 to conductive tracks 22 arranged between the first 10 and second substrates 12. Electrical connection of the conductive tracks 20, 22 through the first substrate 10 is achieved by means of miniature blind vias 24 at selected positions. In this context, as is known in the art, a via is an aperture through the substrate which forms a conductive path between via pads 26 on opposite faces of the substrate. Typically the blind vias 24 have a circular cross section and a diameter of less than 200calm. We have successfully made vias of 150 or 100 or 50pm in diameter.A preferred method of forming the miniature blind vias 24 and the conducting tracks 20 is described in our co-pending patent applications numbers (reference P/60767/MRCG, P/60771/MRCG and P/60795/MRCG...
in the records of the Applicant's Patent Department) which is hereby incorporated into this application by way of reference.
With particular reference to Figure 2 the first dielectric substrate 10 is formed from a sheet of polyimide of approximately 75pm in thickness and the second dielectric substrate 12 comprises a glass fibre loaded epoxy material of approximately one millimetre (mm) thick which is substantially rigid.
On an outer surface of the second substrate 12 there is a regular array of electrical contacts 28 of diameter 0.8 mm spaced 1.2 mm apart, though it will be appreciated that other diameters and spacings can be used depending upon the requirements of the particular application. The electrical contacts 28 electrically connect through the second substrate 12 by means of through vias 30 to the corresponding via pads 32 on the inner surface of the substrate. The through vias 30 are conveniently formed by mechanically drilling through the substrate 12 in the centre of the via pads 32 prior to laminating the first substrate 10 onto the second substrate 12. The substrate is then conditioned and metallised by immersion in a bath of activated palladium, to form a conductive path 34 between the electrical contacts 28 and the via pads 32.Typically the diameter of the through vias 30 is approximately 300pm.
It will be appreciated that the component contacts 14 can be selectively connected to the electrical contacts 28 by defining appropriate conductive tracks 20, 22 to connect with the via pads 32, or by forming a miniature via 24 through either a component contact 14, or the appropriate conductive track, directly into the required via pad 32.
In the preferred arrangement shown in Figure 2 the array of contacts 28 comprises a regular array which is used to produce a "ball grid array". As is known in the art, a ball 36 of high tin (90% Sn) is applied to each pad 28 using a low eutectic solder 38. The ball grid array provides a convenient method for connecting the electronic packaging to another circuit. The present invention enables the reliable packaging of components with 676 (26x26) connections to a ball grid array using a substrate of less than twelve square centimetres in area.
With the invention it is also possible to provide heat sinking of the electronic component 16 as illustrated in Figure 3. A heat sink is defined by an area of copper 40 on the outer face of the first substrate 10. The electronic component 16 is bonded to the heat sink 40 such that the component 16 is in good thermal communication with the heat sink 40. By appropriately positioning and interconnecting thermally conductive blind vias 24, thermally conductive tracks 22 and thermally conductive through vias 30, a thermally conductive path can be defined from the area 40 to selected contacts 28.
It will be appreciated that whilst the packaging shown comprises two substrates 12, 14, further substrates with further intermediate layers of conductive tracks can be used to achieve complex interconnecting of the upper array of contacts 14 to the contacts 28.
Furthermore packaging of a plurality of electronic components is possible.

Claims (15)

1. Electronic component packaging comprising a multi-layer printed circuit board structure defining, on an outer surface of a first substrate, a first array of contacts connected to the electronic component and, on an outer surface of a second substrate, a second array of contacts for connection to an electronic circuit, the first array of contacts being connected to conductive tracks also formed on the outer surface of the first substrate, and the conductive tracks being selectively connected to appropriate contacts of the second array by conductive blind vias extending through the first substrate and connected by conductive tracks arranged between the first and second substrates, wherein substantially all of the connections of the electronic component are connected to the first array of contacts.
2. Electronic component packaging, according to Claim 1, comprising at least one further substrate carrying conductive tracks arranged between the first and second substrates.
3. Electronic component packaging, according to Claim 1 or Claim 2, in which the electronic component is in thermal communication with an area of thermally conducting material on the outer surface of the first substrate, the area being connected by thermally conductive vias to a heat sink
4. Electronic component packaging, according to any of Claims 1, 2 or 3, in which the first array of contacts are spaced at a pitch of less than 200pm..
5. Electronic component packaging, according to Claim 4, in which the first array of contacts is spaced at a pitch of more than 150cm.
6. Electronic component packaging, according to Claim 4, in which the first array of contacts is spaced at a pitch of more than 100calm.
7. Electronic component packaging, according to any preceding claim, in which the conductive tracks are of width less than 100pom.
8. Electronic component packaging, according to Claim 7, in which the conductive tracks are of a width of more than 75calm.
9. Electronic component packaging, according to Claim 7, in which the conductive tracks are of a width of more than 50calm.
10. Electronic component packaging, according to any preceding claim, in which the conductive blind vias are of less than 200 m.
11. Electronic component packaging, according to Claim 10, in which the conductive blind vias are more than 150pm.
12. Electronic component packaging, according to Claim 10, in which the conductive blind vias are of more than 100 m.
13. Electronic component packaging, according to Claim 10, in which the conductive blind vias are of more than 50pom.
14. Electronic component packaging, according to any preceding claim, in which the second array of contacts is a ball grid array.
15. Electronic component packaging substantially as hereinbefore described with reference to the accompanying drawings.
GB9523456A 1995-11-16 1995-11-16 Electronic component packaging Withdrawn GB2307334A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9523456A GB2307334A (en) 1995-11-16 1995-11-16 Electronic component packaging

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9523456A GB2307334A (en) 1995-11-16 1995-11-16 Electronic component packaging

Publications (2)

Publication Number Publication Date
GB9523456D0 GB9523456D0 (en) 1996-01-17
GB2307334A true GB2307334A (en) 1997-05-21

Family

ID=10783990

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9523456A Withdrawn GB2307334A (en) 1995-11-16 1995-11-16 Electronic component packaging

Country Status (1)

Country Link
GB (1) GB2307334A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014224732A1 (en) * 2014-12-03 2016-06-09 Automotive Lighting Reutlingen Gmbh Printed circuit board for a motor vehicle lighting device with optimized heat dissipation

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0268111A2 (en) * 1986-11-17 1988-05-25 International Business Machines Corporation Interposer chip technique for making engineering changes between interconnected semiconductor chips
EP0520841A1 (en) * 1991-06-27 1992-12-30 Motorola, Inc. Composite flip chip semi-conductor device and method for making and burning-in the same
EP0592022A1 (en) * 1992-08-12 1994-04-13 International Business Machines Corporation A direct chip attach module (DCAM)

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0268111A2 (en) * 1986-11-17 1988-05-25 International Business Machines Corporation Interposer chip technique for making engineering changes between interconnected semiconductor chips
EP0520841A1 (en) * 1991-06-27 1992-12-30 Motorola, Inc. Composite flip chip semi-conductor device and method for making and burning-in the same
EP0592022A1 (en) * 1992-08-12 1994-04-13 International Business Machines Corporation A direct chip attach module (DCAM)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014224732A1 (en) * 2014-12-03 2016-06-09 Automotive Lighting Reutlingen Gmbh Printed circuit board for a motor vehicle lighting device with optimized heat dissipation
EP3030058A3 (en) * 2014-12-03 2017-03-01 Automotive Lighting Reutlingen GmbH Printed circuit board for a motor vehicle lighting device with optimized heat dissipation
DE102014224732B4 (en) 2014-12-03 2022-02-10 Automotive Lighting Reutlingen Gmbh Printed circuit board for a motor vehicle lighting device with optimized heat dissipation

Also Published As

Publication number Publication date
GB9523456D0 (en) 1996-01-17

Similar Documents

Publication Publication Date Title
US5719749A (en) Printed circuit assembly with fine pitch flexible printed circuit overlay mounted to printed circuit board
KR100442215B1 (en) Printed wiring circuit multilayer assembly and manufacturing method thereof
US5375042A (en) Semiconductor package employing substrate assembly having a pair of thin film circuits disposed one on each of oppositely facing surfaces of a thick film circuit
US5412539A (en) Multichip module with a mandrel-produced interconnecting decal
KR960006982B1 (en) Stepped Multilayer Interconnect
US5943212A (en) Ceramic circuit board and semiconductor device using same
US20020158335A1 (en) High performance, low cost microelectronic circuit package with interposer
KR970003991B1 (en) Double sided memory board and memory module using the board
US20010002727A1 (en) Semiconductor device and module of the same
US5953816A (en) Process of making interposers for land grip arrays
US6147870A (en) Printed circuit assembly having locally enhanced wiring density
JPS5826826B2 (en) Ceramic packages for integrated circuits
JPH04233794A (en) Multilayer circuit board assembly and its manufacture
EP0139431B1 (en) Method of mounting a carrier for a microelectronic silicon chip
US5245135A (en) Stackable high density interconnection mechanism (SHIM)
US6034437A (en) Semiconductor device having a matrix of bonding pads
JP2500308B2 (en) Method for manufacturing multilayer printed wiring board
GB2307334A (en) Electronic component packaging
US5880935A (en) Device for using in an electronic controller
JPH09246684A (en) Bga mounting structure
JP4372407B2 (en) Multilayer printed wiring board
CA1311854C (en) Apparatus and method for high density interconnection substrates using stacked modules
JP2817715B2 (en) Ball grid array type circuit board
JP3508739B2 (en) Interposer board
JPH0645763A (en) Printed wiring board

Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)