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GB2305295B - Method for forming interlayer insulating film of semiconductor device - Google Patents

Method for forming interlayer insulating film of semiconductor device

Info

Publication number
GB2305295B
GB2305295B GB9619116A GB9619116A GB2305295B GB 2305295 B GB2305295 B GB 2305295B GB 9619116 A GB9619116 A GB 9619116A GB 9619116 A GB9619116 A GB 9619116A GB 2305295 B GB2305295 B GB 2305295B
Authority
GB
United Kingdom
Prior art keywords
semiconductor device
insulating film
interlayer insulating
forming interlayer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9619116A
Other versions
GB9619116D0 (en
GB2305295A (en
Inventor
Si Bum Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of GB9619116D0 publication Critical patent/GB9619116D0/en
Publication of GB2305295A publication Critical patent/GB2305295A/en
Application granted granted Critical
Publication of GB2305295B publication Critical patent/GB2305295B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H10W20/071—
    • H10W20/01—
GB9619116A 1995-09-14 1996-09-12 Method for forming interlayer insulating film of semiconductor device Expired - Fee Related GB2305295B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950030005A KR100197980B1 (en) 1995-09-14 1995-09-14 Manufacturing method of semiconductor device

Publications (3)

Publication Number Publication Date
GB9619116D0 GB9619116D0 (en) 1996-10-23
GB2305295A GB2305295A (en) 1997-04-02
GB2305295B true GB2305295B (en) 2000-05-10

Family

ID=19426789

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9619116A Expired - Fee Related GB2305295B (en) 1995-09-14 1996-09-12 Method for forming interlayer insulating film of semiconductor device

Country Status (4)

Country Link
JP (1) JP2937886B2 (en)
KR (1) KR100197980B1 (en)
DE (1) DE19637458A1 (en)
GB (1) GB2305295B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112635329A (en) * 2020-12-14 2021-04-09 华虹半导体(无锡)有限公司 Interlayer dielectric layer of DMOS device and manufacturing method thereof

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002313968A (en) * 2001-02-08 2002-10-25 Seiko Epson Corp Semiconductor device and manufacturing method thereof
JP5110783B2 (en) 2004-10-28 2012-12-26 ルネサスエレクトロニクス株式会社 Semiconductor device
CN111725180A (en) * 2020-07-23 2020-09-29 华虹半导体(无锡)有限公司 Interlayer dielectric layer structure for power MOS device and fabrication method thereof
CN115745417B (en) * 2022-11-08 2024-07-19 福建华佳彩有限公司 Silicon oxynitride film forming method used on indium gallium zinc oxide

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0249173A1 (en) * 1986-06-06 1987-12-16 Rockwell International Corporation A planarization process for double metal mos using spin-on glass as a sacrificial layer
US5003062A (en) * 1990-04-19 1991-03-26 Taiwan Semiconductor Manufacturing Co. Semiconductor planarization process for submicron devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0249173A1 (en) * 1986-06-06 1987-12-16 Rockwell International Corporation A planarization process for double metal mos using spin-on glass as a sacrificial layer
US5003062A (en) * 1990-04-19 1991-03-26 Taiwan Semiconductor Manufacturing Co. Semiconductor planarization process for submicron devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112635329A (en) * 2020-12-14 2021-04-09 华虹半导体(无锡)有限公司 Interlayer dielectric layer of DMOS device and manufacturing method thereof

Also Published As

Publication number Publication date
JP2937886B2 (en) 1999-08-23
JPH09129625A (en) 1997-05-16
GB9619116D0 (en) 1996-10-23
KR970018399A (en) 1997-04-30
KR100197980B1 (en) 1999-06-15
GB2305295A (en) 1997-04-02
DE19637458A1 (en) 1997-03-20

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20100912