GB2304503A

GB2304503A - Data transmission receivers

Info

Publication number: GB2304503A
Application number: GB9517033A
Authority: GB
Inventors: Bipinchandra Patel
Original assignee: Northern Telecom Ltd
Current assignee: Nortel Networks Ltd
Priority date: 1995-08-19
Filing date: 1995-08-19
Publication date: 1997-03-19
Anticipated expiration: 2015-08-19
Also published as: GB2304503B; GB9517033D0

Abstract

A digital data 10 and a receiver 18 for use in a digital data system are disclosed. The receiver unit includes a clock recovery filter or PLL 26 for determining the clock signal. The receiver separates at 20 the data and clock components of the signal to produce at a decision circuit 28 a data output which is correctly sequenced. A single device may incorporate a signal divider 20 a low pass filter 22, and a high pass filter 24. The high pass filter 24 may may suitably be incorporated in a TDM or FDM system. The pilot clock signal impressed upon the incoming data may be an optical pre-chirped signal or other pre-emphasis signal. The data system may use a non-return-to-zero format.

Description

CLOCK RECOVERY SCHEME FOR DATA TRANSMISSION SYSTEMS This invention relates to digital data transmission systems and in particular relates to a clock recovery scheme for use in such systems.

Digital transmission systems almost always transmit signal elements at a uniform rate. Transmission of a digital signal through a transmission medium tends to destroy this uniformity. A signal examined at some point along the transmission path will arrive in a slightly irregular manner. This timing irregularity is frequently referred to as jitter. Jitter can degrade the signal by displacing the effective decision point from the centre of the signal eye and thus lead to a reduction in the signal to noise ratio.

Known systems have attempted to overcome the problems arising as a result of jitter in a variety of ways. One type of system employs a clock signal generator which operates on the data signal at the transmitter. At high data rates an independent clock signal at a receiver may not prove to be sufficiently accurate since the timing/phase error period may correspond to the data rate and thereby destroy the information content of the signal. For complete regeneration of the data transmitter timing signal, it is preferred that this timing signal is extracted from the data signal. This can be carried out by a spectral analysis of the signal and if it contains a discrete component at the pulse repetition frequency it can be assumed that timing information is available and this component may be extracted by a suitable filter and be used to drive a local clock.

However, this sort of spectral analysis is not always appropriate, especially in the case where a non repetitive pulse sequence is being transmitted. Since a random pulse train will have finite components over an infinite time interval, the convergence of the intervals required to perform a Fourier transform analysis are not available. To overcome this problem an autocorrelation function method of analysis can be employed to extract a timing signal employing autocorrelation relationships. This signal is subjected to a non-linear operation. A common technique is to apply the signal to a threshold detector and pulse generator arranged so as to produce a short pulse having an amplitude E and a duration t will otherwise be similar to the original pulse train.Spectral analysis of this signal will show that the output possesses a line spectrum having a fundamental component at the pulse repetition frequency given by:

where T = duration of full width clock pulse period.

Such simple threshold detection systems will not always provide sufficiently accurate results and more extensive non-linear processing is preferable. Mathematically, the results of these operations may be considered to be equivalent to the generation of sum and difference components of the various elements of the signal spectrum. Most of these combine in a random manner but, due to the hidden phase relationships, those being multiples of the pulse repetition frequency tend to add in a systematic way, thus producing the line spectrum. Typically a differentiator, rectifier, threshold detector and short pulse generator are connected in series.

The above described system is not suitable, however, for the generation of regular repetitive trains of clock pulses since they do not contain pulses in every time slot and further operations are required to produce a continuous clock pulse train. These operations can give rise to timing jitter.

The present invention seeks to provide an improved clock recovery arrangement for use in a receiver of a digital data system.

In accordance with one aspect of the invention there is provided a receiver for use in digital data system wherein data is transmitted and a clock signal is impressed upon the data, the receiver comprising a signal divider, a data filter for data extraction, a clock recovery filter for extracting the clock signal and a decision circuit, wherein the decision circuit receives an output from the data filter and an output from the clock recovery filter whereby the data output by the decision circuit is correctly sequenced.The data recovery filter may be a low pass filter, which can operate with a high pass filter to remove noise: the clock signal can be determined by a band pass filter.Such a low pass filter could be combined with the signal divider, a high pass filter and clock recovery filter to provide a device having a single input and two outputs, one output providing the signal data and the other output providing the reference clock, both outputs being directed to a decision circuit.

In one embodiment, the receiver is employed in a digital data system which is operable to directly demultiplex TDM data, the decision circuit in the receiver including a number of sub-circuits to demultiplex each channel.

In another embodiment, the receiver is employed in a digital data system which is operable to transmit WDM signals or FDM signals, the decision circuit in the receiver including a number of sub-circuits corresponding in number to the WDM or FDM signal multiple, each sub-receiver being supplied with appropriate signals from the wavelength division demultiplexer or frequency division demultiplexer which is connected to the clock recovery filter, whereby each sub-circuit samples a single data signal.

The receiver accordingly can operate on a multi-signal basis, wherein a clock signal is impressed only on one transmitted signal, which signal is extracted by only one clock extraction filter, the output of which is communicated with all decision circuits in the receiver. The data transmitter can include a clock signal generator which produces a chirped or prechirped signal for the dual purpose of improving transmission through the medium and for providing a reference clock for the receiver.

In accordance with one embodiment of the invention the low and high pass filters are combined together. The use of a combined low pass/high pass filter structure can improve the impedance match between the receiver front end and decision circuit and can result in lower patterning penalties. Such features are especially beneficial in high bit rate receivers. In order to provide a more detailed understanding of the invention, reference will now be made to Figures as shown on the accompanying drawing sheets, wherein:: Figure 1 shows a digital data transmission system using a pilot clock for providing a reference clock in the receiver; Figure 2 shows a frequency v amplitude representation of the data signal of Figure 1 with a pilot clock signal; Figure 3 shows an implementation of a circuit operable to provide a combined low pass filter and high pass filter; Figure 4 shows a simple implementation of a circuit operable to provide a combined low pass filter and clock recovery filter; Figure 5 shows a TDM signal digital transmission system using the pilot clock for data demultiplexing; Figure 6 shows a representation of the TDM signal of Figure 5 in the time domain; and Figure 7 shows a WDM (FDM) digital transmission system using a single pilot clock for providing a reference clock for the receivers for all channels.

Referring now to Figure 1, reference numeral 10 indicates generally a transmission system comprising a transmitter 12, which transmits digital data through a transmission medium 16 and a receiver 18. A clock signal generator 14 impresses a clock signal upon the data as it is transmitted.

Preferably the clock signal is of low amplitude relative to the data signal i.e. it is a pilot clock signal, whereby the clock signal does not corrupt the data signal. The input of the receiver 18 comprises a divider 20 which divides the signal into two arms. A first arm inputs a signal portion to a low pass filter 22 in order to determine data relating to the message and a second arm inputs a signal portion into a high pass filter 24 in order to determine the input clock signal. The high pass filter 24 outputs into a high-Q phase lock loop (PLL) or clock recovery filter 26 to generate a component at the transmitter clock frequency. A decision circuit 28 then receives data from the low pass filter 22 and from the clock recovery filter and determines the information by arranging the data relating to the message in a correctly timed sequence. Optionally, the divider receives an input from a receiver front end amplifier.

Figure 2 shows a data signal in a frequency v amplitude format, with the data signal DS being transmitted at a particular bit rate, eg 10Gbit/s, and a pilot clock signal TS being transmitted at a bit rate frequency outside the data spectrum. Accordingly the data content of the signal can be extracted by a low pass filter 22 with the clock signal data being extracted by a high pass filter 24. Figure 3 shows a simple implementation of a circuit where a signal is divided by a signal splitter 20, with one path leading to a high pass filter 24 and then towards a clock recovery filter, and the other path leading to a low pass filter 22 in order that information can be extracted therefrom. Provided that the signal is divided cleanly, a high pass filter is not strictly necessary and the clock recovery filter may receive an input directly from the divider, as shown in Figure 4.

The low pass filter and high pass filter (or CRF) can be an integrated design to improve the impedance match between the receiver front end and the following circuit. This means that there is a reduction in patterning penalties in the extraction of the data: the eye of the data signals in the data stream is more clearly defined due to a reduction in mismatch. The integrated filter design can also be more easily implemented, with a single device having a single input and two outputs.

The pilot clock signal can be an optical prechirped signal or other equivalent pre-emphasis signal, applied at the transmitter to improve the quality of the transmission through the medium 16.

Referring now to Figure 5, reference numeral 50 indicates generally a transmission system comprising a transmitter 12, which transmits n-TDM digital data signals (with n = 4 in this figure), through a transmission medium 16 and a receiver 18. A pilot clock signal generator 14 impresses a pilot clock signal upon the data as it is transmitted. The input of the receiver 18 comprises a divider 20 which divides the data into two arms.

A first arm inputs a signal portion to a low pass filter 22 in order to determine data relating to the message and a second arm inputs a signal portion into clock recovery filter 26 in order to determine the input clock signal. The output of the clock recovery filter is fed into a divide by N circuit which produces a reference clock signal at 1/Nth of the original clock frequency. This method of dividing the recovered clock down and using it to directly demultiplex the incoming data allows for the possibility of employing a very high bit rate ( > 10Gbitis). Data from the low pass filter 22 is separated out in the time domain in the decision circuit 28 comprising several decision sub-circuits 52a - 52n, each sub-circuit 52a - 52n being dedicated to one of the n-TDM signals.The decision sub-circuits 52 are operated under the control of auto-phase-alignment devices 54a - 54n whereby correctly sequenced TDM data signals are provided at the output.

The auto-phase-alignment devices 54 are fed with the divided down reference clock frequency. Alternatively, if a clock signal was impressed at 1myth of the bit rate, then the divide by N circuit need not be present.

The data signal of the apparatus of Figure 5 is in TDM format, as best represented in Figure 6 where the multiple data signals of Figure 5 are shown in the time domain.

The present invention is also suited for use in wavelength (frequency) division multiplexed systems, provided the data is synchronous in all the channels. Typically, in such a system, the signals differ in wavelength by 2nm and the range of operating wavelengths can be eg 1550nm, 1 552nm Signals for each wavelength (frequency) are treated separately, the signals of different wavelength (frequency) being separated by wavelength (frequency) division multiplexers, as is known.

Only one clock recovery circuit would then be required for all the frequency channels if auto-phase alignment of the clock signal with respect to the data signal in each channel was employed, and only one transmission channel would require the clock signal to be impressed upon it. Future developments are expected to employ synchronous digital trunk traffic, and such a feature could be especially important.

Referring now to Figure 7, there is shown a wavelength division multiplexed system 70 with a multiplexer/transmitter 72 having a number of input channels 12a - 12n and a single clock input 14. The pilot clock signal need only be impressed on a single channel eg 12a. After transmission through a transmission medium 16 the demultiplexer 74 assigns the channel carrying the data to receiver units 18a -18n. The receiver unit 18a comprises a divider 20, a low pass filter 22, a high pass filter 24 connected to a clock recovery filter 26 and a decision circuit 28a.

The clock signal from 26 is also fed to the other decision circuits 28b - 28n whereby correctly sequenced data is output from all outputs 28a - 28n.

The use of only one transmission channel for the carrying of the clock signal and recovering it simplifies the electronic circuitry employed considerably. Low pass filters could also be configured to provide gain. The present invention is suited to digital data systems, especially those using a non-retum-to-zero format and, in particular, high bit rate optical transmission systems where an optical preamplifier is used. This is because the optical pre-amplifier takes the place of some electronic circuitry which allows high bit rates to be reliably maintained. A further advantage is that the clock recovery filter could be of lower specification with an attendant financial saving.

In systems employing clock prechirp, the prechirp signal can be used for clock recovery. A further advantage of the present invention is that in optical systems, the receiver performance can be improved through the reduced impact of patterning, by employing a combined low pass/high pass filter or a combined low pass/clock recovery filter design.

Claims

1. A receiver for use in a digital data system wherein data is transmitted and a clock signal is impressed upon the data, the receiver comprising a signal divider, a data filter for data extraction, a clock recovery filter for determining the clock signal and a decision circuit, wherein the decision circuit receives an output from the data filter and an output from the clock recovery filter whereby the data output by the decision circuit is correctly sequenced.

2. A receiver as claimed in claim 1, wherein the data filter is combined with the signal divider and a high pass filter and a clock recovery filter, the combined device having a single input and two outputs, one output providing the signal data and the other output providing the clock data, both outputs being directed to a decision circuit.

3. A receiver as claimed in claim 1 or 2 wherein data filter is a low pass filter and the clock recovery filter is a band pass filter.

4. A digital data system according to claims 1 to 3 wherein the data transmitter includes a clock signal generator which produces a chirped or prechirped signal, whereby transmission through the medium is improved and a reference clock for the receiver is provided.

5. A receiver according to claims 1 to 4 wherein the digital data system is operable to transmit TDM signals, the decision circuit in the receiver including a number of sub-circuits corresponding in number to number of demultiplexed channels, each sub-circuit operable under the control of an auto-phase alignment device which is operably connected to the divided down recovered clock signal, whereby each sub-circuit samples a single demultiplexed data signal.

6. A receiver according to claims 1 to 5 wherein the digital data system is operable to transmit WDM signals, the decision circuit in the receiver including a number of sub-circuits corresponding in number to the WDM signal multiple, each sub-circuit fed with the appropriate output of a wavelength division multiplexer, wherein only one channel has a pilot clock signal impressed upon it and only the corresponding receiver requiring a clock recovery filter, wherefrom the other receiver units determine the recovered clock.

7. A receiver according to claim 4 operable in a multi-signal basis, wherein a clock signal is impressed only on one transmitted signal, which signal is extracted by only one clock extraction filter, the output of which is communicated with all decision circuits in the receiver and used to directly demultiplex the incoming data.

8. A digital data system comprising a data transmitter including a clock signal generator; a transmission medium and a data receiver wherein the data receiver comprises a receiver according to any one of claims 1 to 6.

9. A receiver for use in a digital data system substantially as described herein with reference to Figures 1 to 7 of the accompanying drawing sheet.

10. A digital data system substantially as described herein with reference to Figures 1 to 7 of the accompanying drawing sheet.

11. A method of extracting data transmitted through a receiver in a digital data system according to any one of claims 1 to 10 wherein data is transmitted and a clock signal is impressed upon the data; the method comprising the steps: inputting a data signal to the receiver; dividing the signal such to provide inputs to a data extraction filter and a clock signal recovery filter; extracting the data from the signal by means of a data recovery filter; extracting the clock signal from the signal by means,and; passing the data and clock signals to a decision circuit; whereby the data output by the decision circuit is correctly sequenced.