GB2302780A

GB2302780A - Packet switching using a hardware router and FIFO proceedure

Info

Publication number: GB2302780A
Application number: GB9613258A
Authority: GB
Inventors: Yoon-Jong Yeom; Seong-Ho Jeon
Original assignee: Hyundai Electronics Industries Co Ltd
Current assignee: SK Hynix Inc
Priority date: 1995-06-28
Filing date: 1996-06-25
Publication date: 1997-01-29
Anticipated expiration: 2016-06-25
Also published as: CN1114301C; GB2302780B; CN1139852A; KR0180774B1; JPH09107379A; GB9613258D0; KR970004520A

Abstract

A packet data transmitting apparatus and a method therefor are disclosed in which a hardware router transmits and receives packet data without utilizing a central processing unit. By utilizing a hardware router, the destination address is detected from the packet data. Then the packet data are transmitted in accordance with the detected destination address. That is, the hardware router designates respective nodes in a sequential manner, and confirms the existence or absence of the packet data to be transmitted. Then the destination address is extracted from the packet data to be transmitted so as to discriminate the transmitting nodes. Thus a transmission path is provided between the transmitting nodes and the receiving nodes. Therefore, without using the central processing unit, the packet data can be communicated with hardware, with the result that the central processing unit is not over-loaded. Consequently, the performance of the central processing unit is improved, and the processing speed of the system is improved. Therefore, the present invention can be applied to a system requiring a multitasking, and to a system requiring a high speed accurate routing.

Description

PACKET DATA TRANSMITTING APPARATUS, AND METHOD THEREFOR BACKGROUND OF THE INVENTION 1. Field of the invention The present invention relates to a packet data transmitting apparatus a method there for, in which packet data consisting of packets as the unit are transmitted to the destination by using a hardware router.

2. Description of the prior art As the method of transmitting data, there are a line exchange method and a packet transmitting method.

The line exchange method is mostly used, for example, in the electronic switching method. In this method, communication lines are installed, so that the data would not be delayed but would be transmitted with real time.

However, in the line exchange method, the line occupies for transmitting the data, and therefore, it happens that the lines cannot be effectively used. Further, the communication expense shows severe differences depending on the magnitude of the communication distance. Further, the communication becomes impossible if the other end has a different communication speed.

On the other hand, the packet method carries out the data transmission by dividing the data into packet units, and is used mostly in the system like the CDMA (code division multiple access) in which control signals and data are exchanged between the communicating parties.

The packet consists of a data unit formed in a predetermined length, and the address of the other communicating party.

In this packet transmitting method, when data are transmitted, a line does not have to be occupied, and therefore, the line can be used effectively. Further the communication becomes possible even if the other party has a different communication speed.

FIG. 1 illustrates a conventional packet data transmitting apparatus.

As shown in FIG. 1, the conventional packet data transmitting apparatus includes: a serial/parallel converting section 100 for converting the incoming serial data into a parallel data; a central processing unit 101 for temporarily storing the output packet parallel data of the serial/parallel converting section 100, and for detecting an address information so as to convert the logical address into a physical address; a buffer 102 for storing the output parallel packet data from the central processing unit so as to output them in the FIFO (first in first out) method; a hardware router 103 for transmitting the output parallel packet data to the relevant destination; and another buffer 104 for storing the packet data transmitted from the hardware router 103 so as to output them in the FIFO method.

In the conventional packet data transmitting apparatus, the serial packet data which are received from the external are converted into parallel packet data by the serial/parallel converting section 100. Then the central processing unit 101 receives the data to store them into the internal memory lOlA in a sequential manner.

The parallel packet data which have been stored in the internal memory lOlA are sequentially read by the central processing unit 101 so as to detect the address information from the packet data. Then the central processing unit 101 converts the logical address to a physical address before outputting it.

The parallel data which have been outputted from the central processing unit 101 are stored in the buffer 102, and are outputted in the FIFO method.

The parallel output data which are outputted from the buffer 102 are inputted into the hardware router 103, and are stored into the buffer 104 of the destination. Then they are outputted in the FIFO method to be transmitted to the destination.

In this conventional packet data transmitting apparatus, the central processing unit reads the destination address of the received data so as to transmit the packet data to the destination.

Therefore, in a system requiring a multitasking, an over-load is imposed on the central processing unit, thereby lowering the operating performance. In the case where a large amount of packet data is inputted into the central processing unit, errors are liable to occur due to the over-load on the central processing unit.

Further, the central processing unit tackles one by one in detecting the address information of the packet data, and therefore, the peripheral circuits of the central processing unit becomes complicated.

SUMMARY OF THE INVENTION The present invention is intended to overcome the above described disadvantages of the conventional technique.

Therefore it is the object of the present invention to provide a packet data transmitting apparatus and a method therefor, in which the destination address of the packet data is detected by using a hardware router, and the packet data are transmitted based on the detected destination address.

In achieving the above object, a hardware router designates respective nodes in a sequential manner to confirm the existence or absence of the packet data to be transmitted, and a destination address is detected from the packet data of the transmitting node so as to discriminate the receiving node.

Therefore, according to the present invention, even without an intervention of the central processing unit, a transmission path is provided for the packet data transmitting node and the receiving node, thereby making it possible to carry out a hardware type packet data communication.

BRIEF DESCRIPTION OF THE DRAWINGS The above object and other advantages of the present invention will become more apparent by describing in detail the preferred embodiment of the present invention with reference to the attached drawings in which: FIG. 1 is a block diagram showing the constitution of the conventional packet data transmitting apparatus; FIG. 2 is a block diagram showing the constitution of the packet data transmitting apparatus according to the present invention; FIG. 3 illustrates in detail the hardware router of FIG.2; FIG. 4 is a signal flow chart showing the operation of a packet data checking section of FIG. 3 for the packet data transmitting method according to the present invention; and FIG. 5 is a signal flow chart showing the operation of a packet data transmitting section of FIG. 3 for the packet data transmitting method according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The packet data transmitting apparatus and method of present invention will be described in detail referring to FIGs. 2 to 5.

FIG. 2 is a block diagram showing the constitution of the packet data transmitting apparatus according to the present invention.

As shown in this drawing, the packet data transmitting apparatus according to the present invention includes: nodes 200, 201 , 20N; a hardware router 210 disposed between the nodes 200, 201 , 20N, for detecting a destination address from packet data received from the nodes 200, 201, 20N so as to transmit it to the destination; transmitting buffers 220, 221, ..., 22N for storing the packet data received from the nodes 200, 201, ..., 20N so as to input them into the hardware router 210 in the FIFO method; and receiving buffers 230, 231, ..., 23N for receiving the packet data from the hardware router 210 so as to output them in the FIFO method and to input them into the transmitting buffers 220, 221, .., 22N.

As shown in FIG. 3, the hardware router 210 includes: a packet data checking section 210A for checking as to the existence or absence of the packet data to be transmitted by the respective nodes 200, 201, ..., 20N; an address detecting section 210B for detecting the destination address contained in the packet data which have been checked by the packet data checking section 210A; and a packet data transmitting section 210C for transmitting the packet data to the destination in accordance with the destination address detected by the address detecting section 210B.

In the present invention constituted as described above, as shown in FIG. 4, the packet data checking section 210A of the hardware router 210 first designates the nodes 200, 201, ..., 20N in a sequential manner at a step S100, and then, confirms as to the existence or absence of the packet data to be transmitted at a step S110.

That is, based on the packet data which are inputted from the nodes 200, 201,..., 20N through the transmitting buffers 220, 221,..., 22N, a judgment is made as to whether there are packet data in other nodes 200, 201, ..., 20N.

If there is no packet data to be transmitted, then the next nodes 200, 201, ..., 20N are designated, and in this way, checking operations are repeated to check as to whether there are other packet data to be transmitted.

If there are packet data to be transmitted, the relevant addresses which are assigned to the nodes 200, 201, ..., 20N having the packet data to be transmitted are designated at a step S120. Then a packet data transmission request is made to the packet data transmitting section 210C at a step S130. Then the time setting, during which the packet data transmitting section 210C recognizes the packet data transmission request, is delayed at a step S140.

When the time setting has elapsed, the packet data checking section 210A judges as to whether a packet data transmission request recognition signal has inputted from the packet data transmitting section 210C, at a step S150.

If the packet data transmission request recognition signal has been inputted, the next nodes 200, 201, ..., 20N are designated in the above described manner, and in this way, the checking operations are repeated to check as to the existence or absence of the packet data to be transmitted.

If the packet data transmission recognition signal has not been inputted, then it is judged that an error has occurred at a step S160. Therefore, the occurrence of an error in the packet data transmitting section 210C is reported to a central processing unit (not shown in the drawing). Then the next nodes 200, ..., 20N are designated, and in this way, the checking operations are repeated to check as to the existence or absence of the packet data to be transmitted.

As shown in FIG. 5, the packet data transmitting section 210C of the hardware router 210 outputs a transmission recognition signal to the packet data checking section 210A at a step S210, if the packet data checking section 210A inputs a packet data transmission request signal at a step S200. Further, the address detecting section 210B detects a destination address from the packet data.

That is, the address detecting section 210B inputs the packet data to be transmitted (transmitted through the transmitting buffers 220, 221,..., 22N) into a 9-byte shift register (not shown in the drawings) to carry out 3 shifts one by one so as to detect the destination address.

That is, generally, a packet data to be transmitted stores its destination address in the third byte, and therefore, the address detecting section 210B detects the destination address by shifting the packet data by three bytes.

When the address detecting section detects the destination address from the packet data to be transmitted, the packet data transmitting section 210C stores the detected destination address at a step S230.

Then at a step S240, the packet data to be transmitted are stored one byte by one byte into the receiving buffer 230 or the receiving buffers 231, 232, ...,23N which are designated by the destination address. Then the packet data are transmitted to the node 200 or to the nodes 201, 202,...,20N.

Here, one byte of the transmitted packet data consists of 8 bits, while the receiving buffers consist respectively of 9 bits. Therefore, when transmitting the packet data, the packet data transmitting section 210C adds one parity bit to each byte, and then, transmits the packet data to the receiving buffers 230, 231,..., 23N.

When one byte of the packet data has been transmitted to the destination, the packet data transmitting section 210C judges as to whether all the packet data have been transmitted at a step 5250.

In the case where all the packet data have been transmitted, and where the end of the packet data has been arrived, the three bytes, which have been shifted for detecting the destination address, and which have been left in the address detecting section 210B, are transmitted through the receiving buffers 230, 231,..., 23N at a step S260.

Then at a step S270, the transmitting operation for the packet data is terminated.

According to the present invention as described above, the hardware router directly detects the destination address from the packet data to be transmitted so as to transmit the packet data to the relevant nodes. Therefore, an over-load is not imposed on the central processing unit.

Therefore, the operational performance of the central processing unit is improved, with the result that the processing speed of the system is improved. Therefore, the present invention can be applied to a system requiring a multitasking, and to a system requiring an accurate high speed packet routing.

Claims

WHAT IS CLAIMED IS:

1. A packet data transmitting apparatus comprising: nodes for transmitting packet data in a bilateral manner; a hardware router disposed between said nodes, for detecting a destination address from packet data received from said nodes so as to transmit it to the destination; transmitting buffers for storing the packet data received from said nodes so as to input them into said hardware router in an FIFO method; and receiving buffers for receiving the packet data from said hardware router so as to output them in an FIFO method and to input them into said transmitting buffers.

2. The packet data transmitting apparatus as claimed in claim 1, wherein said hardware router comprises: a packet data checking section for checking as to the existence or absence of the packet data to be transmitted by said respective nodes; an address detecting section for detecting the destination address contained in the packet data which have been checked by said packet data checking section; and a packet data transmitting section for transmitting the packet data to the destination in accordance with the destination address detected by said address detecting sect ion.

3. A method for transmitting packet data, comprising the routines of: checking respective nodes for making a packet data transmission request upon finding a packet data to be transmitted (packet checking routine); detecting a destination address from a packet data for which a transmission request is made at the packet checking routine (address detecting routine); and transmitting the packet data in accordance with the destination address detected at the address detecting routine, upon finding a packet data transmission request from the packet checking routine (packet transmitting routine).

4. The method as claimed in claim 3, wherein the packet checking routine comprises the steps of: designating said nodes in a sequential manner, and checking the existence or absence of a packet data to be transmitted (first step); repeating the first step upon finding no packet data to be transmitted at the first step (second step); storing relevant addresses assigned to said nodes, making a transmission request, making a time delay for recognizing the packet data transmission request, and making a judgment as to whether the packet data transmission request has been recognized, if there is a packet data to be transmitted at the first step (third step);; and repeating the first step upon recognizing the packet data transmission request at the third step, and reporting an occurrence of error and repeating the first step upon failing a recognition of the packet data transmission request (fourth step).

5. The method as claimed in claim 3, wherein the packet data transmitting routine comprises the steps of: generating a transmission confirming signal, and storing the destination address of the address detecting routine, upon receiving a transmission request signal (first step); transmitting the packet data by byte by byte to the destination accordance with the destination address of the first step (second step); and transmitting the shifted three bytes of the packet data (shifted for detecting the address at the address detecting routine) (third step).

6. The method as claimed in claim 5, wherein, at the step 2, the packet data are transmitted after adding one parity bit to each byte of the packet data.

7. The method as claimed in claim 3, wherein, at the address detecting routine, the packet data to be transmitted are shifted 3 times byte by byte so as to detect the destination address.