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GB2301937A - IC package with a ball grid array on a single layer ceramic substrate - Google Patents

IC package with a ball grid array on a single layer ceramic substrate Download PDF

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Publication number
GB2301937A
GB2301937A GB9611726A GB9611726A GB2301937A GB 2301937 A GB2301937 A GB 2301937A GB 9611726 A GB9611726 A GB 9611726A GB 9611726 A GB9611726 A GB 9611726A GB 2301937 A GB2301937 A GB 2301937A
Authority
GB
United Kingdom
Prior art keywords
integrated circuit
digital integrated
circuit package
package
vias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9611726A
Other versions
GB9611726D0 (en
Inventor
Norman L Greenman
M P Ramachandra Panicker
Jorge M Hernandez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Circuit Components Inc
Original Assignee
Circuit Components Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Circuit Components Inc filed Critical Circuit Components Inc
Publication of GB9611726D0 publication Critical patent/GB9611726D0/en
Publication of GB2301937A publication Critical patent/GB2301937A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
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    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

A Digital Integrated Circuit Package is disclosed which exhibits a large input/output (10) capability while maintaining a small footprint. The package employs a Ball Grid Array (BGA) format and a single layer ceramic substrate with bimetallic filled precisely positioned vias 22, 25. Some of the vias 25 are located for heat conduction from a die 30. The conductive balls 17 of the array may be of copper or lead/tin solder. A protective layer 31 is provided outside a cover 32. In other arrangements the die is encapsulated in epoxy material, and the die may be flip-mounted with the cover extending to the edge of the substrate.

Description

A HIGH PERFORMANCE DIGITAL IC PACKAGE, USING BGA (BALL GRID ARRAY) pO FORMAT, AND SINGLE LAYER CERAMIC SUBSTRATE WITH BIMETALLIC FILLED VIA TECHNOLOGY Cross-Reface@ce @@ Rela@ed Application; This is a contioustion-in-part of U.S. Pat@nt Application Serial No. 08/398.586 @@ed Mrcb 2. 1993.
Back@round of the Invention: Field of the Invention This invention rclales to the field of single and multiple chip packages for digital integrated circuits. More particularly, this invention relates to a single layer ceramic substrate supporting a multiplicity of bi-metallic or tri-metallic vias connected to a Ball Grid array, to promote a larger number of connections in a small unit area.
One of todays successful package styles for single and multiple IC chips. uses the BGA (Ball Grid Array) VO fonnat, as opposed to LGA (Land Grid Array). or leaded package styles. This is so because the BGA format is conducive to higher I/O content than a practical leaded package of the same size and it can be easily installed on a PC Board, especially when solder balls are used for the BGA. This is in contrast to an LGA package, which has the same 1/0 density but requires socketing because olherwise assuring the quality of solder joints when the package is mounted flush over the PCB, is extremely difficult, if not impossible.
Among the presently known BGA packages, there are a number of construction schemes with advantages and disadvantages. as follows: BGA packages using ceramic construction employ a multilayer cofired structure.
A multilayer structure is needed because the slirinkage inherent to the process, in addition to the drawbacks of thick film screen printable refractory metal conductive pastes, liniit the physical size (line width and spacing, via capture pad diameters, etc.) of interconnection circuitry required to bring in signals from tlie PC Board lo the IC chip(s) and vice vcrsa. A single ceramic layer lacks suffcient surface area to accommodate the number of traces and pads needed to completely connect the dcsired IC's. l'o alleviale the situation, prior an constructions employed multiple layer construction. Drawbacks are experienced with this method in that as the number of I/O's grows, so does tlie number of layers, if the package size is to be maintained as small as possible.
An increased number of layers (and package size) aggravales the problem of electrical parasitics which adversely alrect the performance of the semiconductor device.
Also, the increased number of layers bring about alignment and registration problems between layers, which are aggravated by the shrinkage of the structure during sintering. Yields of these packages are adversely affected thereby, and costs associaled with produclion of the packages is increased. Generally speaking, multilayer cotired ceramic packages are more expensive than other alternatives.
Anolher type of construction employing glass and ceramic material alleviates to a significant extent, the problem created by shrinkage, since Ilie glass-ceramic material is designed to minimize shrinkage. I however since the circuitry is still screen printed, and screen printing is a process with limited resolulion capability, there is a limit lo the number of traces and pads that caii be accommodaled on a single layer. Therefore, there is still the need for a multilayer structure like that above. As will be appreciated, this translates to higher cost than other alternatives.
In yet another prior art configuration, an epoxy-fiberglass board is patterned on one side to receive the array of solder balls, whereas the opposite surface (or layers) art: circuit patterned using plated through holes for interconnection between layers.
Improved photoresist-etching technology is employed to achieve line widths/spacings in the vicinity of 0.003"-0.004" (75 to 100 mierometers). This is known as Plastic Ball Grid Array construction. There are two sigiiiricant problems with this type of construction: (1) is that as the number of I/O's increases, the cosl of lie package becomes prohibitive, especially if tlie package size is to be kepl to a minimum; (2) is tlial as the 1/0 count increases, so (in general) does the power dissipaled by the IC chip.Because of an inability of the package to dissipate tlie heat generated by the IC chip in an adequate manner these chips are prone to early failurc. For this reason, common commercial devices such as Intel's Pentium Processors wliicli are configured with l'GA ceramic packages must employ fans mounted directly on top of tlie package to remove heat therefrom.
A major problem with ceramic multilayer, glass ceramic and plastic ball grid array constructions is the difficulty in achieving the flatness on tlie two large surfaces of the package, needed for coplanarity of the ball array or for flip chip mounting t the semiconductor device. Cm fired multilayer ceramic structures and PCB laminates have inherent camber problems.
Another problem with multilayer cofired ceramic BGA packages is ilie poor coplanarity of the balls once they are attached to the package, making difficult tlie assembly of the packaged IC. I'lie nominal coplanarity of multilayer ceramic BGA packages is only 0.006", which is considered excessive in the industry. In the package of the present invention, the coplanarity can be tightly controlled.
The package of the present invention alleviates or significantly reduces the problems and limitations of BGA packages of the prior art.
Other prior art includes U.S. Pat. 5,089,881 to Panicker, U.S. Pat. 4,942,216 to Panicker (both of which are fully incorporated herein by reference) and other pin grid array configurations. An exemplary multilayer BGA package is illustraled iii FIGURE 1.
Moreover, Amkor produces a plastic BGA package which uses l'C13 technology to create circuit traces and side-to-side connections.
Summarv of the Invention: The above-discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by the Ball Grid Array IC package of the invention.
The present invention employs a fully sintered ceramic, single layer substrate or other material having similar characteristics. Vias are subsequently laser drilled in a multiplicity of places in a generally regular pattern and witlo both thermal vias and signal/power vias being provided for. Vias are filled with a bi-metallic or tri-metallic composite material. The whole substrate is alien nielalized by a number of alternative methods and metals including thin film titanium, chroiuium, molybdenum, tungsten or a combination thereof, copper and nickel.Pads Inay also be of the copper thick film variety. The balls for the BGA will generally be of a lead/tin alloy and be brazed onto the ball side of substrate.
In order lo more effectively dissipate beat troin the thermal vias a heat spreader pad is metalized over the thermal vias in several methods as outlined above. Pads are also provided around the heat spreader for connection to the wirebonds or flip-chip.
These pads are connected to the appropriate vias by traces approximately 0.002 inch wide widlh spacings therebetween of 0.002 inch.
The metalization of the die attach side of the substrate is as follows: I ) Adhesion promoter bonded to substrate; 2) current carrying material bonded to adhesion promoter; 3) buffer. material bonded to current carrying material; 4) protective finish bonded lo buffer.
Completing the package is accomplished in one of three preferred ways including arranging a metallic or metal plated lid over the die and bonding pads but leaving the protective coaling exposed; arranging a similar lid or ceramic lid to cover the entire substrate, or applying a "blob" of epoxy over tlie die and wirebonds.
The invention provides a niimimally dimensioned package which avoids tloe drawbacks of multiple layering while maintaining a iow cost.
The above-discussed and other features and advantages of the present invention will be appreciated and understood by loose skilled in the art from the following detailed description and drawings.
Brief Description of the Drawings: Referring now to the drawings wherein like elements are numbered alike in tlie several FIGURES: FIGURE I is a cross section view of a prior art multilayer substrate and a ball grid array; FIGURE 2 is a perspective exploded view of one embodiment of the invention; FIGURE 3 is a perspective exploded view of a second embodimenl of tlie invention; FIGURE 4 is a perspective exploded view of a third embodiment of the invention; FIGURE 5 is a sectional view taken along section lines 5-5 in FIGURE 2; FIGURE 6 is a sectional view taken along lines 6-6 in FIGURE 3; FIGURE 7 is a sectional view taken along lines 7-7 in FIGURE 4; FIGURE 8 is an exemplary sectional view of an embodiment employing a flipchip;; FIGURE 9 is a plan view of a substrate with drilled vias where the vias are in a regular pattem; FIGURE 10 is a plan view of a substrate with drill vias where the vias are in an interstitial pattern; FIGURE Il is a schematic view of a substrate of the invention illustraling the layers of metalization on both the die attach side and BGA side; FIGURE 12 is a plan view of the die attach side of the substrate illusirating the trace pattern of the package; FIGURE 13 is a cross section of a package with a size malched ceramic cover.
Detailed Description Of The Preferred Embodiments Referring to FIGURE I a prior art multiple layer Ball Grid Array (BGA) is illustrated in cross section. As will be recognized by one of skill in the art, in order to achieve a sufficient nuniber of balls I for the array, multiple layers 2 of substrate are necessary all of which contribute to tulle drawbacks discussed in the Background of the Invention set forth above.It is these drawbacks, inlet alia, which the present invention solves by maintaining a single layer substrate while providiiig a larger number of inlerconnection sites in the bond of balls in a Ball Grid Array (L3GA).
it should be noted that the basic concepl of the invention is similar throughout tulle following description and that preferred embodiments are merely modifications of the concept. For the ensuing discussion, each of the drawings may be generally referred to.
In the most general descripiion, the iiivei0tion employs a siiigle layer substrate I comprising a fully sintered ceramic material. Preferred materials include but are not limited to Aluminum oxide (Al203), Aluminum Nitride (AIN), Beryllium Oxide (BeO), Boron Nitride (BN), Silicon Carbide (SiC), elc. Known sintering methods are utilized to form this substrate material. Preferred starting thickness of the substrate 10 for use in the invention is approximately 0.040 inch.
Once the substrate 10 is fully prepared, vias 22 and 25 are drilled in a predetermined pattern. It will be appreciated that vias 22, 25 may be drilled by any suitable melhod, however it is prelerred to employ a compuler conlrolled laser to very precisely locale the vias in the predetermined position, r It is preferred to place a large number of thermal vias 25 in a central location on tlie substrate 10, which localion will correspond with the location of tie die 30 to be placed thereon. The thermal vias 25 thus draw heat from the die 30 and cooperate with structures to be discussed hereunder to dissipate the collected heat. Power and signal vias 22 are located along the periphery of the substrate 10. Alternately, power and ground vias can be placed under the chip, especially when the application is for flip cliip die attachment. All vias are generally spaced from each other in columns or rows by about 0.050 inch. In a regular pitch, as illustrated in FIGURE 9, tlie above is tlie oiily dimension between vias. Where aii interstitial pitch is employed, however, it will be recognized from FIGURE 10 that rows and columns are still spaced therealong at about 0.050 inch between vias but since the rows are staggered, the distance between each columnar via in adjacent rows are merely about 0.025 inch apart.This provides for a larger number of vias in a unit area without losing the 0.050 incli clearance between vias in each column or row. Both are fully functional. In nip chip assembly applications, smaller and irregular via pattems are often employed to accommodale the pad layout of the IC die.
Vias 22, 25 are filled witl' preferably a bi-metallic or tri-metallic composite such as with W-Cu or with W-CuAg (wherein the CuAg is an eutectic CuAg alloy). Vias may be filled with these malerials ill ways known per se.
Subsequently to via filling the final thickness of the substrate is achieved by lapping to both the die attach surface II and the ball attach surface 13 and finishing to less than about 2.0 microinch Ra.
Referring to FIGURE I 1, one will appreciale the melalization of lye surfaces of substrate 10. Die attach surface II is depicted on the upper side of substrate 10 in the FIGURE whereas Ball attach surface 13 is depicted on the lower surface of substrate 10 in the FIGURE.
Die attach surface II includes adhesion promoter 6 bonded directly to the ceramic substrate 10. Promoter 6 most preferably comprises thin film Chromium, thin fill litanium or thin film Titanium/l'ungsten, @ l'itanium/Molybdenum in a thickness of approximately 500-2000A, however the promoter may be any material which provides sufficient adhesion to both the ceramic material employed for the substrate and to a current carrier layer 7 which is bonded to the promoter 6. Current carrier 7 most preferably is comprised of copper in a thickness of approximately 5-10 micrometers because of its excellent electrical/conductive properties.Following carrier 7, a buffer 8 is deposited, buffer 8 is commonly nickel in a thin film fonn of about I about 3.5 micrometers in thickness. The buffer is to prevent diffusion of Copper into the final protective finish. Finally, protective finish 9 is added, gold being the preferred material, in a thickness of about 2 about 3.5 micrometers. It should be noted that all metalization layers deposited on die attach surface II as well as on Ball attach surface 13 may be applied by any conventional deposilion method including but not limited to:: sputtering, enhanced ion plating, low temperature Arc Vapor deposilioii.
Where a nip chip is employed it is sometimes desirable to alternatively metalize as follows: promoter approximately 500-2000A; current carrier approximately 5- 10 ; and a layer of chromium of approximately 300-1000 . Ball auache surface (still referring to FIGURE 11) may employ the lirst three layers of metalization of die attach surface or may employ all four layers. The lirst layer is adhesion promoter 14 wliicli is prelerably selected from among the same niaterials of that of promoler 6.Similar to that above, a current carrying layer 15, being preferably copper, is then deposiled over promoter 14 and a third layer is metal 16 which preferably is nickel to provide a good surface for bonding of an AgCu eutectic alloy which is used to attach Balls 17 to the package; a gold protective layer may then be added. Thicknesses of the layers varies for the ball surface as follows: 500-2000A; current carrier 3-5 ; buffer 2-5 and gold 300-2000A. Balls 17 may be Copper, but in most cases Balls 17 will be formed from a solder having a high melting point such as 95% Pb 5% Sn or 90% Pb 10% Sn. In this case metal 16 may be omitted and the balls attached directly to copper layer 15 for good bondability with balls 17, made of solder.
Capture pads 18 are placed upon both surfaces of the substrate 10 in electrical contact with vias 22. It should be noted that while individual vias are generally about 0.006 inch in diameter in the capture pads 18 provide a 0.010 inch diameter area ii) which to attach traces, balls, etc. which is much easier to work with. Caplure pads 18 can be formed by preferably a photoresist-etch process, by pllysical "asking, by a lift-off process, or by a copper thick film paste such as DuPont 9922 nitrogen fireable copper paste.
The die attach surface 11 further includes a die attach area 12 immediately surrounded by a multiplicity of wire bonding pads 19 for electrical attachment of the Die 30 through wire bonds 20 or flip chip attachment pads around the periphery or the underside of the die (not shown).
On BGA surface 13 ofsubstrate 10 a heat sprcader pad 21 is nlelallized usiiig similar metalizalion options as described with respect lo I3GA surface 13.
Referring now to FIGURES 2 and 5 one embodiment of the package is illustrated which includes a passive insulative protection layer 31 to proleclively cover the plurality of circuit traces 5 (see FIGURE 12) in the perimetrical area of substrate 10 which is not covered by lid 32. Layer 31 is preferably glass or epoxy or polyimide but niay be any other adequately electrically insulalive material.
Layer 3 1 does not necessarily extend completely over the entire substrate, rather it defines an opening in the center thereof large enough to expose the die 30 and wire bonding pads 19 or the nip chip contact pads. In order to bond a lid as described hereunder a seal ring 33 is provided alop layer 31 immediately perimetrically adjacent tlie geometrical shape defined by wire bonding pads 19. Seal ring 33 is generally constructed of the same material of which traces 5 are composed, which preferably is gold.
Lid 32 is preferably formed from nickel or Kovar and is nominally deep drawn. It will be understood, however, that oliver methods are available and equally ellective in forming lids. For some applications a gold plating is preferred oil lid 32.
Attachment of lid 32 in the preferred embodiment of IlGURES 2 and 5 is by a conductive epoxy material, solder (Pb/Sn), AuGe brazing alloy material lo bond Ille lid 32 in bonding zone 32a to the sealing ring 33. Oiie of skill in the art will appreciate that other compounds are possible and that those listed are preferred.
In anolher embodiment of the Ilvelitiol) tlie layer 31 is unnecessary due to the lid 34 covering the entire substrate 10. (See FIGURES 3 und 6). Tlie seal ring 35, in this case, is positioned along the outer perimeter of substrate 10 aid outside owt all area defined by the outermost row of vias 22. In other respects tlie lid 34 and zone 34a are as were lid 32 and bonding zone 32a.
A third embodiment, as illustrated in FIGURES 4 and 7, employs the passive insulating protective layer 31 in niucli the same manner as that in the embodiment of FIGURES 2 and 5. This embodiment differs in that instead of adhering a seal ring 33 and lid, a "blob" of epoxy material is placed atop the die and wire bonds thereby protecting them.
A further preferred embodiment is illustrated in FIGURE 13 in cross section wherein a ceramic lid 36 is employed which covers tlie entire package. The preferred materials for creating the lid 36 are the same as can be employed for the substrate, and the lid is preferably metalized on at least one if not both surfaces. l he lid 36 is adhered to substrate 10 by an epoxy adhesive frame on bonding area 37.
The invention in each of the embodiments provides a high input/output (I/O) ralio to the overall size of the package without sacrificing clarity of signal or experiencing manufacturing difficulties (and concomitant cost).
While preferred embodiments have been shown and described, various modifications and substitutions Inay be made thereto without departing from the spirit and scope of the iiivention. Accordingly, it is to be understood that tloc present iiiveiitioii has been described by way of illustration and not limitation.
What is claimed is:

Claims (58)

  1. CLAIM 1. A Digital Integrated Circuit Package comprising: a) a single layer substrate leaving a preselected pattern of vias; b) a multiplicily traces extending from a mulliplicily of at least one of wi@e bonding pads aiid nip chip attachment pads to a multiplicity olvias lo make electrical conlacl therebetween, said traces all beiiig disposed upon said single layer substrate;;
    c) at least one protective structure disposed such that said vias, traces, wire bonding pads, at least one wire bond and at least one die are protected front environmental influence.
    d) a multiplicity of electrically conductive balls disposed upon a second surface of said substrate said surface being opposed to a first surface of said substrate whereupon said at least one die is disposed.
  2. CLAIM 2. A Digital Integrated Circuit Package as claimed in claim I wherein said single layer is of a fully sintered ceramic material.
  3. CLAIM 3. A Digital Integrated Circuit Package as claimed in claim 2 wherein said ceramic material is an aluminum oxide (Al2O3)material. - CLAIM
  4. 4. A Digital Integrated Circuit Package as claimed in claini 2 wherein said ceramic is an aluminum nitride (AIN) material.
    Cl,AIM
  5. 5. A Digital Integrated Circuit Package as claimed in claim I wherein said pattern of vias includes a closely patterned central section for thermal conduction and a peripheral pattern for signal/power.
  6. CLAIM 6. A Digital Integrated Circuit Package as claimed in claim 5 wherein said signal/power vias maintain a columnar and row distance between each via of in the range of about 0.050 to 0.025 inch.
  7. CLAIM 7. A Digital Integrated Circuit Package as claiined in claim 5 wherein said signal/power vias mainlain a column aiid row distance between each via of about 0.050 inch and wherein column to column interstitial spacing is about 0.025 inch.
  8. CLAIM 8. A Digital Integrated Circuit Package as clainied in claim I wherein said traces comprise a layered metalization including an adhesion promoter, current carrier, buffer, and protective layer.
  9. CLAIM 9. A Digital Integrated Circuit Package as claimed in claim 8 wherein said traces are about 0.002 inch in width.
  10. CLAIM 10. A Digital Integrated Circuit Package as claimed in claim I wherein said wire bonding pads comprise a layered metalization including an adhesion promoter, current carrier, buffer, and protective layer.
    CLAIM
  11. II. A Digital Integrated Circuit package as claimed iii claim I wherein said vias are filled with a bi-metallic composition.
  12. CLAIM 12. A Digital Integrated Circuit Package as claimed in claim 11 wherein said bi-metallic composition is Copper-Tungsten.
  13. CLAIM 13. A Digital Integrated Circuit Package as claimed iii claim I wherein said vias are filled with a tri-metallic composition.
  14. CLAIM 14. A Digital Integrated Circuit I'ackage as claimed in claini 11 wherein said tri-metallic composition is Copper-Silver-Tungsten.
  15. CLAIM 15. A Digital Integrated Circuit Package as claimed in claim I wherein said traces are spaced apart from one another by at least about 0.002 inch.
  16. CLAIM 16. A Digital Integrated Circuit Package as claimed in claim I wherein said protective structure comprises a protective coating extendillg from a peripheral edge of said substrate into proximity with said wire bonding pads aiid a cover is bonded to said protective coating and extends over said wire bonding pads, wire bonds and at least oiie die.
  17. CLAIM 17. A Digital Integrated Circuit Package as claimed in claim I wherein said protective structure comprises a cover bonded to an outer periphery of said substrate, said cover extending over the entirety of said package.
  18. CLAIM 18. A Digital Integrated Circuit Package as claimed ii) claim I wherein said protective structure comprises a protective coating extending from an ouler periphery of said substrate to within proximity of said wire bonding pads and wherein a "blob" of epoxy is applied to the package covering part of said protective coating and all of said wire bonding pads, wire bonds and at least one die.
  19. CLAIM 19. A Digital Integrated Circuit Package as claimed in claim 16 wherein said cover is selected from the group consisting of metal and Kovar.
  20. CLAIM 20. A Digital Integrated Circuit Package as claimed iii claim @ 19 wherein sald cover is plated with a conductive metal.
  21. CLAIM 21. A Digital Integrated Circuit Package as claimed in claim 20 wherein said conductive metal is Gold.
  22. CLAIM 22. A Digital Integrated Circuit Package as claimed in claim 17 wherein said cover comprises a ceramic material.
  23. CLAIM 23. A Digital Integrated Circuit package as claimed in claim 22 wherein said ceramic material is Al2O3.
  24. CLAIM 24. A Digital Integrated Circuit Package as claimed in claim 22 wherein said ceramic material is AIN.
  25. CLAIM 25. A Digital Integrated Circuit Package as claimed in claim 17 whereiii said cover is selected from the group consisting of metal and Kovar.
  26. CLAIM 26. A Digital Integrated Circuit Package as claimed in claim 25 wherein said cover is plated with a conductive metal.
  27. CLAIM 27. A Digital Integrated Circuit l'ackage as claimed iii claim 26 wherein said conductive metal is Gold.
  28. CLAIM 28. A Digital Integrated Circuit @ package as claimed in claim 16 wherein said protective coating is glass.
  29. CLAIM 29. A Digital Integrated Circuit Package as claimed in claim 16 wloeieiio said protective coating is polyimide or epoxy.
  30. CLAIM 30. A Digital Integrated Circuit Package as claimed in claini 16 wherein said protective coating is an insulative material.
  31. CLAIM 31. A Digital Integrated Circuit Package as claimed in claim 18 wherein said protective coating is glass.
  32. CLAIM 32. A Digital Integrated Circuit package as claiiiied in claim 18 wherein said protective coating is polyimide.
  33. CLAIM 33. A Digital Integrated Circuit Package as claimed in claim 18 wllerein said protective coating is an insulative material.
  34. CLAIM 34. A Digital Integrated Circuit package as claimed ii) claim I wherein said first surface supports a series of metalizatioiis including an adhesion promoter, a current carrier, a buffer and a protective finish.
  35. CLAIM 35. A Digital Integrated Circuit Package as claiiioed in claim 34 wherein said prollioter is selected from the group consisting of titaniuioi, chromium, an alloy of litanium/tungsten and an alloy of titanium/molybdenum CLAIM
  36. 36. A Digital Integraled Circuit Package as claimed in claim 35 wherein said promoter is of a thickness of about 500 to about 2000 Angstroms.
  37. CLAIM 37. A Digital Integrated Circuit Package as claimed in claim 34 wherein said current carrier is copper.
  38. CLAIM 38. A Digital Integrated Circuit Package as claimed in claim 37 wherein said copper is in a thickness of about 5 to about 10 micrometers.
  39. CLAIM 39. A Digital Integrated Circuit Package as claimed in claim 34 wherein said buffer is nickel.
  40. CLAIM 40. A Digital Integrated Circuit Package as claimed in claim 39 wherein said nickel is in a thickness of about I to about 3.5 micrometers.
  41. CLAIM 41. A Digital Integrated Circuit Package as claimed in claim 34 wherein said protective finish is gold.
  42. CLAIM 42. A Digital Integrated Circuit l'ackage as claimed in claim 4 1 wllereill said gold is of a thickness of about 2 to about 3.5 micrometers.
  43. CLAIM 43. A Digital Integrated Circuit Package as claimed in claim I wherein said second surface supports a series of metalizations including an adhesion promoter, current carrier and a protective layer.
  44. CLAIM 44. A Digital Integrated Circuit Package as claimed in claim 43 whereiii said adhesion promoler is selected from the group consisting of titanium. chron'iuin, an all my of titanium/tungsten and an alloy of titanium/molybdenum.
  45. CLAIM 45. A Digital Integrated Circuit Package as clainled in claim 44 wherein said promoter is of a thickness of about 500 to about 2000 Angstroms.
  46. CLAIM 46. A Digital Integrated Circuit Package as claimed in claim 43 wtierein said current carrier is copper.
  47. CLAIM 47. A Digital Integrated Circuit Package as claimed in claim 46 wherein said copper is in a thickness of about 3-5 .
  48. CLAIM 48. A Digital Integrated Circuit package as claimed in claim 39 wherein said buffer is nickel.
  49. CLAIM 49. A Digital Integrated Circuit Package as claimed in claim 48 wherein said nickel is in a thickness of about 2.0-5 .
  50. CLAIM 50. A Digital Integrated Circuit Package as claimed in claim 43 wherein said protective finish is gold.
    CLAIM
  51. 5 1. A Digital Integrated Circuit Package as claimed in claim 5() wliereiii said gold is of a thickness of about 300-2000A.
  52. CLAIM 52. A Digital Integrated Circuit package as claimed ii) claim I wherein said first surface supports a series of metalizations including an adhesion promoler, a current carrier, and a top metalization.
  53. CLAIM 53. A Digital Integrated Circuit Package as claimed in claim 52 wherein siid promoter is selected from the group consisting of titanium, chromium, an alloy of titanium/tungsten and an alloy of titanium/molybdenum.
  54. CLAIM 54. A Digital Integrated Circuit Package as claimed in claim 53 wliereiio said promoter is of a thickness of about 500 to about 2000 Angstroms.
  55. CLAIM 55. A Digital Integrated Circuit Package as claimed in claim 52 wherein said current carrier is copper.
  56. CLAIM 56. A Digital Integrated Circuit l'ackage as claimed in claim 55 wliereiii said copper is in a thickness of about 5 to about 10 micrometers.
  57. CLAIM 57. A Digital Integrated Circuit Package as claimed in claim 52 wherein said top metalization is chromium.
  58. CLAIM 58. A Digital Integrated Circuit Package as claimed in claim 57 wliereiii said chromium is of a thickness of about 300-1 ouuA.
    CLAIM 59 A Digital Integrated Circuit Package substantially as hereinbefore described with reference to any one of Figures 2 to 13
GB9611726A 1995-06-06 1996-06-05 IC package with a ball grid array on a single layer ceramic substrate Withdrawn GB2301937A (en)

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GB2377080A (en) * 2001-09-11 2002-12-31 Sendo Int Ltd Integrated circuit package and printed circuit board arrangement

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US6284566B1 (en) 1996-05-17 2001-09-04 National Semiconductor Corporation Chip scale package and method for manufacture thereof
US6140708A (en) * 1996-05-17 2000-10-31 National Semiconductor Corporation Chip scale package and method for manufacture thereof
GB9818474D0 (en) * 1998-08-26 1998-10-21 Hughes John E Multi-layer interconnect package for optical devices & standard semiconductor chips
US6198166B1 (en) * 1999-07-01 2001-03-06 Intersil Corporation Power semiconductor mounting package containing ball grid array
DE10010461A1 (en) * 2000-03-03 2001-09-13 Infineon Technologies Ag Process for packing electronic components comprises injection molding components into ceramic substrate having conducting pathways, contact connection surfaces and pressure contacts
JP6397806B2 (en) 2015-09-11 2018-09-26 東芝メモリ株式会社 Semiconductor device manufacturing method and semiconductor device

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GB2377080A (en) * 2001-09-11 2002-12-31 Sendo Int Ltd Integrated circuit package and printed circuit board arrangement
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KR970003879A (en) 1997-01-29
TW299487B (en) 1997-03-01
MXPA96002171A (en) 2002-04-19
JPH09213829A (en) 1997-08-15
DE19622650A1 (en) 1996-12-12

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