GB2294584A

GB2294584A - High-voltage transistor

Info

Publication number: GB2294584A
Application number: GB9421789A
Authority: GB
Inventors: David Arthur Garnham
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 1994-10-28
Filing date: 1994-10-28
Publication date: 1996-05-01
Anticipated expiration: 2014-10-28
Also published as: GB2294584B

Abstract

A high voltage transistor comprises an emitter 30 of a first conductivity type, a base 28 of a second conductivity type having at least one deep region 22 of a predetermined radius of curvature, and a collector 24 of the first conductivity type profiled such that the separation d between the base and collector regions is substantially constant. The radius of curvature of region 22 is a function of the required operating voltage of the transistor. The collector 24 is formed by diffusion of phosphorus. <IMAGE>

Description

IMPROVEMENTS IN OR RELATING TO TRANSISTORS This invention relates to an improved transistor, in particular to a transistor having improved high voltage performance.

A typical planar transistor has a collector, an emitter and a base. An example of a high voltage planar transistor is a 1500V BVCBO (breakdown voltage between collector and base with the emitter open). Design of transistors having this level of operating voltage is fraught with difficulties.

There is often a pay off between the size of the device and the optimum operating characteristics. Obviously, this is not always an easy problem to resolve.

In the past the N+ diffusion has been designed to be the same penetration over the whole of the wafers collector region. To withstand the 1500V collector base voltage the radius of the curvature of the base region (the P-region in Figure 1) has to be increased. Following on from this the thickness of the intrinsic N type region between the N+ penetration and Ppenetration ends up wider than required (d+8) over much of the device. This results in a thicker and bulkier device and in higher than expect VCESAT loses. The prior art device is shown in Figure 1.

One object of the present invention is to provide a high voltage transistor which suffers from at least less of the problems found in the prior art.

According to one aspect of the present invention, there is provided a high voltage transistor comprising an emitter of a first conductivity type; a base of a second conductivity type having at least one deep region of a predetermined radius of curvature; and a collector of the first conductivity type profiled such that the separation between the base and collector regions is substantially constant.

According to a second aspect of the present invention, there is provided a method of forming a high voltage transistor, comprising the steps of: forming a base of a second conductivity type, the base having at least one deep region of a predetermined radius of curvature which is radius is determined by the operating voltage; and forming a collector of the first conductivity type having a profile such that the separation between the base and collector is substantially constant.

The invention has the advantage that both the overall size of the device and the VCESAT performance are optimised on the same device. This minimises the amount of silicon used and thus further produces a cost reduction.

Reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 is a cross sectional view of a prior art device; Figure 2 is a cross sectional view of a device according to one aspect of the invention; and Figures 3a-3h are cross sectional diagrams for illustrating how the device of Figure 2 is fabricated.

Referring to Figure 2, a high voltage device 20 is shown. The device includes a Deep P-region (22) having a radius of curvature which dictates the operating voltage and a profiled N+ region (24). The thickness of the intrinsic N layer (26) is constant for the whole of the device due to the profiled N+ region, thereby ensuring the VCESAT loses are minimised. The base (28) and emitter (30) function conventionally.

Referring to Figure 3a to 3h, the structure shown in Figure 2 can be fabricated by the following method.

A silicon wafer 30 is oxidised at about 1100 C to produce an upper and lower oxidation (32 and 34) which have a nominal thickness of about 1.3 llm.

This is shown in Figure 3a.

Initially, fabrication is carried out on the lower surface of the wafer.

The oxide layer 34 is patterned and removed to expose a silicon window 36 as shown in Figure 3b. Next a phosphorous deposition is carried out at about 120000 for about 240 minutes. The phosphorous is provided by phosphorous oxychloride (POCL3) which degenerates during the deposition and produces a phosphorous glass on the surface. This phosphorous glass is removed with Hydrogen Fluoride (HF). The phosphorous is then diffused for about 156 hours at about 1325"C to produce a penetration of about 240 Rm. This forms the N+ region 38 shown in Figure 3c.

The wafer is then flipped over and all further processing is carried out on the upper surface of the wafer. The oxidation layer 32 is patterned and removed to form a window 40, as is shown in Figure 3d. Boron is implanted through this window and diffused for about 90 hours at about 130000 to achieve a penetration of about 135 . This forms the P-region 42 as is shown in Figure 3e. The base oxide 32, 34 is then removed thereby producing the structure shown in Figure 3f.

The base is then produced by implanting boron into area 44 and diffusing the boron into the silicon at about 130000 for about 2.2 hours. This achieves a penetration of 16 KLm and thus forms the base 46 as shown in Figure 3e.

Next the emitter oxide is removed and a phosphorous deposition is carried out to produce the emitter 48. The phosphorous is once again provided in the form of POCL3 at a temperature of about 1000"C. The diffusion takes place for about 85 minutes at 1 1500C to achieve a penetration of 6 pun.

Contacts of metallisation is applied to the structure as in standard planar technology. The resultant structure (without metallisation) is as shown in Figure 2.

The method above is merely one example of how the Figure 2 structure can be made. It will be understood that variations to this method can be envisaged as long as the method ensures that the distance d between the base and collector is maintained substantially uniform.

Claims

1. A high voltage transistor comprising an emitter of a first conductivity type; a base of a second conductivity type having at least one deep region of a predetermined radius of curvature; and a collector of the first conductivity type profiled such that the separation between the base and collector regions is substantially constant.

2. A transistor according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

3. A transistor according to claim 1 or claim 2, wherein the deep region of the base is substantially on the periphery of the base.

4. A transistor according to claim 3 wherein the collector region thinner in the area where the deep region is located.

5. A transistor substantially as hereinbefore described, with reference to and as illustrated in Figure 2 and 3a-3h of the drawings.

6. A method of forming a high voltage transistor, comprising the steps of: forming a base of a second conductivity type, the base having at least one deep region of a predetermined radius of curvature; and forming at collector of the first conductivity type having a profile such that the separation between the base and collector is substantially constant.

7. A method according to claim 6, further comprising providing the first conductivity type as N-type and the second conductivity type as P-type.

8. A method according to claim 6 or claim 7, wherein the step of forming the collector comprises: growing an oxide layer on a first surface of a silicon wafer; patterning the oxide to expose a first window; implanting phosphorous into the window; and diffusing the phosphorous into the wafer.

9. A method according to claim 8, wherein the phosphorous implanting step comprises introducing phosphorous oxychloride into the first window heating the wafer to about 1200"C for about 240 minutes.

10. The method according to claim 8 or claim 9, wherein the diffusing step comprises diffusing the phosphorous at a temperatures of about 1325"C for about 156 hours.

11. A method according to any of claims 8 to 10, wherein the step of forming the base comprises: growing an oxide on a second surface of the silicon wafer; patterning the oxide to expose a second window; implanting boron into the second window; diffusing the boron into the wafer; patterning the oxide to expose a third window; implanting further boron into the third window; and diffusing further boron into the wafer.

12. A method according to claim 11, wherein the boron diffusing step comprises diffusing for about 90 hours at a temperature of about 1300"C.

13. A method according to claim 11 or claim 12, wherein the further boron diffusing step comprises diffusing for about 2.2 hours at a temperature of about 1300"C.

14. A method of forming a transistor substantially as hereinbefore described with reference to and as illustrated in Figure 2 and 3a-3h of the accompanying drawings.