GB2290905A - Semiconductor integrated circuit structure and method of fabricating same - Google Patents
Semiconductor integrated circuit structure and method of fabricating same Download PDFInfo
- Publication number
- GB2290905A GB2290905A GB9510129A GB9510129A GB2290905A GB 2290905 A GB2290905 A GB 2290905A GB 9510129 A GB9510129 A GB 9510129A GB 9510129 A GB9510129 A GB 9510129A GB 2290905 A GB2290905 A GB 2290905A
- Authority
- GB
- United Kingdom
- Prior art keywords
- silicon substrate
- integrated circuit
- semiconductor integrated
- circuit structure
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims description 60
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 32
- 229910052710 silicon Inorganic materials 0.000 claims description 32
- 239000010703 silicon Substances 0.000 claims description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 6
- 230000000994 depressogenic effect Effects 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 235000012431 wafers Nutrition 0.000 description 5
- 239000002131 composite material Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- OQCFWECOQNPQCG-UHFFFAOYSA-N 1,3,4,8-tetrahydropyrimido[4,5-c]oxazin-7-one Chemical group C1CONC2=C1C=NC(=O)N2 OQCFWECOQNPQCG-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/63—Combinations of vertical and lateral BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
Landscapes
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
2290905 SEMICONDUCTOR INTEGRATED CIRCUIT STRUCTURE AND METHOD OF
FABRICATING SAME
FIELD OF THE INVENTION
This invention relates to a semiconductor integrated circuit structure including a high power device and a low power control device and a method of fabricating such an integrated circuit structure.
BACKGROUND OF THE INVENTION
In many applications it is necessary to include both high power devices, for example working at up to 1000 volts, and control logic devices, working at, perhaps only 6 volts, on the same integrated device. For purposes of cost it is desirable to manufacture the high power device in a vertical orientation. In this case, if both the high power and the control logic devices are integrated on the same integrated circuit, problems can arise at the interface between the two devices where variations in the voltage of the high power device can affect the voltages in the control logic device, thereby affecting its operation.
This problem has been addressed in the past in several different ways. Firstly, in bipolar technology, the two devices have been isolated by the provision of a semiconductor npn junction laterally between the two devices and a buffer conductive layer below the two devices. This structure has the disadvantage that it requires extra masking steps in the fabrication process, which can be as high as 14-16 extra steps.
Furthermore, the npn junction, acting as a parasitic transistor introduces latchup and unwanted oscillations.
In a second known structure, a highly resistive surface is provided laterally between the devices. This is limited, however to lateral double diffused metal oxide silicon (LDMOS) devices as no vertical isolation can occur. Furthermore, the isolation is limited to 600 volts and even to achieve this level requires very low fluctuations in thickness and resistivity ( 2% in resistivity), which is very difficult to achieve. Even so, problems of voltage variations are not completely solved.
Thirdly, dielectic barriers of substrate polysilicon have been used in DMOS and LDMOS to isolate two lateral devices. Although this technique is successful in achieving isolation both in respect of oscillations and voltage variations, it requires the polysilicon to be grown to a thick layer to provide the necessary mechanical strength, which is a high cost process.
2 It is also limited to lateral isolation and any warpage of the wafers during polysilicon is incompatible with logic level definition.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a high power semiconductor integrated circuit structure which overcomes, or at least reduces, the above problems.
Accordingly, in one aspect, the invention provides a semiconductor integrated circuit structure having both a relatively high power device and a relatively low power control device integrated therein, the high power device including a vertical transistor having at least one layer extending below the low power control device and the low power control device being vertically isolated from said one layer by a dielectric layer.
Preferably, the dielectric layer is silicon dioxide. In a preferred embodiment, the dielectric layer is produced at a junction between two silicon substrates which are bonded together.
According to a second aspect, the invention provides a method of fabricating a semiconductor integrated circuit structure having both a relatively high power device and a relatively low power control device integrated therein, the method comprising the steps of.
providing a first silicon substrate having a first surface; at least partially fabricating the relatively low power device in a first portion of the first silicon substrate; providing a second silicon substrate having a first surface; bonding the first surfaces of the first and second silicon substrates together, wherein a dielectric layer is provided between the first portion of the first silicon substrate and the first surface of the second silicon substrate; and fabricating the relatively high power device in a second portion of the first silicon substrate and in the second silicon substrate so as to extend in the second silicon substrate across the first portion of the first silicon substrate, but separated therefrom by the dielectric layer.
Preferably, the relatively low power device is fabricated in the first silicon substrate such that a surface of the first portion is at an inner level compared to the first surface of the substrate and the dielectric layer is provided between the surface of the first portion and the first surface of the second silicon substrate.
3 In a preferred embodiment, the bonding takes place at high temperatures, whereby the dielectric layer is formed of silicon dioxide from the first layer of the second silicon substrate BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments of the invention will now be more fully described, by way of example, with reference to the drawings, of which:
FIGS. 1 to 17 show stages in the fabrication of a first embodiment of a semiconductor integrated circuit according to the invention; FIG. 18 shows an integrated circuit structure incorporating the first embodiment described with reference to FIGS. 1 to 17; FIG. 19 shows an integrated circuit structure of a second embodiment.
DETAILED DESCRIPTION
Thus, as shown in Figs. 1 to 17, an integrated circuit structure is fabricated to include low power control circuitry and a high power device, according to one embodiment of the invention, by providing a first silicon substrate 1, as shown in Fig 1, which has been prediffused with an N dopant to produce an N- substrate. A photoresist patterned layer 2 is the applied to a top surface 3 of the substrate 1 with a first oxide layer 4 between the photoresist layer 2 and the substrate 1, as shown in Fig 2. The substrate 1 is then etched on its top surface 3, except where the photoresist layer 2 was positioned, and the photoresist layer 2 and first oxide layer are then removed to leave the silicon substrate 1 etched to produce a depressed area 5, as shown in FIG. 3.
An epitaxial oxide layer 6, as shown in FIG. 4, is then grown on the top surface 3 of the substrate 1, including the depressed area 5. As shown in FIG. 5, two P+ areas 7 and 8 are then diffused into the substrate 1 at below either side of the depressed area 5. following which an N+ area 9 is diffused deeply into the substrate 1 below the depressed area 5 between the two P+ areas 7 and 8, as shown in FIG. 6. The P+ and N+ impurities in areas 7, 8 and 9 are then driven in deeper into substrate 1, as shown in FIG. 7, and a further, shallower area 10 of N+ is diffused into the substrate 1 below depressed area 5 adjacent the first N+ area 9, as shown in FIG. 8.
The epitaxial oxide layer 6 is then removed and a layer 11 of oxide is deposited over the whole top surface 3 of the substrate 1, including the depressed area 5, as shown in FIG. 9.
A first photoresist layer PR1 is now deposited over the oxide layer 11, as shown in FIG. 10. As can be seen, due to the sides of the depressed area 4 being sloped, the photoresist layer PR1 is thinner over the slopes than elsewhere. Therefore, if etching were to take place at this stage, the oxide layer 11 would not be etched to a flat surface right across the depressed area 5, as is required. Accordingly, the first photoresist layer PR1 is itself etched to produce a layer 12 extending solely over the depressed area 5, as shown in FIG. 11, and is then UV cured and hard baked. A second photoresist layer PR2 is then deposited over the first photoresist layer PR1, and over the rest of the oxide layer 11, as shown in FIG.12. This is then etched, together with layer 12 of photoresist PR1 to leave the oxide layer 11 solely within the depressed area 5 with a flat surface 13 slightly below the level of the top surface 3 of substrate 1, as shown in FIG. 13.
A second silicon substrate 14 is pre-diffused with N dopant to produce a top layer 15, which is N-, and a bottom layer 16, which is N+. The first substrate 1 is then turned upside down so that its top surface 3 contacts the top surface 17 of top layer 15 of second substrate 14. The two substrates are then heated to approximately 1200 C until the two substrates are atomically bonded together at bonding interface 18 formed at the junction of top surface 3 of the first substrate 1 and the top surface 17 of top layer 15 of second substrate 14. The heating causes a layer 19 of silicon dioxide to be formed in the gap between the surface 13 of oxide layer 11 and the top surface 17 of top layer 15 of second substrate 14. The composite wafer 20 formed by the two substrates 1 and 14 bonded together is then polished and aligned in the processing apparatus and a layer 21 of silicon dioxide is formed on the surface 22 thereof over the control circuitry, which surface was previously, as can be seen in FIG. 15, the bottom surface of the first substrate 1.
As shown in FIG. 16, the silicon dioxide layer 21 is then etched to provide electrical contact access to the two P+ areas 7 and 8. These areas, together with the N+ areas 9 and 10 and the oxide layer 11 form part of the low power control circuitry of the integrated circuit. To form the high power device, a P area 23 is first diffused into the composite wafer 20 adjacent the control circuitry areas. The P area 23 forms the base of the high power device and extends into the second substrate 14. As can be seen 1k in FIG. 17, further control circuitry areas, including P area 24 and an N area 25 are then diffused into the surface 22 of composite wafer 20 between the N+ area 9 and the P+ area 8. Furthermore, an N+ area 26 is diffused into the P area 23 of the high power device to form the emitter thereof, The silicon dioxide layer 21 is then extended over the surface 22 of composite wafer 20 over the high power device and contacts 27 to 32 are provided through the silicon dioxide layer 21 to contact the areas 8, 9, 24, 25, 23 and 26, respectively. The N+ area 16 of substrate 14, which extends below the control circuitry forms the collector of the high power device.
The final integrated circuit can be seen in FIG. 18, where the control circuitry and the high power device are shown in conjunction with various other parts of the integrated circuit, which are shown as comprising further N+ regions 33 and 34, with respective contacts 35 and 36. This integrated circuit is for a so-called intelligent insulated gate bipolar transistor integrated circuit.
FIG. 19 shows a second embodiment of a high voltage integrated circuit formed from a first substrate 37 and a second substrate 38 bonded to the first substrate 37 at a bonding interface 39 in the manner decsribed above with reference to the first embodiment of the invention. The first substrate 37 is provided with differently doped regions, including P+ and N+ regions having contacts, such as contact 40, attached to them, to form control circuitry 41. At the bonding interface 39, in the same manner as described above, there is provided an insulating layer 42 Of Si02 to isolate the control circuitry 41 from the high voltage portion of the circuit. The high voltage portion includes a high power transistor 43 formed by an emitter N+ region 44 provided with contact 45, a base P region 46 provided with contact 47 and a collector N+ region 48 provided with contact 49 and which extends below the Si02 layer 42.
It will be appreciated that although only two particular embodiments of the invention have been described in detail, various modifications and improvements can be made by a person skilled in the art without departing from the scope of the present invention.
6
Claims (8)
1. A semiconductor integrated circuit structure having both a relatively high power device and a relatively low power control device integrated therein, the high power device including a vertical transistor having at least one layer extending below the low power control device and the low power control device being vertically isolated from said one layer by a dielectric layer.
2. A semiconductor integrated circuit structure according to claim 1, wherein the dielectric layer is silicon dioxide.
3. A semiconductor integrated circuit structure according to either claim 1 or claim 2, wherein the dielectric layer is provided at a junction between two silicon substrates which are bonded together to form the semiconductor integrated structure.
4. A method of fabricating a semiconductor integrated circuit structure having both a relatively high power device and a relatively low power control device integrated therein, the method comprising the steps ofproviding a first silicon substrate having a first surface; at least partially fabricating the relatively low power device in a first portion of the first silicon substrate; providing a second silicon substrate having a first surface; bonding the first surfaces of the first and second silicon substrates together, wherein a dielectric layer is provided between the first portion of the first silicon substrate and the first surface of the second silicon substrate; and fabricating the relatively high power device in a second portion of the first silicon substrate and in the second silicon substrate so as to extend in the second silicon substrate across the first portion of the first silicon substrate, but separated therefrom by the dielectric layer.
5. A method of fabricating a semiconductor integrated circuit structure according to claim 4, wherein the relatively low power device is fabricated in the first silicon substrate such that a surface of the first portion is at an inner level compared to the first surface of the substrate and the dielectric layer is provided between the surface of the first portion and the first surface of the second silicon substrate.
6. A method of fabricating a semiconductor integrated circuit structure according to either claim 4 or claim 5, wherein the bonding takes 7 place at high temperatures, whereby the dielectric layer is formed of silicon dioxide from the first layer of the second silicon substrate
7. A semiconductor integrated circuit structure substantially as hereinbefore described with reference to FIGS. 1 to 18 or FIG 19 of the drawings.
8. A method of fabricating a semiconductor integrated circuit structure substantially as hereinbefore described with reference to FIGS. 1 to 18 or FIG 19 of the drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR9407119A FR2721139A1 (en) | 1994-06-10 | 1994-06-10 | Semiconductor integrated circuit structure and method of manufacturing the same. |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9510129D0 GB9510129D0 (en) | 1995-08-02 |
| GB2290905A true GB2290905A (en) | 1996-01-10 |
Family
ID=9464085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9510129A Withdrawn GB2290905A (en) | 1994-06-10 | 1995-05-16 | Semiconductor integrated circuit structure and method of fabricating same |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH07335886A (en) |
| KR (1) | KR960002885A (en) |
| DE (1) | DE19521142A1 (en) |
| FR (1) | FR2721139A1 (en) |
| GB (1) | GB2290905A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004303861A (en) | 2003-03-31 | 2004-10-28 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0176747A1 (en) * | 1984-08-31 | 1986-04-09 | Kabushiki Kaisha Toshiba | Silicon semiconductor substrate with an insulating layer embedded therein and method for forming the same |
| EP0220974A1 (en) * | 1985-09-24 | 1987-05-06 | STMicroelectronics S.A. | Power semiconductor component and associated control logic |
| EP0405183A2 (en) * | 1989-06-06 | 1991-01-02 | National Semiconductor Corporation | Dielectric isolation used in high voltage power IC process |
| US5204282A (en) * | 1988-09-30 | 1993-04-20 | Nippon Soken, Inc. | Semiconductor circuit structure and method for making the same |
| EP0559405A2 (en) * | 1992-03-03 | 1993-09-08 | Motorola, Inc. | Vertical and lateral isolation for a semiconductor device |
-
1994
- 1994-06-10 FR FR9407119A patent/FR2721139A1/en active Pending
-
1995
- 1995-05-16 GB GB9510129A patent/GB2290905A/en not_active Withdrawn
- 1995-05-30 KR KR1019950013747A patent/KR960002885A/en not_active Application Discontinuation
- 1995-06-07 JP JP7163102A patent/JPH07335886A/en active Pending
- 1995-06-09 DE DE19521142A patent/DE19521142A1/en not_active Withdrawn
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0176747A1 (en) * | 1984-08-31 | 1986-04-09 | Kabushiki Kaisha Toshiba | Silicon semiconductor substrate with an insulating layer embedded therein and method for forming the same |
| EP0220974A1 (en) * | 1985-09-24 | 1987-05-06 | STMicroelectronics S.A. | Power semiconductor component and associated control logic |
| US5204282A (en) * | 1988-09-30 | 1993-04-20 | Nippon Soken, Inc. | Semiconductor circuit structure and method for making the same |
| EP0405183A2 (en) * | 1989-06-06 | 1991-01-02 | National Semiconductor Corporation | Dielectric isolation used in high voltage power IC process |
| EP0559405A2 (en) * | 1992-03-03 | 1993-09-08 | Motorola, Inc. | Vertical and lateral isolation for a semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2721139A1 (en) | 1995-12-15 |
| GB9510129D0 (en) | 1995-08-02 |
| KR960002885A (en) | 1996-01-26 |
| JPH07335886A (en) | 1995-12-22 |
| DE19521142A1 (en) | 1995-12-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |