GB2289606A - Electronic hybrid circuit - Google Patents

Abstract

In order to reduce echos, there is disclosed a electronic hybrid circuit, comprising an input port 1 for four-wire signals, buffer mean Q1 - Q4 providing first signal paths 2, 3 from the four-wire input port to a two wire port T, R and to summing means X5 having an output coupled to an output port 4 for four-wire signals; a second signal path 3 connecting the four-wire input port to said summing means and separate from either first signal path, the arrangement being such that four wire signals on said first and second paths are summed in opposite senses by said summing means X5; means 10 for injecting a test signal into said first signal path 2 via Q2 - Q4; and adjusting means X4 responsive to the magnitude of the test signal at the two wire port to adjust the transfer function of the first and/or the second signal path so as to reduce the level of four-wire input signals at the four-wire output port. A further test signal may be applied to compensate for reactive changes in the impedance applied to the two wire port. <IMAGE>

Description

ELECTRONIC HYBRID CIRCUIT This invention relates to electronic hybrid circuits.

Hybrid circuits are used to convert between fourwire signals and two-wire signals. In telephone networks, voice signals between a central office and a subscriber are usually communicated by means of a two wire line. Voice signals between central offices are usually by four-wire circuits which may include time division multiplex or frequency multiplex via cable and/or radio, optical fibres and so on. A connection between two subscribers is thus generally served by a hybrid circuit at each end.

Although the four-wire input signal cannot, in practice, be completely eliminated from the four-wire output signal, a problem experienced with conventional hybrid circuits is that if the two-wire line is not exactly matched to the circuit, there is an increase in the level of the four-wire input signal present in the four-wire output signal. The impedance of a telephone line is not constant, nor are the impedances of any two lines identical. An attenuated version of the four-wire input signal is thus returned on the four-wire output line and would be perceived as echo in long distance telephone calls.

Conventionally, the effects of this echo have been mitigated by one of the following: 1) A loss imposed on long distance circuits over relatively short distances. This prevents the build up of recurrent echoes when there is an impedance mismatch between two wire lines and balance impedances at both ends of a long distant link; 2) Echo suppressing which detects which of the parties in the conversation is talking and places an attenuation on the receive pair associated with the talker; or Echo cancelling which analyses the incoming signal on the receive pair, analyses any echo component in the transmit pair and generates an inverted replica of the echo which is used to cancel the echo.

The conventional arrangements involve loss of signal level, unsatisfactory operation, undesirably high cost and complexity, respectively.

Against this background, in accordance with one aspect of the invention, there is provided an electronic hybrid circuit, comprising an input port for four-wire signals, buffer means providing first signal paths from the four-wire input port to a two wire port and to summing means having an output coupled to an output port for four-wire signals; a second signal path connecting the four-wire input port to said summing means and separate from either first signal path, the arrangement being such that four wire signals on said first and second paths are summed in opposite senses by said summing means; means for injecting a test signal into said first signal path; and adjusting means responsive to the magnitude of the test signal at the two wire-port to adjust the transfer function of the first and/or the second signal path so as to reduce the level of four-wire input signals at the four-wire output port.

The two-wire line loads the two-wire port. If there is a mismatch between the two-wire port and the two wire line this is reflected in the level of the test signal at the two-wire port. The effect on the hybrid is compensated by adjusting the transfer function of the first or second signal path.

In one form, the adjustment is to the gain of the signal path. Alternatively, or most preferably additionally, the trans-reactance is adjusted.

In order to substantially remove the test signal from the four-wire output signal, the test signal is preferably injected into both the first and the second signal paths so as to be summed in opposite senses in the summing means.

The two-wire line of a telephone system is normally a balanced line. Unbalanced signals require less complicated and less expensive equipment to deal with them, however. The first signal paths therefore preferably include: an unbalanced section coupled to the four-wire input port; a balanced section coupled to the two-wire port; and converter means for converting between the two sections, comprising: an impedance coupling an input node of the converter means to a feedback path; first differential buffer means having differential inputs connected to opposite ends of the impedance and opposite phase outputs coupled one to the tip and the other to the ring conductors of the two-wire port; second differential buffer means having respective differential inputs coupled to the tip and ring conductors and an output providing a feed back signal via said feedback path in a sense to reduce the signal appearing across the impedance. An unbalanced signal applied to the unbalanced port appears at the balanced port via the first differential buffer means, and is fed back to the input of the first differential buffer means via the second differential buffer means in a sense to provide negative feedback.The input impedance of the unbalanced port is increased by the feedback reducing the load of the circuit driving it. A balanced signal applied to the balanced port appears at the unbalanced port via the second differential buffer means and is fed back to the balanced port via the first differential buffer means. The sense of the signals round the loop again ensures that the feedback is negative.

When the adjusting means is operative to adjust the gain of one of the signal paths, the signal injected preferably has a component frequency outside or near an end of the range 300Hz to 3300Hz, to which component frequency the adjusting means is responsive to adjust the gain.

When the adjusting means is operative to adjust the gain and the trans-reactance of one of the signal paths, the signal injected preferably has component frequencies above and below, or high and low in the range 300Hz to 3300Hz, to which component frequencies the adjusting means is responsive to adjust the gain and the trans-reactance.

A second aspect of the invention extends to an electronic circuit for converting between a two-wire unbalanced line and a two-wire balanced line, comprising an impedance coupling a signal terminal of an unbalanced port of the converter means to a feedback path; first differential buffer means having differential inputs connected to opposite ends of the impedance and opposite phase outputs coupled one to each of balanced line terminals of a balanced port; second differential buffer means having respective differential inputs coupled to the balanced line terminals and an output providing a feed back signal via said feedback path in a sense to reduce the signal appearing across the impedance.

One embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, which is a circuit diagram of a hybrid circuit embodying the invention.

Referring to the drawing, voice signals appearing at a four-wire input port 1 are applied to a long tailed pair differential buffer amplifier comprising Darlington pairs Q1 and Q2. Darlington pairs Q3 and Q4 provide DC bias to the following stages and further balanced amplification.

Voice signals of opposite phase appear at the collectors of the Darlington pairs Q3 and Q4. The opposite phase signals are transmitted by matched signal paths 2 and 3 to an input of summing means in the form of an operational amplifier X5 the output of which is connected to a four-wire output port 4. If the circuit is completely balanced, the output signal at the four-wire port will contain no component from the four-wire input signal.

An unbalanced section of a two wire signal path is provided by line 6 connected to the signal path 3 at the collector of Darlington pair Q3. The unbalanced section terminates at a collector resistor R48 of a Darlington pair Q12, which resistor is matched by a resistor R15 in the other signal path 2. Signals received at the four-wire input therefore appear on the two wire line section 6.

Signals placed on the two wire line section 6 by the Darlington pair Q12 are prevented from appearing at the four-wire input port 1 by the buffer Darlington pair Q3, but appear at the input to a buffer X2 which is matched by a buffer X1 in the other signal path 2. As there is no corresponding appearance of the signals in the signal path 2, signals placed on the two wire line section 6 by the Darlington pair Q8, are thus not cancelled at the amplifier X3 and appear at the four-wire output port 4.

The two-wire port 8 is balanced having tip and ring conductors T and R as is conventional. The unbalanced line 6 contains a small series resistor R31 opposite sides of which are connected to respective inputs of a long tailed pair differential amplifier comprising Darlington pairs Q7 and Q8. Signals placed on the unbalanced section 6 by the Darlington pair Q3 create a current through the resistor R31. The voltage drop across the resistor is thus amplified by the differential amplifier Q7, Q8. Respective opposite phase outputs are taken from the collectors of the Darlington pairs Q7 and Q8 through emitter follower amplifiers comprising Darlington pairs Q9 and Q10 to the tip and ring conductors T and R. Resistors R28 and R43 in the tip and ring conductors have a value to match the nominal impedance of the line.

The tip and ring conductors also contain current sensing series resistors R39 and R44. These are bridged by resistors R40, R41, R45 and R46 to provide differential current dependent signals to a long tailed pair differential buffer amplifier comprising a Darlington pair Q11 and the Darlington pair Q12.

The signal on the tip and ring conductors will contain a mixture of signal components. One component will be the voice signal received via the four-wire input port 1.

Another component will be the voice signal receive via the two-wire balanced line. The mixed signal appears at the input to the Darlington pair Q7 in such a sense that the four-wire component thereof is in phase with the four-wire component applies by the Darlington pair Q3 to the other end of the resistor R16 to reduce the differential signal appearing across the resistor R31. For signal components placed on line 6 by the Darlington pair Q3, a stable negative feedback buffer is thus provided between the output of Darlington pair Q3 and the two-wire port 8. For signal components received from the two wire line at the port 8 and placed on the unbalanced line 6 by the Darlington pair Q12, the buffer amplifier comprising Darlington pairs Q7 to Q10 provide a stable negative feedback path to the two-wire port 8.

The signal paths 2 and 3 also contain matched voltage controlled amplifiers X4 and X3 respectively. The hybrid circuit can be balanced for the impedance of a particular line by adjusting the gain of the amplifier X3 with the voltage divider V1. If however the impedance of the two-wire line attached to T and R line changes, decreases for example, the balance is upset. A decrease in, say, the resistance of the two wire line, produces an increase in the signal current through the resistors R39 and R44 which increases the differential signal level applied to the differential buffer amplifier Qll and Q12. That in turn increases the signal level applied to the resistor R31 at the end connected to the Darlington pair Q3 and increases the signal level at the input to the buffer X2.Unless the relative gains of the signal paths 2 and 3 are adjusted to compensate, the circuit will be out of balance and received four-wire signals will appear at the four-wire output port 4.

In order to maintain the hybrid circuit in better balance, a low magnitude low frequency test signal, preferably below the telephonic voice frequency range 300Hz to 3300Hz, e.g. 160Hz is injected by oscillator 10 into the base of the Darlington pair Q2. This produces signal components of opposite phase in the signal paths 2 and 3 which thus cancel in the amplifier X5 if the circuit is in balance. In an alternative arrangement, the test signal is above or high in the range.

In the arrangement illustrated, a high Q-factor filter 12, comprising amplifiers X6, X8 and respective feedback networks and buffer X7, is arranged to reject frequencies other than that of the test signal frequency applying the filtered signal to a detector arrangement 14.

The filtered signal is applied to the source of a field effect transistor Q13. The filtered signal is applied to an input to an inverter comprising an amplifier X9 and a feedback resistor network, the inverted signal being applied to the source of field effect transistor Q14. The drains of the field effect transistors Q13 and Q14 are connected to a smoothing network comprising a resistor R64 and a capacitor C12. The field effect transistors Q13 and Q14 are of opposite polarity types and are gated on and off alternately in antiphase by a square wave signal output of a comparator Xl0 to an input of which the output of filter 12 is applied.

Thus alternate half waves are created of the same polarity and are passed to the junction of the drains of Q13 and Q14.

A full wave rectified signal is thus obtained at the input to the smoothing network C12,R64. The magnitude of the rectified and smoothed signal is representative of the magnitude of the test signal component appearing across R39 and R44 which are connected to the tip and ring conductors T and R and thus of the load applied thereto by the line. The combination of low signal level and. low frequency ensure that the test signal is not heard by the subscriber. In order to ensure that there is a signal when the line is open circuit, a resistor R72 is connected between the tip and ring conductors.

An increase, say, in the magnitude of the smoothed signal indicates that the gain in the signal path 3 has increased. In order to compensate for that increase, the smoothed signal across the capacitor C12 is applied to the differential input of an amplifier X11 whose gain is controlled by an input resistor R65 and a variable feedback resistor V4. The output of the amplifier X11 is mixed with a DC level setting signal output of a buffer amplifier X12, by an amplifier X13 with its feedback resistor R68 and input resistors R69 and R67, to generate a control signal at the output of the amplifier X13. The output of the buffer amplifier X12 is controlled by a potentiometer V5 connected to an input thereof.

The control signal at the output of the amplifier X13 is fed via a lag network, comprising a resistor R71 and a capacitor C13, and via a buffer amplifier X14 to a control input of the amplifier X4. Correct adjustment of the gain of amplifier Xli by variable resistor V4, and of the DC level by potentiometer V5, enable the gain of the amplifier X4 to be adjusted to reflect the change in gain in the signal path 3 caused by resistive changes in the load applied to the tip and ring conductors T and R, thereby to maintain the hybrid circuit in balance so that the four-wire input signal is accurately cancelled from the output of the amplifier X5 which is applied to the four-wire output port 4. The lag is intended to prevent transients on the line from affecting the balance of the hybrid.

In other embodiments, not illustrated, compensation is also provided for reactive changes in the impedance applied to the tip and ring conductors T and R.

To this end, a separate high frequency test signal is also injected into the base of the Darlington pair Q2.

This produces signal components of opposite phase in the signal paths 2 and 3 which thus cancel in the amplifier X3 if the circuit is in balance. The frequency of the signal is preferably towards the upper end of the voice signal range 300Hz to 3300Hz and most preferably above the range.

Similarly to the low frequency test signal, the signal on the Darlington pair Q7 is filtered to reject other frequencies, rectified and smoothed. This smoothed DC level is compared to the smoothed DC level generated from the first test signal and a control signal is generated to adjust a variable reactance element, e.g. a varactor, in the signal path 2 so as to compensate for changes in the gain of the signal path 3 as reactive elements in the two wire load react to frequency variations in signals within the band 300HZ to 3300HZ, thereby maintaining balance at all frequencies within this band.

In an alternative arrangement the gain setting test signal is high frequency and the variable reactance setting signal is low frequency.

Claims (8)

1. An electronic hybrid circuit, comprising an input port for four-wire signals, buffer means providing first signal paths from the four-wire input port to a two wire port and to summing means having an output coupled to an output port for four-wire signals; a second signal path connecting the four-wire input port to said summing means and separate from either first signal path, the arrangement being such that four wire signals on said first and second paths are summed in opposite senses by said summing means; means for injecting a test signal into said first signal path; and adjusting means responsive to the magnitude of the test signal at the two wire port to adjust the transfer function of the first and/or the second signal path so as to reduce the level of four-wire input signals at the four-wire output port.

2. A hybrid circuit as claimed in claim 1, wherein the test signal is injected into both the first and the second signal paths so as to be summed in opposite senses in the summing means

3. A hybrid circuit as claimed in claim 1 or claim 2, wherein the first signal paths include: an unbalanced section coupled to the four-wire input port; a balanced section coupled to the two-wire port; and converter means for converting between the two sections, comprising: an impedance coupling an input node of the converter means to a feedback path; first differential buffer means having differential inputs connected to opposite ends of the impedance and opposite phase outputs coupled one to the tip and the other to the ring conductors of the two-wire port; second differential buffer means having respective differential inputs coupled to the tip and ring conductors and an output providing a feedback signal via said feedback path in a sense to reduce the signal appearing across the impedance.

4. A hybrid circuit as claimed in any preceding claim, wherein the adjusting means is operative to adjust the gain of one of the signal paths.

5. A hybrid circuit as claimed in claim 4, wherein the signal injected has a component frequency near an end of or above the range 300Hz to 3300Hz, to which component frequency the adjusting means is responsive to adjust the gain.

6. A hybrid circuit as claimed in any preceding claim, wherein the adjusting means is operative to adjust the trans-reactance of one of the signal paths.

7. A hybrid circuit as claimed in claim 6 when dependent on claim 5, wherein the signal injected has component frequencies above and below, or high and low in the range 300Hz to 3300Hz, to which component frequencies the adjusting means is responsive to adjust the gain and the trans-reactance.

8. An electronic circuit for converting between a two-wire unbalanced line and a two-wire balanced line, comprising an impedance coupling a signal terminal of an unbalanced port of the converter means to a feedback path; first differential buffer means having differential inputs connected to opposite ends of the impedance and opposite phase outputs coupled one to each of balanced line terminals of a balanced port; second differential buffer means having respective differential inputs coupled to the balanced line terminals and an output providing a feedback signal via said feedback path in a sense to reduce the signal appearing across the impedance.