GB2286286A - Semiconductor device having shield conduction lines - Google Patents
Semiconductor device having shield conduction lines Download PDFInfo
- Publication number
- GB2286286A GB2286286A GB9426405A GB9426405A GB2286286A GB 2286286 A GB2286286 A GB 2286286A GB 9426405 A GB9426405 A GB 9426405A GB 9426405 A GB9426405 A GB 9426405A GB 2286286 A GB2286286 A GB 2286286A
- Authority
- GB
- United Kingdom
- Prior art keywords
- conduction
- conduction lines
- lines
- semiconductor device
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A semiconductor device is formed to have spaced inner conduction lines (1, 2, 3) and shield conduction lines (a, b) each arranged between adjacent ones of the inner conduction lines (1, 2, 3). A shield plate (6) is in electrical contact with the shield conduction lines (a, b) and connected to ground. The shield conduction lines (a, b) and the shield plate (6) are effective to shield a coupling capacitance formed due to increased integration of the inner conduction lines (1, 2, 3). Thus, generation of noise is prevented, as is erroneous operation of the chip even when variations in voltage between adjacent inner conduction lines occur. In another embodiment, the device has upper and lower shield plates (16, 17 - Fig. 3B, not shown). <IMAGE>
Description
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
The present invention relates to a semiconductor device and a method for fabricating the same.
As semiconductor devices have higher degrees of integration, the distance between adjacent inner conduction lines thereof is reduced. Such a reduced distance results in an increase in coupling capacitance. Since a variation in voltage is generated at the inner conduction lines due to the increased coupling capacitance, peripheral inner conduction lines are subject to an adverse effect. As a result, the semiconductor device has problems in that noise is generated, and erroneous operation of the chip can arise.
It is an object of the present invention to provide a semiconductor device in which these problems are reduced.
According to a first aspect of the present invention there is provided a semiconductor device comprising:
a number of inner conduction lines formed on an insulating layer;
at least two second conduction lines respectively formed on a portion of the insulating layer not formed with the inner conduction lines; and
a shield plate insulted from the inner conduction line or lines and electrically connected to the second conduction lines, whereby the or each inner conduction line is shielded from noise or from interference occurring among the inner conduction lines.
The invention also extends to a method of fabricating such a semiconductor device.
A semiconductor device according to one embodiment of the invention includes shield conduction lines and a shield plate connected to a ground line arranged to shield a coupling capacitor formed by increased integration of the inner conduction lines, thereby capable of preventing noise generation and erroneous operation of the chip even when variations in voltage between adjacent inner conduction lines occur.
In accordance with one aspect, the present invention provides a semiconductor device comprising: a plurality of inner conduction lines formed on an insulating layer and uniformly spaced from one another; at least two second conduction lines respectively formed on portion of the insulating layer not formed with the inner conduction lines; and a shield plate insulated from the inner conduction lines and electrically connected to the second conduction lines, whereby a noise or a co-interference occurring among the inner conduction lines is shielded.
In accordance with another aspect, the present invention provides a method for fabricating a semiconductor device, comprising the steps of: depositing a first conduction layer over a first insulating layer; selectively etching the first conduction layer, thereby forming a plurality of spaced inner conduction lines and a plurality of second conduction lines each disposed between adjacent groups of the inner conduction lines; forming a second insulating layer over the entire exposed surface of the resulting structure obtained after the formation of the conduction lines; etching predetermined portions of the second insulating layer, thereby forming contact holes through which the second conduction lines are exposed, respectively; and depositing a second conduction layer over the entire exposed surface of the resulting structure obtained after the formation of the contact holes, etching a predetermined portion of the second conduction layer, thereby forming a shield plate being in contact with the second conduction lines through the contact holes and electrically connected to the second conduction lines.
Embodiments of the present invention will hereinafter be described, by way of example, with reference to the accompanying drawings, in which:
Figures 1A and 1B are a layout view and a sectional view respectively illustrating the construction of inner conduction lines by a known fabrication method;
Figures 2A and 2s are a layout view and a sectional view respectively illustrating a semiconductor device fabricated in accordance with a first embodiment of the present invention;
Figures 3A and 3B are a layout view and a sectional view respectively illustrating a semiconductor device fabricated in accordance with a second embodiment of the present invention; and
Figures 4A and 4B are a layout view and a sectional view respectively illustrating a semiconductor device fabricated in accordance with a third embodiment of the present invention.
In the drawings, similar features and elements have been accorded the same reference numerals.
Figure lA shows a plan view showing the layout of inner conduction lines 1, 2 and 3 arranged in a conventional construction. As can be seen, inner conduction lines 1 and 3 are arranged on opposed sides of an intermediate inner conduction line 2. When there is an increase in voltage from a low level to a high level at a low voltage level state of the intermediate inner conduction line 2, the voltage of the intermediate inner conduction line 2 increases from the low level to a high level. As a result, an erroneous operation of the chip of a semiconductor may be generated. Such a phenomenon becomes severe as the semiconductor device is more highly integrated.
Figures 2A and 2B illustrate a semiconductor device fabricated in accordance with a first embodiment of the present invention.
Figure 2A is a plan view illustrating a layout of the semiconductor device. As shown in Figure 2A, the semiconductor device includes inner conduction lines 1, 2 and 3 spaced from one another, and shield conduction lines a and b each arranged between adjacent ones of the inner conduction lines 1, 2 and 3. The semiconductor device also includes a shield plate 6 which is in contact with the shield conduction lines a and b.
Figure 2B is a cross-sectional view taken along the line A - A' of Figure 2A. The structure shown in Figure 2B is fabricated in the following manner. A first conduction film is deposited over an insulating layer 4. The first conduction film is then partially etched, thereby forming the inner conduction lines 1, 2 and 3 and the shield conduction lines a and b. Over the entire exposed surface of the resulting structure, an insulating layer 14 is then formed. Subsequently, predetermined portions of the insulating layer 14 are etched, thereby forming contact holes 5 through which the shield conduction lines a and b are exposed. A second conduction layer is then deposited over the entire exposed surface of the resulting structure.
Finally, a predetermined portion of the second conduction layer is etched to form the shield plate 6.
The centrally disposed inner conduction line 2 is surrounded by the shield conduction lines a and b, which are connected to a ground line, so that it is not affected by possible voltage variations occurring on the inner conduction lines 1 and 3 disposed on opposite sides thereof.
Figures 3A and 3B illustrate a semiconductor device fabricated in accordance with a second embodiment of the present invention. Figure 3A is a plan view illustrating a layout of the semiconductor device fabricated in accordance with the second embodiment. As shown in Figure 3A, the semiconductor device includes inner conduction lines 1, 2 and 3 spaced from one another, and shield conduction lines a and b each arranged between adjacent ones of the inner conduction lines 1, 2 and 3. The semiconductor device also includes an upper shield plate 16 and a lower shield plate 17, both of the shield plates 16, 17 being in contact with the shield conduction lines a and b.
Figure 3B is a cross-sectional view taken along the line A - A' of Figure 3A. The structure shown in Figure 3B is fabricated in the following manner. A first conduction film is deposited over an insulating layer 4. A predetermined portion of the first conduction film is then etched to form the lower shield plate 17. Over the entire exposed surface of the resulting structure, an insulating layer 12 is then deposited. Subsequently, the insulating layer is etched at predetermined portions thereof, thereby forming contact holes 15' through which the shield plate is exposed at the predetermined portions. Thereafter, a first conduction film is formed over the entire exposed surface of the resulting structure. The first conduction film is then etched at predetermined portions thereof to form the inner conduction lines 1, 2 and 3 and the shield conduction lines a and b. Over the entire exposed surface of the resulting structure, an insulating layer 14 is then formed.
Subsequently, predetermined portions of the insulating layer 14 are etched, thereby forming contact holes 15 through which the shield conduction lines a and b are respectively exposed. A second conductor layer is then deposited over the entire exposed surface of the resulting structure. Finally, a predetermined portion of the second conduction layer is etched to form the shield plate 16.
Figures 4A and 4B illustrate a semiconductor device fabricated in accordance with a third embodiment of the present invention. Figure 4A is a plan view illustrating a layout of the semiconductor device. As shown in Figure 4A, the semiconductor device includes inner conduction lines 1, 2, 2', 2" and 3 spaced from one another, and shield conduction lines a and b arranged inwardly adjacent to the inner conduction lines 1 and 3 which are opposite outer ones of the inner conduction lines, respectively. The semiconductor device also includes a shield plate 26 which is in contact with the shield conduction lines a and b.
Figure 4B is a cross-sectional view taken along the line A - A' of Figure 4A. The structure shown in Figure 4B is fabricated in the following manner. A first conduction film is deposited over an insulating layer 4. The first conduction film is then partially etched, thereby forming the inner conduction lines 1, 2, 2', 2" and 3 and the shield conduction lines a and b. Over the entire exposed surface of the resulting structure, an insulating layer 14 is then formed. Subsequently, predetermined portions of the insulating layer 14 are etched, thereby forming contact holes 25 through which the shield conduction lines a and b are respectively exposed. A second conduction layer is then deposited over the entire exposed surface of the resulting structure. Finally, a predetermined portion of the second conduction layer is etched to form the shield plate 26.
The centrally disposed inner conduction lines 2, 2' and 2" are surrounded by the shield conduction lines a and b which are connected to a ground line, so that they are not affected by possible voltage variations occurring at the inner conduction lines 1 and 3 disposed on opposite sides thereof.
The method shown in Figure 4B is generally similar to the method shown in Figure 2B except that several inner conduction lines are shielded by the shield plate, and the shield conduction lines are connected to the ground line, so as to prevent the generation of noise and erroneous operation of the chip. In the case of Figure 2B, only one inner conduction line is shielded by the shield conduction lines and the shield plate.
As is apparent from the above description, the present invention provides a semiconductor device having a structure including shield conduction lines and a shield plate capable of serving as a shield film and thereby preventing a generation of noise and an erroneous operation of the chip even when a variation in voltage between adjacent inner conduction lines occurs.
Although preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope of the invention as defined in the accompanying claims.
Claims (12)
1. A semiconductor device comprising:
a number of inner conduction lines formed on an insulating layer;
at least two second conduction lines respectively formed on a portion of the insulating layer not formed with the inner conduction lines; and
a shield plate insulted from the inner conduction line or lines and electrically connected to the second conduction lines, whereby the or each inner conduction line is shielded from noise or from interference occurring among the inner conduction lines.
2. A semiconductor device as claimed in Claim 1, wherein the shield plate is connected to a ground line.
3. A semiconductor device as claimed in Claim 1 or Claim 2, wherein the shield plate is disposed at a region defined beneath or above the inner conduction lines and the second conduction lines.
4. A semiconductor device as claimed in any of Claims 1 to 3, wherein the shield plate is disposed at each of regions respectively defined beneath and above the inner conduction lines and the second conduction lines.
5. A semiconductor device as claimed in any preceding claim, wherein a plurality of said inner conduction lines are formed on said insulating layer and are substantially uniformly spaced apart.
6. A method of fabricating a semiconductor device, comprising the steps of:
depositing a first conduction layer over a first insulating layer;
selectively etching the first conduction layer to thereby form a number of inner conduction lines and at least two second conduction lines interspersed with the inner conduction line or lines;
forming a second insulating layer over the entire exposed surface of the resulting structure obtained after the formation of the conduction lines;
etching predetermined portions of the second insulating layer, thereby forming contact holes through which the second conduction lines are exposed; and
depositing a second conduction layer over the entire exposed surface of the resulting structure obtained after the formation of the contact holes, etching a predetermined portion of the second conduction layer to form a shield plate which is in contact with the second conduction lines through the contact holes and electrically connected to the second conduction lines.
7. A method as claimed in Claim 6, comprising etching a plurality of spaced inner conduction lines, each said second conduction line being disposed between adjacent groups of the inner conduction lines.
8. A method as claimed in Claim 7, wherein each group of the inner conduction lines includes at least one inner conduction line.
9. A method as claimed in any of Claims 6 to 8, wherein the shield plate has a rectangular planar structure.
10. A method of fabricating a semiconductor device, comprising the steps of:
depositing a first conduction layer over a first insulating layer, and etching a predetermined portion of the first conduction layer to form a lower shield plate;
depositing a second insulating layer over the entire exposed surface of the resulting structure obtained after the formation of the lower shield plate, and selective etching predetermined portions of the second insulating layer to form contact holes through which the shield plate is exposed;
depositing a second conduction layer over the second insulating layer, etching predetermined portions of the second conduction layer to form a plurality of spaced inner conduction lines and plurality of shield conduction lines each disposed between adjacent groups of the inner conduction lines;
forming a third insulating layer over the entire exposed surface of the resulting structure obtained after the formation of the conduction lines, etching predetermined portions of the third insulating layer to form contact holes through which the shield conduction lines are exposed; and
depositing a third conduction layer over the entire exposed surface of the resulting structure obtained after the formation of the contact holes for exposing the shield conduction lines, etching a predetermined portion of the third conduction layer to form a shield plate electrically connected to the shield conduction lines.
11. A semiconductor device substantially as hereinbefore described with reference to Figures 2A to 4B of the accompanying drawings.
12. A method of fabricating a semiconductor device substantially as hereinbefore described with reference to
Figures 2A to 4B of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR930031822 | 1993-12-31 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9426405D0 GB9426405D0 (en) | 1995-03-01 |
| GB2286286A true GB2286286A (en) | 1995-08-09 |
| GB2286286B GB2286286B (en) | 1998-05-27 |
Family
ID=19374754
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9426405A Expired - Fee Related GB2286286B (en) | 1993-12-31 | 1994-12-30 | Improvements in or relating to the fabrication of semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2286286B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000014801A1 (en) * | 1998-09-03 | 2000-03-16 | Telefonaktiebolaget Lm Ericsson | High voltage shield |
| US6133621A (en) * | 1998-10-15 | 2000-10-17 | Stmicroelectronics S.R.L. | Integrated shielded electric connection |
| FR2826780A1 (en) * | 2001-06-28 | 2003-01-03 | St Microelectronics Sa | SEMICONDUCTOR DEVICE WITH MICROWAVE STRUCTURE |
| EP1750370A2 (en) * | 2005-08-01 | 2007-02-07 | Samsung Electronics Co.,Ltd. | Monolithic duplexer and fabrication method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2134708A (en) * | 1983-01-18 | 1984-08-15 | Western Electric Co | Integrated circuits |
| GB2261991A (en) * | 1991-11-28 | 1993-06-02 | Samsung Electronics Co Ltd | Noise supression in memory device |
| US5296735A (en) * | 1991-01-21 | 1994-03-22 | Mitsubishi Denki Kabushiki Kaisha | Power semiconductor module with multiple shielding layers |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3283984B2 (en) * | 1993-12-28 | 2002-05-20 | 株式会社東芝 | Semiconductor integrated circuit device |
-
1994
- 1994-12-30 GB GB9426405A patent/GB2286286B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2134708A (en) * | 1983-01-18 | 1984-08-15 | Western Electric Co | Integrated circuits |
| US5296735A (en) * | 1991-01-21 | 1994-03-22 | Mitsubishi Denki Kabushiki Kaisha | Power semiconductor module with multiple shielding layers |
| GB2261991A (en) * | 1991-11-28 | 1993-06-02 | Samsung Electronics Co Ltd | Noise supression in memory device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000014801A1 (en) * | 1998-09-03 | 2000-03-16 | Telefonaktiebolaget Lm Ericsson | High voltage shield |
| US6384463B1 (en) | 1998-09-03 | 2002-05-07 | Telefonaktiebolaget Lm Ericsson (Publ) | High voltage shield |
| US6133621A (en) * | 1998-10-15 | 2000-10-17 | Stmicroelectronics S.R.L. | Integrated shielded electric connection |
| FR2826780A1 (en) * | 2001-06-28 | 2003-01-03 | St Microelectronics Sa | SEMICONDUCTOR DEVICE WITH MICROWAVE STRUCTURE |
| EP1274128A1 (en) * | 2001-06-28 | 2003-01-08 | STMicroelectronics S.A. | Semiconductor device with hyper-frequency structure |
| US6876076B2 (en) | 2001-06-28 | 2005-04-05 | Stmicroelectronics Sa | Multilayer semiconductor device for transmitting microwave signals and associated methods |
| EP1750370A2 (en) * | 2005-08-01 | 2007-02-07 | Samsung Electronics Co.,Ltd. | Monolithic duplexer and fabrication method thereof |
| EP1750370A3 (en) * | 2005-08-01 | 2008-09-17 | Samsung Electronics Co.,Ltd. | Monolithic duplexer and fabrication method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2286286B (en) | 1998-05-27 |
| GB9426405D0 (en) | 1995-03-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20091230 |