GB2286067A

GB2286067A - A processor system

Info

Publication number: GB2286067A
Application number: GB9326311A
Authority: GB
Inventors: Ilan Pardo; Ilia Greenbiat; Yoav Talgam
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1993-12-23
Filing date: 1993-12-23
Publication date: 1995-08-02
Also published as: GB9326311D0; JPH07210404A

Abstract

A processor system for processing a plurality of tasks comprises a set of execution resources and a control arrangement (6, 7) for switching the processor system between a first mode of operation and a second mode of operation. In the first mode of operation, the control arrangement (6, 7) assigns the set of execution resources to one of the plurality of tasks, in the second mode of operation, the control arrangement (6, 7) assigns a first subset of the execution resources to a first task, which may be the same task as that processed in the first mode, and a second different subset to a second task, which may be an interrupt task, whereby the processor system simultaneously processes the first and second tasks. <IMAGE>

Description

A Processor System This invention relates to a processor system for processing a plurality of tasks and more particularly to a processor system operable in two modes: in a first mode, the processor system processes one task and in a second mode, the processor can simultaneously process a plurality of tasks.

Background of the Invention In modern processors, the performance can be improved by utilising parallel mechanisms, such as out-of-order execution and speculative execution, and/or highly pipelined execution units, such as floating point, vector processors and graphic units. However, when interrupts occur, the advantages of these mechanisms is considerably reduced for the following reasons.

When the hardware responds to an interrupt request, a long clean-up action is executed to unroll the pipelines of the execution units. This action, in addition to taking considerable time, normally involves cancellation of computations carried out for the interrupted program. These computations have to be re-executed after the interrupt is served.

In order that the handler has working registers space, the interrupt handler routine must save some of the processor state before it starts to do anything useful.

Typical interrupt handlers have implicit high data dependency. This is due to the fact that typical interrupts are typified by short code sequences, which often have explicit or implicit data dependencies resulting from the need to service Input/Output (I/O) devices.

Furthermore, the processing within the interrupt handler is essentially not numeric and so all special purpose hardware (such as the floating point unit) is under utilised.

An alternate method for interrupt processing utilises a dedicated special processor. Typically, such a dedicated processor has its own memories and interfaces which makes the cost of this alternative method prohibitive. Low cost integrated micro-controllers could reduce the cost.

However, such dedicated processors have a further disadvantage in that they introduce a separate programming environment for interrupt processing, which has its ownership, training and maintenance cost. Additionally, if cooperative action is required between the dedicated interrupt processor and the main CPU, they must communicate through memory at some latency and performance penalty.

It would therefore be desirable to develop a multi-task processor system which can process interrupts, whilst continuing execution of the original task, and which does not have the above problems and disadvantages.

Summary of the Invention In accordance with the present invention there is provided a processor system for processing a plurality of tasks, the processor system comprising a set of execution resources and control means for switching the processor system between a first mode of operation and a second mode of operation, wherein in the first mode of operation, the control means assigns the set of execution resources to one of the plurality of tasks, and in the second mode of operation, the control means assigns a first subset of the execution resources to a first task and a second different subset to a second task, whereby the processor system simultaneously processes the first and second tasks.

In a preferred arrangement, in the second mode of operation, the first task is an interrupt routine and the second task is the continuation of the same task which was already being processed in the first mode of operation.

The present invention therefore provides a processor system with improved handling of real-time interrupts.

The switching of the processor system in accordance with the present invention, from the first mode to the second mode, is equivalent to slicing the processor system such that a small part of the hardware execution resources are put aside to virtually create an independent sliced processor, in addition to the original main processor which utilises the rest of the hardware execution resources. In this second mode, the sliced processor in accordance with a preferred embodiment can therefore handle interrupts, whilst the original processor continues executing the main routine. Once the interrupt has been processed, the sliced processor is merged again with the original processor with zero time penalty. The performance of the original processor may be insignificantly reduced, since some of the execution resources are assigned to the sliced processor. Since the original processor continues execution, the large computation resources, such as the floating point units, are not under-utilised. The sliced processor typically uses the minimal number and straight forward execution resources of the processor system and thus, requires minimal context switching time.

Brief Description of Drawings A processor system in accordance with a preferred embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings in which: Fig. 1 is a block schematic diagram of a processor system in accordance with the present invention; Fig. 2 is a block schematic diagram of the processor system of Fig. 1 in a second 'sliced' mode which shows the execution resources available to the main routine; Fig. 3 is a block schematic diagram of the processor system of Fig. 1 in a second 'sliced' mode which shows the execution resources available to a second task; and Fig. 4 is a block schematic diagram of part of the control logic of the processor system of Fig. 1.

Detailed Description of the Drawings Referring firstly to Fig. 1, a processor system 2 in accordance with a preferred embodiment of the invention comprises a plurality of execution resources 4 coupled to a sequencer 6, via at least two control buses 8 and 10, and to a set of data buses 12. The preferred embodiment is a dual instruction issue system; that is, it issues two instructions per clock cycle, and therefore, there are two control buses 8 and 10 for coupling instructions from the sequencer to the execution resources 4.

The preferred embodiment will be described with reference to switching between a main routine and an interrupt routine on receipt of an interrupt signal. However, it is not intended that the invention be limited to such a specific arrangement. The invention relates generally to switching between a first mode in which one task is processed by the system and a second mode in which first and second tasks can be processed simultaneously by the system.

The sequencer 6 receives the interrupt signal and the instructions of the task or tasks to be processed from a cache memory 18 via two prefetch buffers 20 and 22. The cache 18 communicates with the system bus 24 via a bus interface unit BIU. A memory management unit MMU controls the accessing of the data and instructions from the cache 18. In the preferred embodiment the cache 18 is an unified cache for data and instructions.

As shown in Fig. 1, the plurality of execution resources 4 may include integer units INT, bit field units BF, floating point register files (FP REG file), floating pointlinteger multipliers (FP/I MUL), general register file (GEN REG file), slice register file 14, integer divider (IDIV) and load/store unit 16.

In a first normal mode of operation, the processor system 2 processes a task as follows. The instructions for the task are fetched from the cache 18, up to four instructions every clock cycle and held in the prefetch buffers 20 and 22 before being sent to the sequencer 6. The sequencer 6 issues up to two instructions every clock to the execution resources 4 via the two control buses 8 and 10 so that the appropriate units are activated to carry out the instructions. The state of the system after each instruction is stored in the general register file GEN REG file and/or the floating point register file FP REG file depending on the issued instruction. Thus, in the first mode, the main CPU has access to all of the execution resources.

In a second 'sliced' mode the execution resources are sliced so that a main portion is assigned to a first task, such as the continuous execution of the main routine, and a small portion of the execution resources are assigned to a second task, such as servicing an interrupt. Thus, the main CPU is assigned the main portion and a sliced processor is assigned the interrupt portion. The processor system 2 is switched from the first to the second mode in response to receiving a switching signal, such as an interrupt signal.

Fig. 2 shows the main portion assigned to the main routine. Fig. 3 shows the portion assigned to the interrupt routine. Like components to those of Fig. 1 are referred to by the same reference numeral.

As can be seen from Fig. 2, the main CPU retains all the low latency and pipelined units, such as the floating point and integer multiplier and divider and a complex part 16a of the load store. As can be seen from Fig. 3, the sliced processor includes a simple part 16b of the load store, integer units INT and BF and the slice register 14. The sliced processor can therefore only execute single cycle instructions and simple load stores, involving no pipelined or parallel execution. The simple structure of the sliced portion avoids the need to support a re-order function, which is normally performed as part of the sequencer 6. This also means that the slice operation can be performed immediately without the need to recover data from the reorder function.

The load store 16 is divided into the complex part 16a for the main routine and the simple part 16b for the interrupt routine. In the first normal mode of operation , the simple part 16b is inactive.

The processor system 2 switches to the second mode when a first level interrupt occurs. In the second mode, the sequencer 6 splits the task flow and starts fetching up to one instruction from each flow every clock. The instructions for the main task flow are prefetched and held in prefetch buffer 20 and the instructions for the interrupt task flow are prefetched and held in prefetch buffer 22. In the preferred embodiment, for each fetch during the second sliced mode of operation, four instructions, including the main task instructions and the interrupt instructions are fetched from the cache 18 and held in the respective prefetch buffer 20 or 22.

The sequencer 6 issues up to one instruction every clock cycle to the execution resources of the main portion (Fig. 2), via control bus 10, and up to one instruction every clock cycle to the execution resources of the sliced portion (Fig. 3), via control bus 8. For the interrupt task flow, if the sequencer receives an instruction which requires the use of a non-available execution resource, the sequencer generates an exception. Contention between the two task's instruction fetches is eliminated by having the two memory buffers 20 and 22: one for each task.

When the interrupt task has been completed, the interrupt routine executes a 'return from interrupt' instruction. In response to this instruction, the system 2 returns to the first mode of normal operation wherein the system operates as a dual issue system. The contents of the slice register file 14 remains valid and can be used next time an interrupt signal is generated.

The above description refers to a first level interrupt, which does not require the saving/restoring of any state, as opposed to a nested interrupt.

From the above, it will be appreciated that the implementation of the present invention requires the duplication of some internal registers, including an instruction pointer (not shown) in the sequencer 6, a machine state/control register and some working registers, such as the slice register file 14. Execution resources, such as ALU's, on-chip memories, bus interface units etc. can be shared between the main portion and the interrupt portion.

In some applications, it may be desirable to dedicate some simple execution resource solely for use by the interrupt task.

Only a small amount of control logic 7 in the sequencer 6 is required to implement the invention.

In a preferred embodiment, the control logic 7 presents unit busy signals to the main portion for those units and data buses that have been allocated to the slice portion, while allowing the sequencer 6 to decode instructions from the interrupt task flow for the allocated slice portion units.

Fig. 4 shows part 30 of the control logic 7 in the sequencer 6. The part 30 comprises a first instruction decoder 32 and a second instruction decoder 34 for decoding instructions fetched from the cache 18. Each one of the decoders 32, 34 is coupled to a respective one of the control buses 8, 10 so as to receive unit busy signals from the units and to transmit unit enable signals thereto. Additional logic 36 is coupled to the second decoder 34. The logic 36 is also coupled to receive a slice signal, which when active indicates that the system has switched to the second sliced mode, and to receive the unit busy signals and dummy busy signals.

In the first normal mode of operation, the slice signal is inactive, and the first 32 and second 34 decoders decode and then issue two instructions to the control buses 8 and 10 per clock cycle.

When the system 2 switches to the second sliced mode of operation, the slice signal is active, whereby the dummy busy signals are coupled to the second decoder 34. These dummy busy signals indicate that the units and buses which have been assigned to the slice portion are busy. The first decoder 32 decodes the instructions for the interrupt task flow and the second decoder 34 decodes the instructions for the main task flow.

The instruction set of the interrupt task is a proper subset of the instruction set of the main CPU. This ensures that a single software environment exists. A further advantage is that additional, application specific mechanisms are easily added to enhance specific functionality, such as providing the sliced processor with ROMed functionality or dedicated control registers, or selected state sharing with the main CPU.

It will be appreciated that whilst the slice processor is handling the interrupt task in the foreground, the other resources are not redundant, but are utilised to continue processing the background task. This ensures optimum throughput and also that there is no under utilisation of the main CPU during interrupts.

Very little additional hardware is required in order to implement the slice processor and thus, the cost for its implementation is very low which provides a number of advantages. The insignificant implementation cost for the slice processor, and the sliced processor's instruction set compatibility, provide distinct advantages in cost sensitive real-time applications, such as fragmented markets. Since it is uneconomic to provide off-the-shelf solutions for each such market, the slice instruction set compatibility with that of the main CPU, makes it possible to delegate the responsibility of the application development to the user. Thus, the processor system in accordance with the invention provides a flexible, low cost generic product.

For example, if a processor is equipped with a generic serial interface unit, one user could program the slice processor to implement a processor-tohost simple interface, while another use could program the slice processor to implement all the lower layers of an Ethernet LAN protocol (while higher layers could be executed in the background on the main CPU). The simplicity of the first user's application is not burdened by the complexity of the second user's application.

Although the processor system in accordance with the present invention has been described such that the system switches between the first mode and second mode on receipt of an interrupt signal, the processor system can be arranged to be switched, between the first and second modes, in response to receiving any context switching signal.

The assigning of the execution resources described herein are by way of example only. It will be appreciated that different units may be assigned between the different tasks.

Although the invention has been described with reference to a processor system which, in a second mode, processes two tasks simultaneously, it is not intended to limit the invention thereto. The processor system may be arranged to support any number of tasks simultaneously. Although, the increase in size and complexity may set a practical limit to the number of tasks which can be processed at any one time.

Claims

1. A processor system for processing a plurality of tasks, the processor system comprising a set of execution resources and control means for switching the processor system between a first mode of operation and a second mode of operation, wherein in the first mode of operation, the control means assigns the set of execution resources to one of the plurality of tasks, and in the second mode of operation, the control means assigns a first subset of the execution resources to a first task and a second different subset to a second task, whereby the processor system simultaneously processes the first and second tasks.

2. A processor system according to claim 1 wherein the set of execution resources comprises a plurality of channels each having at least one execution unit, and wherein in the first mode the plurality of channels are assigned to one of the tasks and in the second mode at least one channel is assigned to the first task and at least one different channel is assigned to the second task.

3. A processor system according to claim 1 or 2 wherein the set of execution resources further comprises a general register for use by tasks in the first and second modes and a slice register for use by a task in the second mode only.

4. A processor system according to any preceding claim wherein the control means comprises: control logic for receiving a mode switching signal and for receiving in the first mode the instructions of the task to be processed and for activating the set of execution resources in dependence on the received instructions and for receiving in the second mode a first set of instructions for the first task and a second set of instructions for the second task and for activating the first subset of execution resources in dependence on the received first set of instructions and for activating the second set of execution resources in dependence on the received second subset of instructions.

5. A processor system according to claim 4 further comprising: memory means for storing the instructions for the plurality of tasks; and a plurality of memory buffers coupled to the memory means and to the control logic, each of the memory buffers being arranged to temporarily hold the instructions of the associated task when the task is to be processed, wherein the plurality of memory buffers are arranged such that in the second mode of operation at least one memory buffer is assigned to the first task and at least one different memory buffer is assigned to the second task.

6. A processor system according to claim 4 or 5 wherein the mode switching signal is an interrupt signal and the second task is an interrupt routine.

7. A processor system according to any preceding claim wherein the first task processed in the second mode of operation is a continuation of the task processed in the first mode of operation.

8. A processor system for processing a plurality of tasks, the processor system comprising: a plurality of channels, each channel having at least one execution unit; and control means for switching the processor system between a first mode of operation and a second mode of operation in response to a mode switching signal, wherein in the first mode of operation, the control means assigns the plurality of channels to one of the plurality of tasks, and in the second mode of operation, the control means assigns at least one channel to the first task and at least one different channel to the second task, whereby the processor system simultaneously processes the first and second tasks.

9. A processor system substantially as hereinbefore described with reference to the accompanying drawings.