GB2283128A - A memory device incorporating a quantum dot array - Google Patents

Abstract

A memory device comprises a source (15), a drain (16) coupled to a 2DEG region (13) in a substrate (10) and a gate (5) that includes an array of dot regions (3, 4) each capable of holding a quantised amount of electric charge. A photoconductive region (12) adjacent the array is responsive to incoming radiation to produce charge carriers for establishing a stored charge associated with each dot region. In a write mode, the gate is held at a write voltage Vw to set a charge on the dots and incoming radiation produces a stored charge pattern in the photosensitive region according to the charge of the dots. The level of stored charge is read by detecting peaks in the source-drain current which occur as the gate voltage is swept through a value corresponding to Vw. <IMAGE>

Description

MEMORY DEVICE This invention relates to a memory device utilising a quantum dot array.

Recently, it has been demonstrated that Coulomb charging effects can be used to create a novel memory device (K.

Nakazato, R. J. Blaikie, J. R. A. Cleaver and H. Ahmed "Single-Electron Memory" Electronic Letters 29, p 384 [1993]). See also our co-pending patent application Nos.

GB 9226382.1 and EP 93301982.0. The advantage of such a Coulomb Blockade limited memory device is that the amount of charge needed to store information can in principle be reduced to a single electron. However, in order to observe Coulomb charging effects at room temperature, an extremely small (of the order of 5nm) quantum dot must be fabricated.

This is difficult to achieve reproducibly. It has however been demonstrated that an array of nanometre scale quantum dots can be made by simply evaporating a very thin metal layer - (B.Abeles, "Granular Metal Films", Applied Solid State Science 6, pp 1-118 [1976]). A memory device based on Coulomb charging of such a quantum dot array would be much easier to manufacture and should operate at higher temperatures than a single quantum dot device.

A memory effect in a two-dimensional array of dots was discovered by J. Lambe and R. C. Jaklevic - see "Charge Quantisation Studies Using a Tunnel Capacitor", Physical Review Letters, p. 1371 [1969]. Figure 1 herein shows a typical device structure as proposed by Lambe and Jaklevic.

An aluminium back contact 1 is covered by a thick layer of Awl203. An extremely thin ( < 10 nm) metal layer is evaporated onto the oxide layer 2. This forms nanometre scale metal droplets or dots 3. The dots are then oxidised to form a thin insulating tunnel barrier 4 and the arrangement is covered with an aluminium electrode layer 5.

When a voltage V is applied between the electrode layer 5 and the back contact 1, electrons tunnel through the thin oxide layer 4 to bring the dots to the same potential as the electrode layer 5. At low temperatures where kT is less than the typical charging energy of one of the dots 3, each dot must contain an integer number of electrons. The ith dot then can only brings its potential to some voltage vj=V*e/C,.

where Ci is the capacitance between the ith dot and the back electrode 1. Thus, the charge on the dot 3 is limited by the Coulomb Blockade effect.

It is possible to show that the total change in the capacitance C of the device due to the presence of the array of dots 3 is given by:

(1) where ai is a constant, independent of V. If the distribution of V,'s among the dots is random then the individual contributions will cancel one another leaving AC = 0. If however the distribution of Vj'S is specially configured so that it peaks at a particular voltage Vg then the capacitance will contain an oscillatory component due to the dots, whose magnitude will also be peaked at Vg.

The memory effect relies on the ability to set the distribution of Vj'S to be peaked at a particular voltage or set of voltages. This can be accomplished by using the semi-mobile charge in the thin tunnel oxide. When voltage Vg is placed across the device between the electrodes 1, 5 at high temperature, for example room temperature, the charge in the tunnel oxide 4 lines up to balance the difference between the potential of the dot 3 and the potential of the top electrode 5. As the device is cooled towards absolute zero, this charge in the tunnelling oxide freezes into position. The device thus "remembers" the voltage at which it was cooled down. When the applied voltage V between the electrodes 1, 5 is swept through a range of values including Vg, at low temperature, an oscillation is observed in the total capacitance C, the oscillation being centred upon Vg. Thus, the device can be used as a memory since the voltage value Vg is stored in the device and detected by the capacitance oscillation that occurs between the electrodes 1, 5 when the applied voltage V is swept through a range of values.

However, this prior arrangement is impractical as a memory device since it needs to be cooled towards absolute zero, for example in a dilution refrigerator and this manner of scanning using external connections and a voltage source, is rather cumbersome.

In accordance with the present invention, a memory device is provided which includes an in-built conductive path which can be used to detect charge stored in association with the dots. Also, in another aspect, the invention provides a memory device in which charges are associated with the dots by means of an input optical pulse rather than by the prior art "freezing" technique.

Broadly stated, in a first aspect, the invention provides a memory device comprising an array of dot regions capable of holding a quantised amount of electric charge, means responsive to the charge storage capacity of the dot regions for storing a quantised charge level associated with each dot, and means defining adjacent the array an electrically conductive path having a conductivity which varies as a function of the stored charges associated with the dot regions.

Thus, by means of the invention, the conductive path provides a means for sensing the stored information associated with the dots. Conveniently, the conductive path extends between source and drain regions in a substrate, the dot regions forming a gate array with the gate array and conductive path being arranged one overlying the other between the source and drain regions. The conductive path may be formed as an essentially twodimensional electron gas.

In a second aspect, the invention provides a memory device comprising an array of dot regions capable of holding a quantised amount of electrical charge, writing means including a photoconductive region adjacent said array and responsive to incoming optical radiation to produce charge carriers for establishing a stored charge associated with each dot region, and reading means responsive to the stored charges associated with the dot regions for providing a memory output.

The photoconductive region thus can establish a charge pattern associated with the dots at room temperatures and there is no need to cool the device in order to freeze the charge pattern.

In order that the invention may be more fully understood, an embodiment thereof will now be described by way of example with reference to the accompanying drawings in which: Figure 1 is a schematic sectional view through a prior art memory device; and Figure 2 is a sectional view through an example of a memory device in accordance with the invention.

The memory device according to the invention shown in Figure 2 can be considered as a modification of the arrangement shown in Figure 1. The device consists of a substrate 10 typically formed of i-GaAs which, by conventional techniques is formed with a layer of AlGaAs 12 so as to provide a AlGaAs/GaAs heterojunction which produces an essentially two-dimensional electron gas 13 (2DEG) in a manner well known per se.

The layer 12 is overlaid by a photorefractive layer.

Suitable materials are described in "Photorefractive Materials and their Applications in Topics in Applied Physics" P. Gunter and J. P. Huignard (Springer, Berlin, 1988), Vol. 61.

Source and drain regions 15, 16 are provided to make contact with the 2DEG 13. The contacts 15, 16 may be formed by electron beam lithography and heavy doping e.g.

to form n+ - GaAs regions for example by ion implantation.

An array of metal dots 3, typically of aluminium formed as described with reference to Figure 1, are deposited on the surface of the photorefractive layer 14. The dots will be of generally similar diameter but will vary from dot to dot. A typical diameter is of the order of 5nm. As described previously, the dots are oxidised so as to become covered with a tunnelling oxide layer 4 of A1203 and an overlying metal layer 5 is thereafter formed to provide a gate electrode. The array of dots 3 thus form a gate array, which influences the conductivity of the 2DEG which, in turn influences the conductivity between the source and drain contacts 15, 16.

The change in conductance for the 2DEG 13for a given change in capacitance due to the array of dots 3, is given by Aa=eAC(Vg-Vt)'L (2) where Vg is the stored voltage associated with the array of dots 3, as discussed with reference to Figure 1, Vt is a threshold voltage for conduction between the source and drain 15, 16 of the device, R is the mobility of the 2DEG, Aa is the change in conductivity, and AC is the change in capacitance.

From this equation, it can be seen that the conductance of the 2DEG is proportional to the capacitance of the dot array gate and thus can be used as a probe for the memory effect in the dot array gate.

Furthermore, an improved way of writing charges to the individual dots 3 is provided by means of the photorefractive layer 14 so that memory storage can be instigated by means of a light pulse rather than through thermal cycling as in the prior art.

The write and read modes for the device are as follows: Write mode: The gate electrode 5 is held at a write voltage Vw which is selected to be within the normal operating range of the device. As a result, electrons tunnel through the oxide layer 4 to the dots such that they assume a voltage Vi and the number of electrons on each dot is limited by the Coulomb Blockade effect, as discussed hereinbefore in connection with equation (1).

The device is then exposed to light, possibly from a LED (not shown) in order to excite carriers in the photorefractive material 14. The released carriers arrange themselves to balance out the voltage difference Vw - V between the dots 3 and the gate electrode 5. The light source is then shut off and the charge carriers remain trapped within the photorefractive material 14 in the charge configuration determined by the dot array. The process may be repeated at a number of different write voltages to store a number of different values of Vw.

Read mode: The conductance of the device is measured as a function of gate voltage. Thus, circuitry (not shown) is connected to the source and drain regions 15, 16 to measure the conductance of the 2DEG 13 whilst the gate voltage applied to electrode 5 is varied. At each of the write voltages Vw, a characteristic spike in the conductance is observed. At each of these values, a large percentage of dots line up with the gate voltage.

The reading of the device is non-destructive and the memory storage time is determined by the storage time of the photorefractive material 14.

A number of modifications and variations to the device are possible. For example, whilst the embodiment of Figure 2 uses a photorefractive layer to produce the charge carriers, the previously described "freezing" method could be used and sensed by means of the 2DEG 13 or other means could be used to provide the charge carrier pattern associated with the dots. However, the device of Figure 2 has the advantage that it may be possible to operate at room temperatures, without freezing.

Whilst the device shown in Figure 2 is fabricated in GaAs technology, other techniques can be used and the 2DEG could be formed using a SiO2 fabrication technique.

As used herein the term photoconductive and photorefractive are to be interpreted broadly to include materials which are responsive both to visible and non-visible radiation.

Claims (14)

1. A memory device comprising; an array of dot regions capable of holding a quantised amount of electric charge; means responsive to the charge storage capacity of the dot regions for storing a quantised charge level associated with each dot; and means defining adjacent the array an electrically conductive path having a conductivity which varies as a function of the stored charges associated with the dot regions.

2. A memory device according to Claim 1 including a photoconductive region adjacent said array and responsive to incoming optical radiation to produce charge carriers for establishing the stored charge associated with each dot region.

3. A memory device comprising; an array of dot regions capable of holding a quantised amount of electric charge; writing means including a photoconductive region adjacent the array and responsive to incoming radiation to produce charge carriers for establishing a stored charge associated with each dot region; and reading means responsive to stored charges associated with the dot regions for providing a memory output.

4. A memory device according to any preceding Claim including a substrate, means defining source and drain regions in the substrate, said conductive path extending between the source and drain regions, and said dot regions forming a gate array, the gate array and the conductive path overlying one another between the source and drain regions.

5. A memory device according to Claim 4 including means defining an essentially two dimensional electron gas extending between the source and drain regions whereby to provide said conductive path.

6. A memory device according to Claim 4 or 5 including gate electrode means for applying an electric field across said array for writing a stored charge pattern in association with the dot regions.

7. A memory device according to any preceding Claim wherein the charge capacity of each of the dot regions is limited by the Coulomb blockade effect.

8. A memory device according to any preceding Claim wherein said dots have been formed by selective deposition of a metallic vapour.

9. A memory device according to Claim 8 wherein said dots are covered by a tunnelling oxide layer.

10. A memory device according to Claim 9 including a conductive gate electrode covering said dot array.

11. A memory device substantially as hereinbefore described with reference to Figure 2 of the accompanying drawings.

12. A method of writing data into the memory device of Claim 2, 3 or any preceding claim dependent thereon, including applying a predetermined voltage across the dot array, and exposing the photoconductive region to incoming radiation so as to form a stored charge pattern associated with the dot regions.

13. A method of reading data from a memory device written with data according to the method of Claim 12 including measuring the conductivity of the device as a function of voltage applied to the dot array.

14. A method of reading and writing data to and from a memory device substantially as hereinbefore described with reference to Figure 2 of the accompanying drawings.