GB2283127A - Thin-film transistors with reduced leakage - Google Patents

Abstract

In a liquid-crystal display comprising thin-film field-effect transistors (TFTs) on a substrate (10), reduction in side-wall leakage current of a TFT is achieved by giving the current path through the channel (1) extra length (L2+L3) adjacent to the side wall 13 of the TFT thin-film body (11) compared with its length (L1) in the area of the body (11) away from the side wall (13). This extra length (L2+L3) is due to an unmodulated drain-adjacent part (7) of the channel region (1) adjacent to the side wall (13). The unmodulated part (7) is substantially intrinsic and unmodulated by the gate (16) in operation of the transistor. This unmodulated part (7) spaces the drain electrode (5) laterally away from the gate electrode (16) at the area adjacent to the side wall (13) where high leakage currents may be generated. <IMAGE>

Description

DESCRIPTION ELECTRONIC DEVICES COMPRISING THIN-FILM TRANSISTORS This invention relates to electronic devices comprising thin-film field-effect transistors (hereinafter termed "TFTs"), and in particular to such devices in which at least some of the TFTs have a low leakage current in their off-state. The device may be, for example, an active-matrix liquid crystal display or other flat panel display, or any other type of large area electronic device with TFTs, for example, a thin-film data store or an image sensor.

There is currently much interest in developing thin-film circuits with TFTs on glass and on other inexpensive insulating substrates for large area electronics applications. Such TFTs fabricated with amorphous or polycrystalline semiconductor films may form the switching elements of a cell matrix, for example in a flat panel display as described in published European patent application EP-A-O 464 897 (our reference PHB33646), the whole contents of which are hereby incorporated herein as reference material. A recent development involves the fabrication and integration of circuits from TFTs (often using polycrystalline silicon) as, for example, integrated drive circuits for such a cell matrix.

Each TFT on the device substrate comprises a semiconductor thin-film body of disordered semiconductor material which provides a channel region of substantially intrinsic conductivity type between source and drain electrodes of the transistor; the channel region is accommodated in the semiconductor thin-film body adjacent to both a major surface of the body and a side wall of the body; a gate electrode is capacitively coupled to the semiconductor thin-film body for modulating in the channel region in operation of the transistor a current flow of charge carriers of a first conductivity type between the source and drain electrodes.

Depending on the TFT technology employed, the disordered semiconductor material may be amorphous, or polycrystalline or microcrystalline in nature. For most present-day TFTs the semiconductor is silicon. For polycrystalline silicon TFTs, the thin-film which provides the channel-region body may be deposited as polycrystalline silicon, or it may be deposited as amorphous silicon which is subsequently converted in situ on the substrate into polycrystalline silicon by heating either in a furnace or with a laser beam. However, even when the resulting channel-region body is of large-grain polycrystalline silicon, it has a high density of charge trapping states due to the disorder in the film. These charge trapping states cause the material to behave quite differently from monocrystalline silicon. Thus, for example, TFTs (even with large-grain polycrystalline silicon) have a high leakage current and a high threshold voltage as compared with field-effect transistors formed in monocrystalline silicon. Furthermore low doping levels generally have little or no effect in changing the substantially intrinsic conductivity type which results from the high density of trapping levels near the middle of the bandgap of the semiconductor material.

In order to reduce TFT leakage current, various proposals have been made, for example as disclosed in published European patent application EP-A-O 408 129 (our reference PHB33571) and in published Japanese patent applications (Kokai) JP-A-02-216870 and JP-A-04-158580. The whole contents of these three published patent applications are hereby incorporated herein as reference material.

EP-A-O 408 129 teaches passivating the trapping states in the polycrystalline material (e.g. by hydrogenation) and implanting dopant of a second conductivity type (opposite to that of the charge-carriers of the conduction channel) at the back of the channel region. Although this treatment is remarkably effective, there remains a leakage current whose magnitude it is desirable to reduce further. This remaining leakage current appears to be associated predominantly with the side wall of the thin-film body.

JP-A-04-158580 teaches reducing the current which flows adjacent to the side wall by forming a hole in the gate electrode in the area away from the side wall and doping the thin-film body in this area away from the side wall to the same doping level as the source and drain electrodes. Thus, the doped area no longer forms part of the channel region, and current flow between the source and drain electrodes in operation of the TFT should generally pass through this doped area and away from the side-wall.

It is an aim of the present invention to provide another means for reducing TFT leakage current at the side wall of the TFT chånnel-region body.

According to the present invention there is provided an electronic device comprising thin-film field-effect transistors on a substrate of the device, each transistor comprising a semiconductor thin-film body which provides a channel region of substantially intrinsic conductivity type between source and drain electrodes of the transistor, the channel region being accommodated in the semiconductor thin-film body adjacent to both a major surface of the body and a side wall of the body, a gate electrode being capacitively coupled to the semiconductor thin-film body for modulating in the channel region in operation of the transistor a current flow of charge carriers of a first conductivity type between the source and drain electrodes, the current path through the channel region having extra length adjacent to the side wall of the semiconductor thin-film body as compared with its length in the area of the semiconductor thin-film body away from the side wall.

In accordance with the present invention, such a device is characterised in that the extra length of the current path adjacent to the sidewall is due at least in part to inclusion of an unmodulated drain-adjacent part of the channel region adjacent to the side wall, which drain-adjacent part is unmodulated by the gate electrode in operation of the transistor and spaces the drain electrode laterally away from the gate electrode at the area adjacent to the side wall.

The semiconductor thin-film body may be of a disordered silicon material, for example polycrystalline silicon or microcrystalline or amorphous silicon, or another semiconductor material. Perferably the unmodulated drain-adjacent part of the channel region adjacent to the side wall is of substantially intrinsic conductivity type, but it may instead comprise a low doping concentration of the first conductivity type.

Since the occurrence of leakage current is related to the high density of trapping states in the disordered material of the channel region, it is surprising that the side-wall leakage currents can be reduced by including an extra length of this unmodulated channel-region material adjacent to the drain electrode. The actual effects and precise cause of these leakage currents are not fully understood and vary with TFT technology. To the extent that the leakage currents may be related to the capacitive coupling arrangement of the gate electrode at the side wall of the channel region (e.g. due to a thinning of a gate dielectric layer at the side wall, or involving charge-trapping effects or mobile ions effects at the interface of the gate dielectric layer and the channel region at the side wall), the inclusive of the unmodulated extra side-wall part of the channel region as a lateral spacing between the drain and gate electrodes can reduce such an effect of the capacitive coupling arrangement at the modulated part of the channel region. To the extent that the side-wall leakage currents may be due to a release of charge trapped in states adjacent to the side wall, the extra length of the path through an unmodulated part of intrinsic conductivity type increases the resistance along this path and so reduces the current, especially as the extra part is not modulated by the gate electrode. To the extent that the side-wall leakage currents may be due to field enhanced generation of charge carriers at the trapping states adjacent to the side wall, the extra unmodulated part of the channel region reduces the electric field in this area by serving as a sidewall field-relief region between the gate electrode and the drain electrode in this area adjacent to the side wall. Thus, the bias voltage between the gate and drain electrodes (in, for example, the off-state of the TFT) is dropped progressively along this unmodulated side-wall part of intrinsic conductivity type, so reducing field intensity in this area.

The part of the channel region modulated by the gate electrode may be of substantially the same length adjacent to the side wall as in the area away from the side wall. Thus, the gate electrode may be of uniform width, and so the TFT may have a simple compact layout geometry.

The inclusion of the unmodulated extra side-wall part of the channel region in accordance with the present invention is preferably used in conjunction with other measures to reduce TFT leakage currents, assuming that a very low level of leakage current is desired in a particular device application.

Thus, for example, the TFT body may comprise hydrogen-passivated polycrystalline semiconductor material, having this extra side-wall part of the channel region adjacent to the drain electrode and having dopant implanted at a back face of the channel region to suppress a leakage channel at this back face in accordance with the teaching in EP-A-O 408 129.

Furthermore, the drain electrode may be designed to have a convex-shaped edge which adjoins the unmodulated drain-adjacent part of the channel region adjacent to the side wall and which extends across the thickness of the semiconductor thin-film body.

Such a convex-shaped edge of the drain electrode may be designed using the teaching in JP-A-02-216870 to reduce a high electric field intensity at the drain edge, for suppressing an increase in leakage current when a high drain voltage is applied. However, it should be noted a TFT in accordance with the present invention already experiences field-relief at the drain edge due to the lateral spacing of the gate and drain electrodes by the unmodulated extra part of the channel region adjacent to the side wall, whereas the TFTs of JP-A-02-216870 still experience a high field intensity at the drain edge adjacent to the side wall because of the overlap of the gate electrode in this area. Thus, although the current path through the channel region of the JP-A-02-216870 TFT structures has extra length adjacent to the side wall, this extra length is entirely overlapped by and modulated by the gate electrode; the advantages of the present invention are not achieved in the JP-A-02-216870 TFT structures. Furthermore, in this context it may be noted that, in the JP-A-04-158580 TFT structures, the current path in the channel-region areas away from the side wall is shorter than that adjacent to the side wall (due to the doping of the central area at a hole in the gate electrode); however, the advantages of the present invention are not achieved in the JP-A-04-158580 TFT structures because, inter alia, the whole length of the channel region adjacent to the side wall of the JP-A-04-158580 TFT structures is overlapped by and modulated by the gate electrode.

Other features of the present invention, and their advantages, are illustrated specifically in embodiments of the invention now to be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a schematic plan view of a thin-film field-effect transistor in an area of an electronic device in accordance with the present invention; Figure 2 is a schematic cross-sectional view on the line II-II of Figure 1; Figure 3 is a schematic plan view of the transistor structure of Figure 1 at a stage in its manufacture, and Figures 4 and 5 are schematic plan views similar to that of Figure 1 but showing two modified transistor structures also in accordance with the invention.

It should be noted that all the drawings are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of the Figures have been shown exaggerated or reduced in size for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in the different embodiments.

The TFTs illustrated in the drawings may be used in a variety of large-area electronic devices, for example a flat panel display as illustrated in EP-A-O 464 897, or a large-area image sensor, or a data store. The device has a substrate 10 on which thin-film circuitry is formed, for example a matrix of TFT switching transistors and TFT drive circuits. Low levels of off-state leakage currents are particularly important in switching transistors, and so the TFT illustrated in the drawings may be designed as a switching transistor in the cell matrix or in the drive circuit of such a device. The particular TFT technology and the transistor parameters are chosen as appropriate for the desired device specification. By way of a convenient example, it may be assumed that a particular embodiment of the TFT of Figures 1 to 3 is formed using the passivated polycrystalline silicon TFT technology described in EP-A-O 408 129.

The device substrate 10 is electrically insulating at least adjacent to its top surface. It may be of glass or any other low-cost insulating material, and in a particular embodiment it may comprise an upper layer of silicon dioxide on a glass base as described in EP-A-O 408 129. A large number of the individual TFTs illustrated in Figures 1 to 4 are generally formed on the device substrate 10 and are interconnected by thin-film conductor patterns extending on the substrate 10.

Each transistor comprises a silicon thin-film body 11 of the disordered semiconductor material (e.g. hydrogenated polycrystalline silicon) which provides a channel region 1 of substantially intrinsic conductivity type (I) between highly-doped (N+) source and drain electrodes 4 and 5 of the TFT. The intrinsic channel region 1 is accommodated in the body 11 adjacent to both a major surface 12 and a side wall 13 of the body 11. A gate electrode 16 is capacitively coupled to the silicon body 11 for modulating in the channel region 1 a current flow of charge carriers of a first conductivity type (electrons, in the n-channel TFT illustrated in the drawings) between the source and drain electrodes 4 and 5. For example as described in EP-A-O 408 129, the gate electrode 16 may be of highly-doped (N+) polycrystalline silicon on a dielectric film 17 (e.g. of silicon dioxide and/or nitride) on the polycrystalline silicon body 11. As illustrated in Figure 1, the gate electrode 16 (and the underlying dielectric film 17) may extend across the top major surface 12 (where the bulk of the channel region is located) and over the side wall 13 and onto the substrate 10. The thin-film conductor patterns which interconnect the individual TFTs on the substrate 10 may comprise an extension of the gate electrode film 16 or a thin-film metal connection to the electrode pattern 16. Figure 2 illustrates thin-film metal connections 14 and 15 to the source and drain electrodes 4 and 5; these connections 14 and 15 may also extend onto the substrate 10 to form part of the interconnections, although the patterns 14 and 15 are not shown in Figure 1 for the sake of simplicity and clarity in the drawing.

Unlike the TFT described in EP-A-O 408 128, the TFT of Figures 1 and 2 has a modified geometry in accordance with the present invention. Thus, the current path through the channel region 1 has extra length (L2 + L3) adjacent to the side wall 13 as compared with its length (L1) in the area away from the side wall 13. In accordance with the present invention, this extra length of the current path adjacent to the side wall 13 is due in part to the inclusion of an unmodulated drain-adjacent part 7 of the channel region 1 adjacent to the side wall 13. This drain-adjacent part 7 is unmodulated by the gate electrode 16 in operation of the TFT, and it may retain the substantially intrinsic conductivity type (I) of the remainder of the channel region 1. The extra length (L2 + L3) of the current path adjacent the side wall 13 of the TFT of Figures 1 and 2 is also due in part to inclusion of source-adjacent part 6. This part 6 of the channel region 1 adjacent the side wall 13 is located laterally between the source and gate electrodes 4 and 16 (as viewed perpendicular to the surface 12) and is unmodulated by the gate electrode 16 in operation of the TFT. Figure 2 shows the parts 6 and 7 having intrinsic conductivity type (I).

There are a variety of effects and mechanisms which appear to play a role in generating and affecting side-wall leakage currents in TFTs. The actual role and relative importance of each of these effects and mechanisms vary depending on the TFT technology employed, the TFT type, the TFT parameters chosen for a give device specification, and the actual process steps used to manufacture the TFT. By way of example, Figures 1 and 2 illustrate an application of hydrogenated polycrystalline silicon TFT technology to form a TFT type in which the source and drain electrodes 4 and 5 are formed as doped regions (N+) in the body 11, the TFT is n channel, and the insulated gate electrode 16 extends from the top surface 12 over the side-wall 13.

Several side-wall leakage effects seem to be dependent on the capacitive coupling arrangement of the gate electrode 16. Thus, for example, the thickness of the gate dielectric film 17 where it deposits over the side wall 13 may differ from its thickness on the major surface 12. Generally, the gate dielectric film 17 is found to be thinner on the side wall 13, although the main thickness reduction may be very local, for example at the edges between the surface 12 and side wall 13 and/or between the side wall 13 and the substrate. When process inhomogeneities are present across the width of the substrate 10, the extent of the dielectric thinning may vary for TFTs at different locations across the substrate 10. For the particular TFT to which it relates, the thinning of the gate dielectric 17 results in a reduction in threshold voltage and an increase in electric field at the side wall 13 where the gate electrode 16 extends over the side wall 13.

These effects are particularly pronounced due to the high density of trapping states in the disordered semiconductor material adjacent to the side wall 13. They can affect charge-trapping at surface states at the side-wall 13 and drift of mobile ions in the dielectric film 16 at the side wall 13. However, in the TFT structures of Figures 1 and 2 in accordance with the present invention, the channel parts 6 and 7 forming the extra length (L2 + L3) of the channel region 1 adjacent the side wall 13 are not overlapped by and so are not modulated by the gate electrode 16; and so the channel parts 6 and 7 space these leakage effects away from the source and drain electrodes 4 and 5. Thus, for example, a side-wall leakage current due to charge accumulated at the side wall 13 below the insulated gate electrode 16 arises at a distance of at least L3 or L2 from the source or drain electrode 4 or 5, and the current must pass through the high-impedance intrinsic parts 6 and 7 to appear at either the source electrode 4 or the drain electrode 5. The magnitude of the resulting leakage current is reduced. The extra length (L2 + L3) provided in accordance with the invention increases the resistance of the current path and also introduces unmodulated intrinsic parts 6 and 7 into the path adjacent to the source and drain electrodes 4 and 5.

Other side-wall leakage effects seem to be dependent on electric field intensities which occur in various regions under the different operating conditions of the TFT. A field-enhanced generation mechanism (for example tunnel emission or Poole-Frenkel emission) may be the source of the leakage current; carrier drift and ion drift also occur in the electric field, and in some situations avalanche breakdown may even occur. The inclusion of the unmodulated intrinsic parts 6 and 7 reduces leakage effects related to the field intensity below the gate electrode 16; the reduction is due, inter alia, to its spacing L3 and L2 from the source and drain electrodes 4 and 5 at the side wall 13, as described in the previous paragraph. Furthermore the longer distance (L1 + L2 + L3) between the source and drain electrodes 4 and 5 at the side wall 13 reduces leakage effects related to the field intensity between the source and drain electrodes 4 and 5.

In the off-state of the TFT and with high drain bias, particularly high fields may occur between the gate and drain electrodes 16 and 5. Thus, in choosing the desired extent L2 of the unmodulated intrinsic drain-adjacent part 7 and the desired edge shape of the drain electrode 5 in this area, this side-wall part 7 adjacent the drain electrode 5 should be regarded as a potentially high field area and hence a leakage charge generation area.

In the TFT structure in accordance with the present invention, the unmodulated extra intrinsic part 7 spaces the drain electrode 5 laterally away from the gate electrode 17 by the distance L2 at the side-wall 13, as illustrated in the plan view of Figure 1. This lateral spacing (viewed perpendicular to the surface 12) thus separates the drain electrode 5 from the surface states which are below the edge of the gate electrode 16 and which act as generation centres. Furthermore, this lateral spacing adjacent to the side wall 13 can introduce an unmodulated field-relief region 7 into the TFT structure so reducing the field intensity in this area by a progressive dropping of the drain-gate bias voltage along the unmodulated side-wall part 7. Furthermore, in the TFT structure of Figures 1 and 2, the edge of the drain electrode 5 has been curved as it approaches the side wall 13 to reduce further the field intensity at the drain edge adjacent to the side wall 13. Thus, the drain electrode 5 has a convex-shaped edge which adjoins the unmodulated drain-adjacent part 7 (as illustrated in Figure 1), and which extends across the thickness of the body 11 (as illustrated in Figure 2 by the solid line between parts 7 and 5 and the broken line between parts 7 and 1). The main edge of the drain electrode away from the side wall 13 is a straight plane substantially coinciding with the edge of the gate electrode 16, i.e. in a plane through the broken line between parts 7 and 1 in Figure 2 and perpendicular to the side wall 13. The gate electrode 16 in the TFT of Figures 1 and 2 has a uniform width (corresponding to L1) with straight edges, and so the channel region modulated by the gate electrode 16 is of substantially the same length L1 adjacent to the side wall 13 as in the area away from the side wall 13.

In a specific example of the TFT of Figures 1 and 2, the active channel length L1 (corresponding to the width of the gate electrode 16) may be 4pm (micrometres), the dimension W1 may be 5ym, and each of the dimensions L2, L3, W2 of the extended regions 6 and 7 may be 2yam. Thus, in this specific example, the length (L1+L2+L3) of the current path through the channel region at the side wall 13 is doubled compared with its modulated length L1 both at the side wall 13 and away from the side wall 13. Preferably the dimensions L2,L3,W2 should be large to reduce sidewall leakage effects. The maximum dimension W2 may be limited by the maximum width of the TFT body 11 which can be accommodated in a given area of the TFT circuit on the substrate. As described later with reference to Figure 4, the dimensions L2 and L3 may be increased by further extension of the parts 6 and 7 along the side wall 13 adjacent to the source and drain electrodes 4 and 5.

In the case of the TFT of Figures 1 and 2, the source and drain electrodes 4 and 5 may be formed by a dopant implant into the body 11 in known manner, using an extended gate pattern 25 as an implantation mask. Figure 3 illustrates a suitable gate mask pattern 25 which is shown hatched for clarity in understanding.

The pattern 25 has edges corresponding to the desired edge shapes of the source and drain electrodes 4 and 5 and so has extension parts 26 and 27 at its ends which cover the areas where the undoped side-wall parts 6 and 7 are to be retained. After the implant, the structure may be coated with photoresist; windows 36 and 37 (shown in broken outline in Figure 3) are defined in the photoresist over the extension parts 26 and 27 which are then etched away at the windows 36 and 37.

As mentioned already, the extended length (L2 + L3) of the channel region 1 adjacent to the side wall 13 is due to the inclusion of both source-adjacent and drain-adjacent parts 6 and 7, an advantage of which is that the leakage-generation area under the gate electrode 16 at the side wall 13 is spaced from both the source and drain electrodes 4 and 5 by unmodulated intrinsic parts (6 and 7). As shown in Figures 1 and 3, the unmodulated source-adjacent and drain-adjacent parts 6 and 7 of the channel region 1 adjacent to the side wall 13 may be of similar geometry to each other. An advantage of similar geometry for these parts 6 and 7 is that the TFT may be used with the electrodes 4 and 5 respectively, as drain and source, instead of source and drain.

However, in a special TFT design in accordance with the present invention, the unmodulated intrinsic part adjacent to the side wall 13 may be omitted from the source end of the channel region 1 and included only as part 7 at the drain end. Such a modification is illustrated in Figure 4.

Figure 4 also illustrates an elongate extension of the unmodulated intrinsic part 7 along the side wall 13 adjacent to the drain electrode. Over most of its length the drain electrode 5 is separated from the side wall 13. By this arrangement, a high field adjacent to the edge of the drain electrode 5 can be separated from a high density of trapping states at the side wall 13, and field enhanced generation of side-wall leakage current can be reduced.

The increased length of the current path in the elongate intrinsic part 7 may also reduce the side-wall leakage current by the increase in resistance, although it should be noted that the charge carriers will tend to flow along the field lines between the drain electrode 5 and the side wall 13, rather than flowing along the side wall 13. In a symmetrical TFT geometry, a similar elongate unmodulated intrinsic part 6 may be provided along the side wall 13 adjacent to the source electrode 4.

The TFT of Figures 1 and 2 comprises a single gate electrode 16 over a single channel 1. However, in TFTs in accordance with the invention, the gate electrode may be split into two or more gate fingers 16a and 16b (as illustrated in Figure 4) which overlie individual channel regions 1. The channel regions 1 are arranged On series, and the part(s) 9 of the body 11 between these individual channel regions 1 may be doped (N+) to the same doping level as the source and drain electrodes 4 and 5. An advantage of such a TFT structure is that the total channel length (comprising the sum of the individual lengths L1) can be large. The split gate fingers 16a and 16b may be connected together on the substrate 10 and so operated as a single gate electrode 16. However, the gate fingers 16a and 16b may have separate connections and so the TFT of Figure 4 may be operated as a tetrode. Although the part 9 between the gate fingers 16a and 16b is doped to the same high level as the source and drain electrodes 4 and 5, this high level doping may be masked from the side-wall adjacent parts 9a and 9b. Thus, the parts 9a and 9b may remain as unmodulated intrinsic regions to decrease further the side-wall leakage effects.

Figure 5 illustrates a further modification in the area of the body away from the side-wall. In the TFT of Figures 1 and 2 the gate electrode 16 extends laterally to the drain electrode 5 at the area away from the side wall 13 and so is capacitively coupled to the drain-adjacent part of the channel region 1 in the area away from the side wall 13. Thus, the gate electrode 16 controls the whole length L1 of the channel region 1 to the drain electrode 5.

In the modification shown in Figure 5, the channel region 1 has an unmodulated drain-adjacent part 8 in the area of the semiconductor thin-film body 11 away from the side wall 13. This unmodulated part 8 away from the side wall 13 has a shorter length L4 than the (length L2 of the unmodulated drain-adjacent part 7 of the channel region 1 adjacent to the side-wall 13.

The inclusion of such an unmodulated part 8 increases the high voltage capability of the TFT but at the expense of the resistance through the channel region 1 and the degree of control by the gate electrode 16.

In order to reduce the increased resistance resulting from the unmodulated part 8, this part 8 may be doped to be of the same conductivity type as the drain electrode 5 but with a lower doping concentration than that of the semiconductor region 5 which provides the drain electrode. Such a lower-doped part 8 can serve as a field relief region. This lower doping concentration may be provided by dopant ion implantation using the gate 16 as an implantation mask. Thus, the same lower doping concentration may also be provided in the unmodulated part 7 adjacent to the side wall 13, where it may s arrangement, the individual areas 26 and 27 of the gate mask pattern 25 were etched away at two separate windows 36 and 37 at each of the opposite side walls 13. However, instead of separate windows 36 and 37, a single long window may be used, at each of the opposite side walls 13, to expose the individual areas 26 and 27 and the adjacent side-wall end areas of the gate electrode 16. By etching away all these exposed areas1 the gate electrode 16 can be cut back entirely from the side wall 13, which may remove some types of leakage current generation at the side wall 13. In this case, the gate electrode 16 can be connected in the thin-film circuit by a thin-film metal connection which is formed in the same process steps as the source and drain connections 14 and 15 and which contacts the gate electrode 16 at a window in an insulating over-layer.

Figure 2 illustrates an n channel TFT with n type source and drain electrodes 4 and 5. However, the geometry of the present invention may be included in p channel TFTs with p type source and drain electrodes 4 and 5. The current flow through the intrinsic channel region 1 in this latter case is by holes under the control of the insulated gate electrode 17. Although Figure 2 illustrates n type source and drain electrodes 4 and 5 formed in the intrinsic body 11 by dopant implantation, the source and drain electrodes 4 and 5 may be formed instead by doped films which are deposited on the substrate 10 before the intrinsic film 11 or which are deposited subsequently on the intrinsic film 11.

Although Figure 2 illustrates the provision of the insulated gate 16 on the intrinsic film 11, an inverted TFT structure may be formed including the unmodulated intrinsic side-wall parts 6 and 7 in accordance with the invention. In this case, the gate electrode 16 is first formed on the substrate 10, then the dielectric film 17 is deposited, and then the intrinsic film 11 is deposited. Finally doped source and drain electrodes 4 and 5 may be deposited and patterned to leave the side-wall parts 6 and 7 which are not overlapped by any of the electrodes 4,5 and 16.

Although embodiments of the invention have been presented in the context of the polycrystalline silicon technology of EP-A-O 408 129, the present invention may also be used with TFTs having amorphous silicon thin-film bodies of intrinsic conductivity type, and also with thin-film semiconductor materials other than silicon.

From reading the present disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalents and other features which are already known in the design, manufacture and use of TFTs and large-area electronic devices and component parts thereof, and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims (10)

1. An electronic device comprising thin-film field-effect transistors on a substrate of the device, each transistor comprising a semiconductor thin-film body which provides a channel region of substantially intrinsic conductivity type between source and drain electrodes of the transistor, the channel region being accommodated in the semiconductor thin-film body adjacent to both a major surface of the body and a side wall of the body, a gate electrode being capacitively coupled to the semiconductor thin-film body for modulating in the channel region in operation of the transistor a current flow of charge carriers of a first conductivity type between the source and drain electrodes, the current path through the channel region having extra length adjacent to the side wall of the semiconductor thin-film body as compared with its length in the area of the semiconductor thin-film body away from the side wall, characterised in that the extra length of the current path adjacent to the sidewall is due at least in part to inclusion of an unmodulated drain-adjacent part of the channel region adjacent to the side wall, which drain-adjacent part is unmodulated by the gate electrode in operation of the transistor and spaces the drain electrode laterally away from the gate electrode at the area adjacent to the side wall.

2. A device as claimed in Claim 1, further characterised in that the part of the channel region modulated by the gate electrode is of substantially the same length adjacent to the side wall as in the area away from the side wall.

3. A device as claimed in Claim 1 or Claim 2, further characterised in that a convex-shaped edge of the drain electrode adjoins the unmodulated drain-adjacent part of the channel region adjacent to the side wall, which convex-shaped edge extends across the thickness of the semiconductor thin-film body.

4. A device as claimed in any one of the preceding claims, further characterised in that the extra length of the current path adjacent to the side wall is also due in part to inclusion of a source-adjacent part of the channel region adjacent to the side wall, which source-adjacent part is located laterally between the source electrode and the gate electrode and is unmodulated by the gate electrode in operation of the transistor.

5. A device as claimed in Claim 4, further characterised in that the unmodulated source-adjacent and drain-adjacent parts of the channel region adjacent to the side-wall are of similar geometry to each other.

6. A device as claimed in any one of the preceding claims, further characterised in that the length of the unmodulated drain-adjacent part of the channel region at the side-wall is at least one half of the length of the channel region in the area away from the side wall.

7. A device as claimed in any one of the preceding claims, further characterised in that the gate electrode extends laterally to the drain electrode at the area away from the side wall and so is capacitively coupled to the drain-adjacent part of the channel region in the area away from the side wall.

8. A device as claimed in any one of the preceding claims, further characterised in that the unmodulated drain-adjacent part of the channel region adjacent to the side-wall is of substantially intrinsic conductivity type.

9. A device as claimed in any one of Claim 1 to 7, further characterised in that the unmodulated drain-adjacent part of the channel region adjacent to the side-wall comprises a doping concentration of the first conductivity type, which doping concentration is lower than the doping concentration of a semiconductor region of the first conductivity type which provides the drain electrode.

10. An electronic device comprising thin-film field-effect transistors having any one of the novel features described herein and/or illustrated in the accompanying drawings.