GB2269505A - Intergrated-circuit image processing device - Google Patents

Abstract

An integrated-circuit image processing device comprises on the same substrate a two-dimensional array (50) of image-sensing cells (20), a memory (70) containing a plurality of storage sites (72) for storing a two-dimensional image field, and an interfacing means (60) for interfacing the contents of the array (50) to the memory (70). In a first embodiment the interfacing means (60) transfers the image sensed by the array (50) into the storage sites (72) of the memory (70), where they are held almost indefinitely and may be output onto video printer or video tape for a hard copy. In a second embodiment a first image is held in the memory (70) and a second image sensed by the array (22) is correlated in the interfacing means (60) with the first image and a signal dependent on the correlation is output (88) from the image processing device. The first image may itself have been originally sensed by the array (22) before the second image was sensed. <IMAGE>

Description

INTEGRATED-CIRCUIT IMAGE PROCESSING DEVICE The invention relates to an integrated-circuit image processing device and in particular an image processing device having a two-dimensional array of sensing cells.

Image processing devices comprising a two-dimensional array of sensing cells are well known and are based on one of two techniques: the charge coupling (CCD) technique and the diode array technique. Both of these techniques conventionally require that scanning, sensing and storage of a received image take place off the sensing chip, and this in turn means considerable expenditure in production costs and sacrifice in terms of space, even if something as basic as a simple camera is to be realised.

Recent developments in image array technology, however, have made possible the radical compression of the space needed to accommodate on a single substrate an image array together with its associated scanning and sensing circuitry, and it is this that forms the springboard for the present invention.

The aim of the invention is to provide an integrated-circuit image processing device which overcomes the above-mentioned drawbacks associated with the conventional techniques.

Accordingly, the invention provides an integrated-circuit image processing device, comprising on the same substrate a two-dimensional array of image-sensing cells for sensing a two-dimensional image field, a memory containing a plurality of storage sites for storing data representing a two-dimensional image field, and means for interfacing the contents of the image-sensing cells with the memory.

The means for interfacing the contents of the image-sensing cells with the memory may include a one-dimensional array of charge-sensing circuits, one circuit for each cell in a row of cells in the two-dimensional image array, the charge-sensing circuits sensing the charge induced in their associated cell by light incident upon the array and producing an output related to the sensed charge.

The means for interfacing the contents of the image-sensing cells with the memory may include means for transferring the outputs of the charge-sensing circuits to the storage sites of the memory.

The means for transferring the outputs of the charge-sensing circuits to the storage sites of the memory may include means for feeding said outputs in parallel into the storage sites on a row-by-row basis.

The means for transferring the outputs of the charge-sensing circuits to the storage sites of the memory may include means for feeding said outputs as a serial data stream representing each pixel in a row of the image array into a serial-parallel converter and feeding the outputs of the serial-parallel converter in parallel into the storage sites of the memory on a row-by-row basis.

The means for interfacing the contents of the image-sensing cells with the memory may include means for correlating a first image field stored in the memory with a second image field sensed by the array and means for outputting from the image processing device a result-of-correlation signal based on this correlation.

The means for interfacing the contents of the image-sensing cells with the memory may include means for transferring the outputs of the charge-sensing circuits into the storage sites and the first image field may be an image field which has, at one point in time, been sensed by the image array and transferred into the storage sites by the transferring means, while the second image field may be an image field which is subsequently sensed by the image array.

The means for transferring the outputs of the charge-sensing circuits into the storage sites may be a first serial-to-parallel converter.

The first image field stored in the memory may be programmed into the memory without the intervention of the image array.

The means for interfacing the contents of the image-sensing cells with the memory may include means for feeding in parallel the outputs of the charge-sensing circuits into one set of inputs of the correlating means, the first image field being output in parallel from the memory and fed to the other set of inputs of the correlating means, correlation thus taking place on a row-by-row basis.

The means for interfacing the contents of the image-sensing cells with the memory may include means for feeding the outputs of the charge-sensing circuits as a serial :data stream representing in turn each pixel in a row of the image array containing the second image field into a second serial-parallel converter and feeding in parallel the outputs of the second serial-parallel converter into one set of inputs of the correlating means, the first image field being output in parallel from the memory and fed to the other set of inputs of the correlating means, correlation thus taking place on a row-by- row basis.

The means for outputting a result-of-correlation signal from the image processing device may include processing means for receiving the output of the correlating means and outputting the result-of-correlation signal from the image processing device.

The processing means may receive an output signal from the correlator for each successive row of the first and second images and perform a mathematical function on the series of output signals received for the whole image field.

The mathematical function performed by the processing means may be an averaging function. The averaging function may be either a block average or a rolling average.

The first image stored in the memory may have the function of a personal identification, the result-of-correlation signal output from the image processing device being an indication of either authorised or unauthorised status.

The integrated circuit may be mounted on a card and the image array may sense an image field by means of a lens mounted on the card in close proximity to the diode array.

Data relating to the image field stored in the memory may be transferred in parallel on a row-by-row basis from the storage sites of the memory into the parallel inputs of a parallel-serial converter and then read out of the parallel-serial converter as a serial data stream.

The image array may be a diode image array.

Embodiments of the invention will now be described solely by way of example and with reference to the accompanying figures, in which: Figure 1 is a schematic diagram of an image array sensor utilising local preliminary charge sensing and common output charge sensing; Figure 2 is a schematic diagram of a diode sensing cell as shown in Figure 1; Figure 3 is a schematic diagram of a preliminary charge sensing stage used in the image array sensor; Figure 4 is a schematic diagram showing the general principle of operation of the image processing device according to the invention; Figure 5 is a schematic diagram of a first embodiment of the integrated-circuit image processing device according to the invention; Figure 6 is a schematic diagram of a second embodiment of the integrated-circuit image processing device according to the invention.

Referring now to the drawings, there is shown in Figure 1 an imaging arrangement 10 which consists of a matrix 22 of light-sensing cells 20, each of which takes the form of a light-sensitive diode 32 and a switching transistor 31, as shown in Figure 2. This matrix of diodes constitutes a pixel array and although this array has been shown in Figure 1 as consisting of only 9 pixels (3 x 3), it will in: practice comprise more like 300 x 300 pixels or, where broadcast-quality images are desired, even more (e.g.

500 x 500).

Light incident on the reverse-biased junction of each diode 32 causes a change in the diode's reverse leakage current and this in turn induces a change in charge on the diode's junction capacitance which serves to back off the applied reverse bias potential. When any particular row of pixels is addressed by the row select line 27 associated with that row, the transistors 31 associated with those pixels are switched on and the above-mentioned charge is passed on to the column select lines 25. The column select lines 25 then pass the charge on to the preliminary charge-sensing stages 40.

One of the preliminary charge-sensing sensing stages 40 is shown in more detail in Figure 3. It is based around an integrator 42 comprising an amplifier 41 and a feedback capacitor 44. When a particular row has been addressed by means of its row select line 27, light-induced charge on each column of that row is taken by column select line 25 to the integrator 42 for each row, where it is integrated across capacitor 44. Note that before this takes place charge on capacitor 44 from a previous integration is first nulled by operation of a switch 48. The resulting voltage appearing at the output of amplifier 41 is then taken by the closing of a switch 45 to a capacitor 46, where it is held until readout of this voltage to the common output chargesensing stage 24 via line 30 is initiated by the closing of a switch 47.The common output charge-sensing stage 24 is likewise realised as an integrator in exactly the same way as the preliminary sensing stages, so that the charge appearing on the capacitor 46 is transferred to an integrator capacitor in the common output stage 24, the resulting voltage on the output of this stage being then taken to further circuitry. In practice switches 48, 45 and 47 are realised by the use of analogue switching devices, e.g MOS transmission gates.

Signals on the column select lines 29 ensure that only one pixel in a row is processed at any one time by the charge-sensing integrators 42, 24. Thus Figure 3 shows a reset switch 49 (likewise for example a MOS transistor in practice) which normally keeps the inverting input of amplifier 41 at high (+Vdd) potential until the column in question is about to be scanned, at which point transfer of charge from the pixel diode concerned to the capacitor 44 via column select line 25 is enabled by the opening of this reset switch.

The invention extends the usefulness of this basic scheme by incorporating on the same substrate as the imaging arrangement 10 a memory and an interface stage which interfaces the imaging arrangement 10 with the memory, to form an image processing device.

The outline of this extended imaging arrangement is illustrated in Figure 4. Figure 4 shows a substrate 80 containing the basic imaging arrangement 10 of Figure 1 and also a memory 70 and an interface 60 connecting the memory 70 with the imaging arrangement 10. Image data may pass from the memory 70 to the interface 60 or from the interface 60 to the memory 70, the choice of direction being determined by the particular application envisaged.

The memory 70, which maybe powered by the same battery as the rest of the device, contains a number of storage sites 72, and there will normally be as many storage sites as there are pixels in the diode array 22. (The block 50 in Figure 4 represents the diode array 22 plus the preliminary charge-sensing stages 40 of Figure 1). The storage sites 72 may be addressed in rows and columns in the same way as the pixels 20 in the diode array 22, or, where parallel data transfer to/from the memory is preferred, the storage sites will beaddressed in rows only.

In the first embodiment of the invention, which is shown in Figure 5 (the substrate 80 is not shown in this and subsequent diagrams), the serial image data stream at the output of the common output charge-sensing stage 24 passes along line 26 to the serial input of a shift register 75 (see Figure 5a). At the start of a frame scan of the image field stored as diode charge in the pixels 20 the row select lines 27 are set to "row 1" and the column select lines 29 are set to column 1.The Read/Write input 73 on the memory 70 is set to "write" and the corresponding input on the shift register 75 is set to "read". Charge is now transferred from the first pixel of the first row (marked "1" in Figure 5) to the appropriate preliminary charge-sensing integrator 40 (not shown in Figure 5) and thence to the common output charge-sensing integrator 24.A voltage corresponding to that charge is converted into a digital code (this conversion is not shown in the drawings, but should be understood to take place), and this code then enters the shift register 75 via serial line (in practice a bus) 26 but is not allowed at this stage to be output along the data lines 74 to the memory 70. (Note that in practice the shift register 75 and the memory 70 will be several bits deep, depending on the resolution required for the imaging digital- code. For simplicity the shift registers and the memory illustrated throughout the specification are shown as being only one bit deep).

Scanning of the image field in the array 22 then passes to the second pixel (marked 2") of the array (i.e.

the column select lines are set to "column 2") and the image data pertaining to this pixel are sent along the serial output 26 to the shift register 75. This process is then repeated for all the remaining pixels in the first row of the diode array. When all the pixels in the first row have been scanned, a timing signal on line 76 commands the shift register 75 to pass the data in its stages in parallel on to the memory data inputs via data lines (buses) 74. Thus the image data for the first image line is read out of the shift register 75 and is written into the storage sites 72 of the memory 70. Timing signals are likewise supplied to the charge-sensing stages 40, 24 and to the memory 70 to synchronise the transfer of data.

Since the memory sites 72 will normally map directly onto the image sites 20, the address signals for the memory will normally be taken from the row select signals for the diode array. No column select signals are needed for the memory in a preferred method of addressing the memory, since the memory storage sites are loaded in parallel for each row.

When scanning of the first row has been achieved, the row select lines are set to "row 2" and the column select lines are set again to "column 1" and the above procedure is repeated for the second row of image data, and for each subsequent row until the whole image field has been scanned.

At the end of this process the image data that were originally found only in the diode array are located also in the memory 70, where they are held virtually indefinitely.

The image will be recoverable from the memory 70 for as long as the battery powering the integrated circuit holds its charge, and for as long also as the image data in the memory are not overwritten. (The memory 70 may be either battery-backed RAM or possibly EEPROM; in the latter case, even if the battery powering the IC fails, any image held in the memory will still be retrievable when power is restored).

Having read the image data into the memory 70, those same data may now be read out of the memory, and this is achieved as shown in Figure 5b.

To read out the image data from the memory 70, it is necessary to instruct the memory to switch to "read" and the shift register to switch to "write" (via the Read/Write line 73). Now clock signals on the "Timing" line 76 supervise the parallel transfer of data from the first line of memory 70 into the shift register 75 and the subsequent outputting of that data in serial form from the output 77 of the shift register 75. These serial data are then taken to circuitry or equipment located off the substrate.

What has been described above is a video chip that can record single images from an image array onto a memory that has as many storage sites as there are pixels in the image array. It is clearly also possible, however, to employ a memory having more storage sites than there are pixels in the image array, and where the total number of storage sites is an integer number times the number of pixels, a corresponding number of images can be stored in the memory.

All that is then required is a command to the row/column select lines to start the transfer of, say, a second image at a location 512 in the memory instead of at location 0, in the case of a 512 x 512 capacity memory.

Uses for this first embodiment of the invention are numerous. It can find applications in surgery, in view of its minute size (the chip itself is approximately 6mm square); in the sending of messages, in advertising, and so on. It can be carried around like a credit card with a fold-away lens element to focus the image onto the sensing array. And where "hard copy" of the stored image is required, this can be furnished by a video printer driven from the output serial data stream at output 77 of the shift register 75; alternatively, where distribution for simple viewing is required, this can be achieved by transferring the data onto video tape.

As previously mentioned, how long the stored image remains recoverable will, in the case of RAM used as the memory 70, depend on the capacity of the battery used to power the device. A small "credit card" sized battery would give a useful life of around two years at least.

A second embodiment of the invention is illustrated in Figure 6. In this embodiment an image stored in the memory 70 is compared or correlated with an image picked up by the sensing array 22 and a signal is sent off-chip to announce the result of the correlation.

Serial image data for each line of a sensed image is, as before, output from the output sensing stage 24 and taken to a shift register 75. However this time the parallel data outputs - 92 of the shift register, instead of being taken directly to the data inputs of the memory 70, are taken to one set of inputs of a correlator 85. The other set of inputs of the correlator 85 are fed by the data lines 74 from the memory 70. As before, line addressing of the image array and the memory takes place in tandem via the row select lines 27, while column addressing of the image array takes place via the column select lines 29.

The mode of operation of this embodiment is divided into two phases and is as follows: In the first phase an image selected by the user is presented to the diode array (for example by means of a lens such as was mentioned in connection with the first embodiment) and is registered by the array as charge pockets in the pixel cell sites 20. Transfer of these charge data into the memory 70 takes place as in the first embodiment by means of a shift register, in this case the further shift register 94. Serial image data from the charge-sensing circuit 24 enter the shift register 94 via a line 96 and are output in parallel along the data lines 74, when the "read"/"write" input 97 of the shift register 94 is set to "read" by an appropriate signal on line 73. The same signal sets the memory 70 to "write" and the image data are written into the- storage sites 72.The contents of the memory 70 will hereinafter be referred to as the "first image".

In the second phase the diode array is presented a second time with an image and this image will hereinafter be referred to as the "second image". At the start of the scanning of this second image, row 1 and column 1 of the array are pinpointed by the row/column select lines 27 and 29 and the image data for pixel 1, then pixel 2, pixel 3, etc, are transferred into the sensing integrators 40 (not shown in Figure 6) and 24 and from there into the shift register 75. At the same time the "read"/"write" line 73 is set to "read" (as far as the memory 70 is concerned) and the corresponding storage locations in memory 70 are addressed in parallel.As soon as the shift register 75 is full of the image data for the first line of the second image both these data and the data for the first line of the first image from the memory 70 are output along lines 92 and 74 respectively to the respective sets of inputs of a correlator 85. The two sets of data for the first line of each image are "correlated" or compared in the correlator 85 and the result of the correlation is taken to the input 86 of a processing stage 87. This process is repeated for all the remaining lines in the image field and for each line the result of the correlation is supplied to the processing stage 87. The processing stage 87 can be arranged to perform any suitable operation on the data supplied to it within each image frame to produce a final output on line 88 indicating whether or not sufficient correlation exists between the two images.The data supplied on the input 86 may, for example, be averaged by the processing stage at the end of each frame (i.e. a "block" average), or a rolling average may be made while the data is still coming in.

Whatever method is chosen, the final result available at the end of a frame may then be threshold-detected against a preset value to give the final "correlated"/"not correlated" (or "matched"/"not matched") indication to the user.

While correlation is taking place the shift register 94, having been set to "write", will be free to write the first image data on data lines 74 into its parallel inputs and then output them in serial form at an output 95 under the control of clocking signals derived from the timing control mentioned earlier.

Uses for the second embodiment are as numerous as those for the first. An obvious application is to increase the level of security provided by ID cards, security passes, bank cards and the like.

In a real-life situation where a bank card, for instance, was concerned, the procedure for obtaining one would be very simple. Blank cards would be readily available at a local bank, where a small terminal for "programming" the card would also be situated. The customer would simply have to insert the card containing the image processing device into a slot in the terminal, sit in front of a lens mounted in the terminal and communicating optically with the diode array in the recording device, and press a button. His image would then be imprinted in the on-card memory 70. As in the case of the first embodiment, the card would be equipped with a very small battery which both powered the electronics on the card and ensured an imprinted image life of at least two years.

The same terminal or other similar terminals dedicated for the purpose could be made available in all bank branches for receiving any customer's card in order to check his authority and effect clearance for a particular transaction.

An analogous procedure would apply to other uses of such a card; indeed, any situation where security clearance, identity checking and authorisation monitoring were required would greatly benefit from the use of the image processing device as realised in this second embodiment of the invention.

Yet another possible application of this second embodiment is its use in a lock. Conventional keys when they get lost allow the finder to have access to whatever the keys are designed to make inaccessible. A key designed after the manner of the second embodiment of the invention, however, might be imprinted as its "first image" with a likeness of the owner. Only the owner would then be able to effect opening of the lock by presenting his own likeness again to the card. A key realised in this manner would be uniquely defined not by a mechanical pattern of tongues designed to operate levers in a lock, but by the facial features, for example, of the key's owner.

In practice such a "key" would normally take the form of a card having a fold-away lens system as previously described and which was inserted by the owner into a slot in the door/door frame, etc. One half of the card would communicate with driver and pick-up electronics in the slot unit, while the other half would be free to register the owner's live image via the lens.

Of course, knowing what degree of correlation would be required in such a situation might be a problem, considering the practical circumstances that might exist, e.g. whether the owner on a particular day had shaved or not, whether his hair needed cutting, and so on. Perhaps a surer method might be to record as the "first image" something other than the owner's face, for example one of his fingerprints. In practice any kind of image could be used as the access pattern, though one advantage of using the owner's likeness is that, should the "key card" get lost, the owner could be identified by the readout of the first image from the card and the card subsequently returned to him. The finder of a card in these circumstances would still not be able to gain access to whatever the key protected, since his face would not sufficiently correlate with the owner's face imprinted in the memory.

Other uses for the "key card" described above are to limit access to personal computers and to protect car radios, videos, etc. Where such a piece of equipment were stolen, the thief would not be able to use it or sell it as useable without showing the owner's "first image" to the equipment.

While the second embodiment as decribed above has been shown as requiring a first phase, in which a "first image" is sensed by the diode array and stored in the memory, it is possible to dispense with this first phase and employ instead a read-only memory, such as an EEPROM, in which an image has already been programmed. Such an image could be custom-ordered or could perhaps be one of a large pool of readily available images for general use. In either event, the ready-programmed memory would only be available as part of a complete card and it would also of course be necessary for the owner of such a card to possess his own personal copy of the image in question in order to be able to gain access to whatever the card was intended to protect.

An advantage of this version of the second embodiment is that, since the first image would be already preprogrammed into the memory and the memory would be read-only, i.e. it could not be overwritten by subsequent image data, it would be impossible for a thief to imprint his own image onto the memory and to use that as a means of operating the card in the owner's lock, PC, video, etc.

Such an arrangement could find ready use in security establishments in place of the push-button combination lock type access systems that are normally used in such areas.

In this application the card containing the array and the ROM might alternatively be arranged to be resident in each access site instead of being carried about by personnel.

The personnel concerned would then gain access by presenting to the resident card their own card containing the same image as that imprinted on the resident card. In this situation the resident card could be looked upon as a "lock", while the cards carried about the person of those using the access could be viewed as a "key".

Although in both the first and second embodiments described above image data transfer from the image array has been assumed to take place in serial form, transfer could alternatively take place in parallel. In this situation the column select lines 29 would not be needed, but the common output stage 24 would have to be duplicated to match the number of pixels in a row of the array. However, a further advantage would be that the shift register 75 would be redundant, allowing direct transfer of the parallel data from the image array 22 to the memory 70 in the case of Figure 5 and to the correlator 85 in the case of Figure 6.

The shift registers mentioned in the description are only one form of serial-parallel or parallel-serial converter, and other forms may equally well be used.

Coupling of the various signals - e.g. the serial data output at output 77 or 95 and the "match"/"not-match" signal -at output 88 of the processing stage 87 - to or from the card can be achieved by already well established means (e.g. inductive coupling), so this is not further discussed in this specification.

While the two embodiments have been described in relation to the use of the diode array technique of image sensing, other sensing techniques, e.g. CCD, could also be used.

Claims (19)

1. An integrated-circuit image processing device, comprising on the same substrate: a two-dimensional array of image-sensing cells for sensing a two-dimensional image field; a memory containing a plurality of storage sites for storing data representing a two-dimensional image field, and means for interfacing the contents of the image-sensing cells with the memory.

2. An integrated-circuit image processing device, according to claim 1, in which the means for interfacing the contents of the image-sensing cells with the memory include a one-dimensional array of charge-sensing circuits, one circuit for each cell in a row of cells in the two-dimensional image array, the charge-sensing circuits sensing the charge induced in their associated cell by light incident upon the array and producing an output related to the sensed charge.

3; An integrated-circuit image processing device, according to claim 2, in which the means for interfacing the contents of the image-sensing cells with the memory include means for transferring the outputs of the charge-sensing circuits to the storage sites of the memory.

4. An integrated-circuit image processing device, according to claim 3, in which the means for transferring the outputs of the charge-sensing circuits to the storage sites of the memory include means for feeding said outputs in parallel into the storage sites on a row-by-row basis.

5. An integrated-circuit image processing device, according to claim 3, in which the means for transferring the outputs of the charge-sensing circuits to the storage sites of the memory include means for feeding said outputs as a serial data stream representing each pixel in a row of the image array into a serial-parallel converter and feeding the outputs of the serial-parallel converter in parallel into the storage sites of the memory on a row-by-row basis.

6. An integrated-circuit image processing device, according to claim 1 or 2, in which the means for interfacing the contents of the image-sensing cells with the memory include means for correlating a first image field stored in the memory with a second image field sensed by the array and means for outputting from the image processing device a result-of-correlation signal based on this correlation.

7. An integrated-circuit image processing device, according to claims 2 and 6, in which the means for interfacing the contents of the image-sensing cells with the memory include means for transferring the outputs of the charge-sensing circuits into said storage sites and in which the first image field is an image field which has, at one point in time, been sensed by the image array and transferred into the storage sites by the transferring means, while the second image field is an image field which is subsequently sensed by the image array.

8. An integrated-circuit image processing device, according to claim 7, in which the means for transferring the outputs of the charge-sensing circuits into the storage sites are a first serial-to-parallel converter.

9. An integrated-circuit image processing device, according to claim 6, in which the first image field stored in the memory is programmed into the memory without the intervention of the image array.

10. An integrated-circuit image processing device, according to any of claims 6 to 9, in which the means for interfacing the contents of the image-sensing cells with the memory include means for feeding in parallel the outputs of the charge-sensing circuits into one set of inputs of the correlating means, the first image field being output in parallel from the memory and fed to the other set of inputs of the correlating means, correlation thus taking place on a row-by-row basis.

11. An integrated-circuit image processing device, according to any of claims 6 to 9, in which the means for interfacing the contents of the image-sensing cells with the memory include means for feeding the outputs of the charge-sensing circuits as a serial data stream representing in turn each pixel in a row of the image array containing the second image field into a second serial-parallel converter and feeding in parallel the outputs of the second serial-parallel converter into one set of inputs of the correlating means, the first image field being output in parallel from the memory and fed to the other set of inputs of the correlating means, correlation thus taking place on a row-by-row basis.

12. An integrated-circuit image processing device, according to any of claims 6 to 11, in which the means for outputting a result-of-correlation signal from the image processing device includes processing means for receiving the output of the correlating means and outputting the result-of- correlation signal from the image processing device.

13. An integrated-circuit image processing device, according to claim 12, in which the processing means receives an output signal from the correlator for each successive row of the first and second images and performs a mathematical function on the series of output signals received for the whole image field.

14. An integrated-circuit image processing device, according to claim 13, in which the mathematical function performed by the processing means is an averaging function.

15. An integrated-circuit image processing device, according to claim 14, in which the averaging function is a block average.

16. An integrated-circuit image processing device, according to claim 14, in which the averaging function is a rolling average.

17. An integrated-circuit image processing device, according to any of claims 6 to 16, in which the first image stored in the memory has the function of a personal identification, the result-of-correlation signal output from the image processing device being an indication of either authorised or unauthorised status.

18. An integrated-circuit image processing device, according to any of the preceding claims, in which the integrated circuit is mounted on a card and in which the image array senses an image field by means of a lens mounted on the card in close proximity to the diode array.

19. An integrated-circuit image processing device substantially as shown in or as hereinbefore described with reference to Figures 4 to 6 of the drawings.

19. An integrated-circuit image processing device, according to any of the preceding claims, in which data relating to the image field stored in the memory may be transferred in parallel on a row-by-row basis from the storage sites of the memory into the parallel inputs of a parallel-serial converter and then read out of the parallel-serial converter as a serial data stream.

20. An integrated-circuit image processing device, according to any of the preceding claims, in which the image array is a diode image array.

21. An integrated-circuit image processing device substantially as shown in or as hereinbefore described with reference to Figures 4 to 6 of the drawings.

Amendments to the claims have been filed as follows

1. An integrated-circuit image processing device, comprising on the same substrate: a two-dimensional array of image-sensing cells for sensing a two-dimensional image field; a one-dimensional array of charge-sensing circuits, one circuit for each cell in a row of cells in the two-dimensional image array, the charge-sensing circuits sensing the charge induced in their associated cell by light incident upon the array and producing an output related to the sensed charge; a memory containing a plurality of storage sites for storing data representing a two-dimensional image field, and means for interfacing the outputs of the charge-sensing circuits with the storage sites of the memory.

2. An integrated-circuit image processing device, according to claim 1, in which the means for interfacing the outputs of the charge-sensing circuits with the storage sites of the memory include means for feeding said outputs in parallel into the storage sites on a row-by-row basis.

3. An integrated-circuit image processing device, according to claim 1, in which the means for interfacing the outputs of the charge-sensing circuits with the storage sites of the memory include means for feeding said outputs as a serial data stream representing each pixel in a row of the image array into a serial-parallel converter and feeding the outputs of the serial-parallel converter in parallel into the storage sites of the memory on a row-by-row basis.

4. An integrated-circuit image processing device, according to claim 1, in which the means for interfacing the outputs of the charge-sensing circuits with the storage sites of the memory include means for correlating a first image field stored in the memory with a second image field sensed by the array and means for outputting from the image processing device a result-of-correlation signal based on this correlation.

5. An integrated-circuit image processing device, according to claim 4, in which the means for interfacing the outputs of the charge-sensing circuits with the storage sites of the memory include means for transferring the outputs of the charge-sensing circuits into said storage sites and in which the first image field is an image field which has, at one point in time, been sensed by the image array and transferred into the storage sites by the transferring means, while the second image field is an image field which is subsequently sensed by the image array.

6. An integrated-circuit image processing device, according to claim 5, in which the means for transferring the outputs of the charge-sensing circuits into the storage sites are a serial-to-parallel converter.

7. An integrated-circuit image processing device, according to. claim 4, in which the first image field stored in the memory is programmed into the memory without the intervention of the image array.

8. An integrated-circuit image processing device, according to any of claims 4 to 7, in which the means for interfacing the outputs of the charge-sensing circuits with the storage sites of the memory include means for feeding in parallel the outputs of the charge-sensing circuits into one set of inputs of the correlating means, the first image field being output in parallel from the memory and fed to the other set of inputs of the correlating means, correlation thus taking place on a row-by-row basis.

9. An integrated-circuit image processing device, according to any of claims 4 to 7, in which the means for interfacing the outputs of the charge-sensing circuits with the storage sites of the memory include means for feeding the outputs of the charge-sensing circuits as a serial data stream representing in turn each pixel in a row of the image array containing the second image field into a serial-parallel converter and feeding in parallel the outputs of the serial-parallel converter into one set of inputs of the correlating means, the first image field being output in parallel from the memory and fed to the other set of inputs of the correlating means, correlation thus taking place on a row-by-row basis.

10. An integrated-circuit image processing device, according to any of claims 4 to 9, in which the means for outputting a result-of-correlation signal from the image processing device includes processing means for receiving the output of the correlating means and outputting the result-of- correlation signal from the image processing device.

11. - An integrated-circuit image processing device, according to claim 10, in which the processing means receives an output signal from the correlator for each successive row of the first and second images and performs a mathematical function on the series of output signals received for the whole image field.

12. An integrated-circuit image processing device, according to claim 11, in which the mathematical function performed by the processing means is an averaging function.

13. An integrated-circuit image processing device, according to claim 12, in which the averaging function is a block average.

14. An integrated-circuit image processing device, according to claim 12, in which the averaging function is a rolling average.

15. An integrated-circuit image processing device, according to any of claims 4 to 14, in which the first image stored in the memory has the function of a personal identification, the result-of-correlation signal output from the image processing device being an indication of either authorised or unauthorised status.

16. An integrated-circuit image processing device, according to any of the preceding claims, in which the integrated circuit is mounted on a card and in which the image array senses an image field by means of a lens mounted on the card in close proximity to the diode array.

17. An integrated-circuit image processing device, according to any of the preceding claims, in which data relating to the image field stored in the memory may be transferred in parallel on a row-by-row basis from the storage sites of the memory into the parallel inputs of a parallel-serial converter and then read out of the parallel-serial converter as a serial data stream.

18. An integrated-circuit image processing device, according to any of the preceding claims, in which the image array is a diode image array.