GB2267767A - On-board (or in-situ) programming of microprocessor memories. - Google Patents
On-board (or in-situ) programming of microprocessor memories. Download PDFInfo
- Publication number
- GB2267767A GB2267767A GB9311990A GB9311990A GB2267767A GB 2267767 A GB2267767 A GB 2267767A GB 9311990 A GB9311990 A GB 9311990A GB 9311990 A GB9311990 A GB 9311990A GB 2267767 A GB2267767 A GB 2267767A
- Authority
- GB
- United Kingdom
- Prior art keywords
- programming
- bscan
- microprocessor
- data
- interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims abstract description 21
- 238000011065 in-situ storage Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000012360 testing method Methods 0.000 claims abstract description 9
- 230000009471 action Effects 0.000 claims abstract description 3
- 238000012546 transfer Methods 0.000 claims description 12
- 230000004913 activation Effects 0.000 claims description 7
- 230000000977 initiatory effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000036316 preload Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/24—Loading of the microprogram
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
A method for programming a microprocessor with a memory means, installed on a circuit card. The method uses an interface such as the Boundary Scan/Joint Test Action Group (BSCAN/JTAG) standard between the programming unit and the microprocessor memory means. The programming may be performed using commands defined by the user. <IMAGE>
Description
A Microprocessor Installed on a Circuit Card
The present invention relates to a microprocessor installed on a circuit card and a method of programming the microprocessor.
Before the storage circuits are installed on a circuit card they are generally preprogrammed for the particular application. Handling of the storage circuits often causes short circuits between the pins during preprogramming. The pins of the microcircuits may also bend slightly during handling thus causing centering problems during installation.
If the program of the microprocessor is changed, the storage circuit needs to be removed from the circuit card and replaced.
A Boundary Scan/Joint Test Action Group (BSCAN/JTAG) interface is standardized and it may be used in any digital microcircuit. The ease of testing of the microcircuit cards can be improved using BSCAN/JTAG testing equipment. Circuits including BSCAN/JTAG logic circuits can be coupled to each other in several ways on the circuit card, as long as it is done according to a standard. The IEEE 1149.1 standard defines some mandatory test commands that it must be possible to implement with the aid of the BSCAN/JTAG interface. In addition to these commands, the user can define special commands for his/her own purposes.
According to a first aspect of the present invention there is provided a microprocessor installed on a circuit card, comprising an interface coupled between the programming unit and the microprocessor memory means, wherein a microcircuit including an interface is coupled to the address and data bus of the microprocessor memory means so that the programming of the microprocessor maybe realized by an interface command.
According to a second aspect of the present invention there is provided a method of programming a microprocessor installed on a circuit card, wherein the method comprises the steps of: - initiating the programming, - formatting the CHIP, - transferring the programming command and the byte address in the
BSCAN chain, - selection of the storage circuit and activation of writing into the storage, - transfer of the address and the data to the BSCAN chain, - transfer of the read command of the state register in the BSCAN chain, - scanning the command which has been read, - reading and clocking the state register, - error checking, and - transfering of the read command of the table in the BSCAN chain.
An advantage of the present invention is the provision of a microprocessor and a method which enables the programming of the microprocessor installed on a a method which enables the programming of the microprocessor circuit card using an interface, and which solves the above problems.
An embodiment of the present invention will be described herewith, by way of example, with reference to the accompanying drawings in which:
Fig. 1 represents a block diagram of a microprocessor in accordance with the invention; and
Fig. 2 represents a flow diagram of an example of the programming of the microprocessor in accordance with the invention.
The method in accordance with to the invention uses an interface, which may adhere to the BSCAN/JTAG standard (IEEE 1149.1), between the programming unit and the microprocessor memory means. A link with the address and data bus of the microprocessor memory means is achieved with the aid of a microcircuit which is connected to the address and data bus. This type of microcircuit should include a BSCAN/JTAG testing logic whereby the contact to the memory means is achieved through the BSCAN/JTAG control and data inputs of the microcircuit connected to the bus. This microcircuit may be a microprocessor or any microcircuit connected to the bus in which the
BSCAN/JTAG logic has been implemented. The control signals between the programming unit and the program storage can be coupled directly or using the
BSCAN/JTAG interface. The supply voltage required by the programming can be supplied from the programming unit or the circuit card.
The programming of the program storage of the microprocessor is realized using a command defined by the user whereby the BSCAN/JTAG logic of the microcircuit(s) coupled to the storage contacts the address and data bus of the program storage, In addition, the control signals may be realized with the aid of the BSCAN/JTAG interface as well. The control signals can also be supplied directly to the memory means.
The bits required in the programming can be separated in the BSCAN register with the aid of the programming commands defined by the user. Consequently, the address and data bus and the control signals required by the programming can be supplied through the BSCAN/JTAG interface as arranged in a reduced
BSCAN data register. In this way, the time used for programming can be decreased because only the necessary bits of the BSCAN data register are scanned.
The programming data is fed to the microcircuit through the BSCAN/JTAG data input and the verification data of the program is read from the
BSCAN/JTAG data output. The BSCAN/JTAG interface is first set into a programming state by scanning in the programming command defined by the user which sets the microcircuit(s) feeding data to the program storage into a special state. This state arranges the BSCAN data register in the abovedescribed way. Exiting the programming state is carried out by returning the microcircuit to the initial state or by using the Reset command.
In some cases the programming may be realized without a special command defined by the user. Since the BSCAN units inside the logic microcircuit are coupled to all the inputs and outputs, the programming can be realized by using commands according to the standard. However, this causes a decrease in the performance of the programming unit. The greatest disadvantage is the increase in the time used for programming and scanning. When commands according to the standard are used, the whole BSCAN data register operates during the programming.
With the aid of the method in accordance with the invention, any kind of memory means can be programmed as long as the microcircuit employed by the
BSCAN/JTAG interface is capable of meeting the programming requirements set by the equipment to be programmed. In the following, the programming, scanning, and verification of the programming of a Flash type EPROM memory is described.
The BSCAN registration units are coupled as swapping registers around the microcircuit. A respective registration unit is reserved for each input and output pin. The print-out signals and the I/O control signals have respective registration units as well. These registration units of the swapping register can be arranged in an optional sequence. A BSCAN programming command has been developed for the programming activities which remains valid once it has been loaded, until the whole microcircuit is returned to the initial state or the
Test Logic Reset command is activated.
The BSCAN register is divided into parts with the aid of the BSCAN programming command. By dividing the BSCAN register chain into two parts the programming procedures are substantially speeded up because the number of the factors of the swapping register chain is decreased. The part of the
BSCAN register which is used in the programming state can be, for instance, the address bus, the data bus and the other signals. The division can be realized in such a way that those BSCAN register units which are not used in the programming state are isolated from the initial BSCAN register chain, the isolation meaning that the units in question are deleted from the BSCAN register chain and the transmission of the control signals to them is prevented.
The BSCAN register units included in the programming of the storage form a new arranged BSCAN register chain in which a TDI input is coupled to the first unit and the last unit is coupled to a TDO output. The new BSCAN chain with its TDI input and TDO output can now be formed in a better way for the programming procedures.
Fig. 1 shows a block diagram of the solution according to the invention. The
BSCAN system comprises control unit 1, command register 2, decoder 3, block 4 of the BSCAN registers required in the programming of the storage, block 5 of the other BSCAN registers and multiplexers 6 to 8, flipflop 9 and bypass block 10.
An FSM control unit with 16 states, according to IEEE 1149.1, can be used as control unit 1, for instance. Command register 2 is the long command register defined by the user. Mandatory or optional command operations can be formed with the aid of decoder 3. The data register comprises BSCAN registers 4 required in the programming of the memory means and other BSCAN registers 5. Bypass 10 is a one-bit bypass register. Control unit 1 is coupled to command register 2 and multiplexers 6 to 8 which control the travel of the data out of the system.
An advantage of the programming method according to the invention is that sensitive memory circuits can be installed on the circuit card without having to preprogram them. This avoids the occurance of short circuits between the pins caused by the handling of the memory circuits during preprogramming as well as centering problems during installation.
By using multiple-write memory circuits, the program of the microprocessor is easy to change without having to replace the storage circuits. The
BSCAN/JTAG interface is standardized and it can be used in any digital microprocessor. By using the BSCAN/JTAG testing equipment for programming, it is sometimes possible to avoid the need to develop special programming hardware.
The command register supports mandatory commands (E)CIBST, SAMPLE/PRELOAD and Bypass) and the commands defined by the user.
Loading of the program commands does not interfere with the use of the mandatory commands. However, the loading of the new commands does not effect the isolated part of the BSCAN chain. If the transmission of the control signals of the isolated part is not prevented, the loading of the new commands of the programming state effects the units in question, but the results of the isolated part cannot be scanned out of the TDO output.
Fig. 2 shows a flow diagram of an example of the programming of the microprocessor in accordance with the invention. CHIP is formatted 12 in the
Flash programming state after initiating 11 the programming. This is followed by the transfer of the programming command and the byte address in BSCAN chain 13. Selection of the memory circuit and activation of the writing into the memory means is realized in three separate blocks 14, 16 and 18. The transfer of the address and the data to BSCAN chain 15 and the transfer of the read command of the state register in BSCAN chain 17 is realized in between. The command read after this is scanned 19, the state register is read and clocked 20. Next, error check 21 notices possible programming errors 22. If the address has increased by one, the procedure is continued in the address verification block 23, otherwise, a return to block 14 is performed. The transfer of the read command of the table in the BSCAN chain is realized in block 24 after which the storage circuit is selected again and the writing into the storage is activated 25 and the program is terminated 26.
The reference numerals in Figures 1 and 2 refers to the following features;
Fig. 1 1 Control Unit 2 Command Register 3 Decoder 4 The BSCAN registers to the programming of the storage 5 The other BSCAN registers 6 Multiplexer 7 " 8 II 9 FF 10 Bypass
Fig. 2 11 Initiating the programming 12 Formatting the CHIP 13 Transfer of the programming command and the byte address in the
BSCAN chain 14 Selection of the storage circuit and activation of the writing into
the storage 15 Transfer of the address and the data into the BSCAN chain 16 Selection of the storage circuit and activation of the writing into
the storage 17 Transfer of the read command of the state register in the BSCAN
chain 18 Selection of the storage circuit and activation of the writing into
the storage 19 Scanning the command which has been read 20 Reading and clocking the state register 70 Clocking cycles 21 Error checking Error 22 Programming Error
No 23 Address = previous address + 1 No
Yes 24 Transfer of the read command of the table in the BSCAN chain 25 Selection of the storage circuit and activation of the writing into
the storage 30 Clocking cycles 26 Termination of programming
In view of the foregoing it will be clear to a person skilled in the art that modifications may be incorporated without departing from the scope of the present invention.
Claims (16)
1. A microprocessor installed on a circuit card, comprising an interface coupled between the programming unit and the microprocessor memory means, wherein a microcircuit including an interface is coupled to the address and data bus of the microprocessor memory means so that the programming of the microprocessor maybe realized by an interface command.
2. A microprocessor as claimed in claim 1, wherein the interface is a
Boundary Scan/Joint Test Action Group (BSCAB/JTAG) interface.
3. A microprocessor as claimed in claim 1 or claim 2, wherein several microcircuits are coupled to the address and data bus of the memory means.
4. A microprocessor as claimed in claim 2 or claim 3, wherein the control signals are realized through the BSCAN/JTAG interface.
5. A microprocessor as claimed in any previous claim, wherein the control signals are supplied directly to the memory means.
6. A microprocessor as claimed in any previous claim, wherein the programming unit supplies the supply voltage required by the programming is supplied from the programming.
7. A microprocessor as claimed in any of claims 1 to 5, wherein the circuit card supplies the supply voltage required by the programming.
8. A method of programming a microprocessor installed on a circuit card, wherein the method comprises the steps of: - initiating the programming - formatting the CHIP, - transferring the programming command and the byte address in the
BSCAN chain, - selection of the storage circuit and activation of writing into the storage, - transfer of the address and the data to the BSCAN chain, - transfer of the read command of the state register in the BSCAN chain, - scanning the command which has been read, - reading and clocking the state register, - error checking , and - transfering of the read command of the table in the BSCAN chain.
9. A method as claimed in claim 8, wherein the programming data is supplied to the microcircuit through the BSCAN/JTAG data input and the check data of the program is read from the BSCAN/JTAG data output.
10. A method as claimed in claim 8 or claim 9, wherein the
BSCAN/JTAG interface is first set into the programming state by scanning in programming commands defined by the user which set the microcircuit(s) feeding data to the program storage into a special state and through which the bits required in the programming are separated in the BSCAN register and the address and data bus, and the control signals required in the programming are supplied through the BSCAN/JTAG interface as arranged in a reduced BSCAN data register.
11. A method as claimed in claim 10, wherein the exit from the programming state is effected by returning the microcircuit to the initial state.
12. A method as claimed in claim 10, wherein the exit from the programming state is effected using the Reset-command.
13. A method as claimed in any of claims 8 to 11, wherein the programming is realized without commands defined by the user.
14. A method as claimed in any of claims 8 to 11, wherein the programming is defined with commands defined by the user.
15. A microprocessor as described herein with reference to Figures 1 and 2 of the accompanying drawings.
16. A method of programming a microprocessor as described herein with reference to Figures 1 and 2 of the accompanying drawings.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI922707A FI93999C (en) | 1992-06-11 | 1992-06-11 | Programming a short-mounted microprocessor's program memory |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9311990D0 GB9311990D0 (en) | 1993-07-28 |
GB2267767A true GB2267767A (en) | 1993-12-15 |
GB2267767B GB2267767B (en) | 1996-10-02 |
Family
ID=8535467
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9311990A Expired - Fee Related GB2267767B (en) | 1992-06-11 | 1993-06-10 | A microprocessor installed on a circuit card |
Country Status (2)
Country | Link |
---|---|
FI (1) | FI93999C (en) |
GB (1) | GB2267767B (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0672910A1 (en) * | 1994-03-17 | 1995-09-20 | Fujitsu Limited | System testing device and method using JTAG circuit |
GB2315583A (en) * | 1996-07-18 | 1998-02-04 | Altera Corp | Configuration memory |
US5869979A (en) * | 1996-04-05 | 1999-02-09 | Altera Corporation | Technique for preconditioning I/Os during reconfiguration |
GB2346473A (en) * | 1996-07-18 | 2000-08-09 | Altera Corp | Configuration memory |
EP2357567A3 (en) * | 2009-12-16 | 2012-07-18 | Giesecke & Devrient GmbH | Method for programming an electronic device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4751633A (en) * | 1984-03-20 | 1988-06-14 | Robert Bosch Gmbh | Externally reprogrammable vehicular microcomputer with hardware lock-out of unauthorized memory modifications |
EP0275510A2 (en) * | 1987-01-20 | 1988-07-27 | International Business Machines Corporation | Smart card having external programming capability and method of making same |
GB2204973A (en) * | 1987-05-19 | 1988-11-23 | Gen Electric Co Plc | Data processing system |
GB2248127A (en) * | 1990-09-04 | 1992-03-25 | Mitsubishi Electric Corp | Data erasing and re-writing circuit for use in programming a microcomputer integrated circuit device |
GB2256734A (en) * | 1991-06-14 | 1992-12-16 | Nokia Mobile Phones Ltd | Modifying program code. |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5355369A (en) * | 1991-04-26 | 1994-10-11 | At&T Bell Laboratories | High-speed integrated circuit testing with JTAG |
-
1992
- 1992-06-11 FI FI922707A patent/FI93999C/en not_active IP Right Cessation
-
1993
- 1993-06-10 GB GB9311990A patent/GB2267767B/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4751633A (en) * | 1984-03-20 | 1988-06-14 | Robert Bosch Gmbh | Externally reprogrammable vehicular microcomputer with hardware lock-out of unauthorized memory modifications |
EP0275510A2 (en) * | 1987-01-20 | 1988-07-27 | International Business Machines Corporation | Smart card having external programming capability and method of making same |
GB2204973A (en) * | 1987-05-19 | 1988-11-23 | Gen Electric Co Plc | Data processing system |
GB2248127A (en) * | 1990-09-04 | 1992-03-25 | Mitsubishi Electric Corp | Data erasing and re-writing circuit for use in programming a microcomputer integrated circuit device |
GB2256734A (en) * | 1991-06-14 | 1992-12-16 | Nokia Mobile Phones Ltd | Modifying program code. |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5781560A (en) * | 1994-03-17 | 1998-07-14 | Fujitsu Limited | System testing device and method using JTAG circuit for testing high-package density printed circuit boards |
EP0672910A1 (en) * | 1994-03-17 | 1995-09-20 | Fujitsu Limited | System testing device and method using JTAG circuit |
US6208162B1 (en) | 1996-04-05 | 2001-03-27 | Altera Corporation | Technique for preconditioning I/Os during reconfiguration |
US5869979A (en) * | 1996-04-05 | 1999-02-09 | Altera Corporation | Technique for preconditioning I/Os during reconfiguration |
US6031391A (en) * | 1996-07-18 | 2000-02-29 | Altera Corporation | Configuration memory integrated circuit |
GB2315583B (en) * | 1996-07-18 | 2000-07-05 | Altera Corp | Configuration memory |
US6097211A (en) * | 1996-07-18 | 2000-08-01 | Altera Corporation | Configuration memory integrated circuit |
GB2346473A (en) * | 1996-07-18 | 2000-08-09 | Altera Corp | Configuration memory |
GB2346473B (en) * | 1996-07-18 | 2000-12-27 | Altera Corp | Configuration memory |
GB2315583A (en) * | 1996-07-18 | 1998-02-04 | Altera Corp | Configuration memory |
US6259271B1 (en) | 1996-07-18 | 2001-07-10 | Altera Corporation | Configuration memory integrated circuit |
US6614259B2 (en) | 1996-07-18 | 2003-09-02 | Altera Corporation | Configuration memory integrated circuit |
EP2357567A3 (en) * | 2009-12-16 | 2012-07-18 | Giesecke & Devrient GmbH | Method for programming an electronic device |
Also Published As
Publication number | Publication date |
---|---|
FI93999B (en) | 1995-03-15 |
GB2267767B (en) | 1996-10-02 |
FI93999C (en) | 1995-06-26 |
FI922707L (en) | 1993-12-12 |
GB9311990D0 (en) | 1993-07-28 |
FI922707A0 (en) | 1992-06-11 |
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Legal Events
Date | Code | Title | Description |
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732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) |
Free format text: REGISTERED BETWEEN 20100819 AND 20100825 |
|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20110610 |