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GB2263253A - Ceramic on metal circuit board - Google Patents

Ceramic on metal circuit board Download PDF

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Publication number
GB2263253A
GB2263253A GB9226220A GB9226220A GB2263253A GB 2263253 A GB2263253 A GB 2263253A GB 9226220 A GB9226220 A GB 9226220A GB 9226220 A GB9226220 A GB 9226220A GB 2263253 A GB2263253 A GB 2263253A
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United Kingdom
Prior art keywords
ceramic
glass
composition
circuit board
weight
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Granted
Application number
GB9226220A
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GB9226220D0 (en
GB2263253B (en
Inventor
Satyam Choudary Cherukuri
Lubomyr Stephen Onyshkevych
Ashok Narayan Prabhu
Barry Jay Thaler
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General Electric Co
Original Assignee
General Electric Co
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Priority claimed from US07/809,372 external-priority patent/US5277724A/en
Priority claimed from US07/809,371 external-priority patent/US5256469A/en
Application filed by General Electric Co filed Critical General Electric Co
Publication of GB9226220D0 publication Critical patent/GB9226220D0/en
Publication of GB2263253A publication Critical patent/GB2263253A/en
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Publication of GB2263253B publication Critical patent/GB2263253B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C10/00—Devitrified glass ceramics, i.e. glass ceramics having a crystalline phase dispersed in a glassy phase and constituting at least 50% by weight of the total composition
    • C03C10/0054—Devitrified glass ceramics, i.e. glass ceramics having a crystalline phase dispersed in a glassy phase and constituting at least 50% by weight of the total composition containing PbO, SnO2, B2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Dispersion Chemistry (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Geochemistry & Mineralogy (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Ceramic Products (AREA)
  • Glass Compositions (AREA)

Description

1 1 1 CERAMIC-ON-METAL CIRCUIT BOARD 2263253 As known in the art,,
multi-layered, co-fired, ceramic circuit boards are fabricated from a stack of layers of ceramic dielectric tape sold under the trademark, GREEN TAPE,, by the E. I. Du Pont company of Wilmington, Del. Each layer of the ceramic tape has a thickness of about five mils (0. 13mm). The surface of each layer may have metallic conductors printed thereon that can be electrically interconnected by means of small holes (knows as vias) in one or more of the layers. The holes are filled with a conductive material. Such a co-fired, ceramic circuit board is described in U.S. Patent No. 5,041,695 issued on Aug. 20, 1991 to J. A. Olenick.
Two types of co-fired, ceramic circuit boards are available. These are: (i) high temperature fire (typically below 13000C) and (ii) low temperature fire (typically below 10000C). The high temperature, co-fire technology is used for alumina and aluminum n#ride ceramics, whereas the low temperature, co-fire technology is used for glass ceramics (ceramic filler filled vitreous glasses or devitrifying glasses). The conductor metallurgy for high timperature, co-fired boards is W or Mo-Mn,, whereas low temperature,, co-fired circuit boards utilize Ag, Au, AgPd or Cu conductors.
Shrinkage in volume,experienced by the ceramic bodies after firing,is a problem encountered in the fabrication of multi-layered, co-fired, ceramic circuit boards. This shrinkage, which occurs in the x and y surface dimensions as well as in the z thickness dimension of the respective layers, results from the release, during firing, of the air distributed between the particles as well as the organic binder material in the green tape. Such shrinkage is quite high, typically 10-15% for low 1 1 3 0 temperature, co-fired circuit boards. While one can attempt to compensate for such shrinkage in the x and y surface dimensions by oversizing the area of the green tape layers, it is quite difficult to control shrinkage consistently. For example, in order that the variation in the x and y dimensions of the multi-layered circuit board, after firing, be maintained within 0.1%, a degree of control that may be as large as one to two parts in one hundred in the amount of shrinkage is required. Because of this, the yield on co-fired circuit boards is low. In addition, the low temperature, co-fired circuit boards suffer from poor thermal conductivity and low flexure strengths associated with the glass ceramic.
A single layer of ceramic fired on a metal base, such as porcelain enamelon-steel, is known in the art. Because the temperature coefficient of expansion exhibited by the steel, which comprises such a base, is relatively large, the composition of the ceramic layer fired on the steel base also must exhibit a relatively large temperature coefficient of expansion, in order to closely match that of the base. High barium, highexpansion glass-ceramics have been developed which may be used to fabricate such porcelain enamel-on-steel board;. While other ceramic composition systems are known that exhibit a relatively large temperature coefficient of expansion, high-expansion in these systems is typically achieved by the addition of heavy metal oxides,such as, lead, barium, or alkali, e.g., sodium and potassium. However, this results in higher dielectric constants and higher dielectric losses, and may lead to poor chemical durability, which makes such high-expansion systems poor candidates for use in fabricating multi-layered, co-fired, ceramic circuit boards that may be employed in microelectronic packaging.
1 1 is The present invention is directed broadly to a multi-layered, co-fired ceramic on a metal base and, more particularly, to a system of low temperature, co-fired, high-expansion glass ceramics that, when finetuned with certain fillers. exhibit dielectric constants and dielectric losses that are sufficiently low to make them suitable for use in the fabrication of multi-layered, co-fired ceramic-on-metal circuit boards suitable for microelectronic packaging. The invention is further directed to a method of fabricating such circuit board utilizing a glass bonding layer to securely attach the ceramic to the metal base.
In the drawings:
Fig. 1 diagrammatically illustrates an example of a microelectronics package fabricated in accordance with the present invention.
Fig. 2 is a flow chart of the process steps involved in the present invention.
BRIEF DESCRIETION OF THE PREFERRED EMBODIMENTS The fabrication process, embodied in Fig. 1, generally comprises forming a metal base 12 having two oppositely disposed major surfaces 14 and 16, for example,by stamping a metal core (not shown) and then annealing the core at a temperature of about 500 to 9000C to provide dimensional stability. The surfaces of the core are cleaned to remove dirt and oxide. Preferably, at least one of the major surfaces 14 and 16 is plated with a suitable material, such as Cu, to a thickness of about 0.5 to 25.0 microns. Suitable materials for the base 12 include Cu, Al, Ni, stainless steel, low carbon steel, Cu/Invar/Cu, Cu/Mo/Cu or Cu/stainless steel/Cu, the latter being preferred.
A bonding layer 18, of a glass having a coefficient of thermal expansion less than that of the base 12, is applied, as a slurry, to one major surface, for example,surface 14, of the base 12. The slurry can be - 3 1 applied by screen printing, spraying, spin coating, curtain coating, fluidized-bed coating, electrophoretic deposition or other equivalent methods. Circuit boards made according to the present invention utilized screen printing and spraying methods. A multi-layered ceramic 20 is provided on the glass bonding layer 18.
The multi-layered ceramic 20 may be formed by applying multiple layers of green tape to the glass bonding layer. or the laminated ceramic structure may be bisque fired prior to being placed on the glass bonding layer 18. For a Cu/stainless steel/Cu base, the resultant structure is co-fired in nitrogen (about 10,000 PPM 02) at a peak temperature of about 900-9300C for about 2 to 20 minutes to bond the ceramic 20 to the surface 14 of the base 12. The intermediate glass bonding layer 18 serves two functions; it provides a means of attaching the multi-layered ceramic 20 to the base 12, and it minimizes the shrinkage of the ceramic 20 in the x and y dimensions during the firing. The glass bonding layer 18, in addition to having a coefficient of expansion less than that of the metal base 12, must be sufficiently reactive with the copper plating and the copper oxides on the surface 14 of the base 12 to promote and maintain adhesion between the ceramic 20 and the base during the co-firing operation. The glass of the bonding layer 18 must have a relatively low softening point (<600OC) so that it can flow and bond to the surface 14 of the metal base 12, and possess appropriate surface tension characteristics at temperatures below the softening point of the glass in the ceramic layer 20 to minimize the lateral (x and y) shrinkage of the ceramic. Additionally, the glass of the bonding layer 18 also must possess good chemical durability and dielectric properties.
The composition of the glass bonding layer 18 is influenced by the composition of the metal core and its thermal characteristics, as well as the composition of the 1 1 is ceramic larainate, the sintering characteristics and the process employed for fabricating the cofired, ceramic-on-metal circuit board. Each layer of the multi-layered ceramic 20 comprises a glass-ceramic/filler composition having a coefficient of thermal expansion that closely matches that of the base 12 and the glass bonding layer 18. over the temperature range from room temperature to about 6000C. A number of glass compositions from the multi-component system PbO-ZW-MO-B203-Si02 are suitable for the glass bonding layer 18. 'These glass compositions may also contain small amounts of Zr02 and A1203. Some of the generalized compositions and their typical properties are listed in Table I.
TABLE I
Glass System Thermal Coefficient Softening of Exp. (10-7)/OC Point (OC) Ph-borate 75-120 280-430 Pb-Zn-borate 70-110 320-450 Pb-borosilicate 40-2.20 370-700 Pb-Zn-borosilicate 75-80 370-700 Pb-Zn-Ba-borolsilicate 75-100 380-400 Pb-alumino silicate 60-85 440-485 Pb-alumino borosilicate 80-90 390-440 Ceramic-on-metal circuit boards have been made according to the present invention using glasses selected from the Pb-Zn-borosilicate and Pb-Zn-Ba- borosilicate glass systems listed in TABLE 1. The preferred glass, from the Pb-Zn-Ba-borosilicate system, is a commercially available glass identified as SCC-11, available from SEM-CON Co. (Toledo, OH). Another suitable glass from this same system is commercially available as CV-808 from Owens Illinois (Toledo, OH). This latter glass contains a small amount of Zr02. A suitable glass from the Pb-Zn-borosilicate system is CV- 101, also commercially available from Owens Illinois.
1 1 is These bonding glasses have been successful in providing good adhesion of the laminated ceramic to a Cu/stainless steel/Cu base 12. Furthermore, the x-y shrinkage of the laminated ceramic layer 20 is decreased by more than an order of magnitude, to about 0.8%,by using these glasses. The x-y shrinkage of the ceramic laminate is typically 12-15% in the absence of the glass bonding layer 18. In addition, the metal base 12 exhibits good thermal conductivity and high flexure strength, thereby overcoming the problems of poor thermal conductivity and low flexure strength suffered by prior-art circuit boards comprising only multi-layers of low temperature, co-fired, glass ceramic.
The conductor metallurgy can be Ag, Au, AuPt, AgPd, Ni, or Cu. Nitrogen or any other inert atmosphere may also be required to fire precious metal conductor co-fired circuit boards to prevent oxidation of the metal base. Appropriate slots can be provided in the laminated tape for integratedcircuit chips to be placed directly on the metal base using adhesive, solder attachment, or other direct bonding method to provide very ef f icient heat spreading. High density circuitry can be produced on the cofired ceramic using photolithography for top layer conductors. It is also possible to spin-on additional polymer layers on the co-fired ceramic and then use thin film-plating techniques to form very high density circuitry.
The co-fired circuit board on metal base technology disclosed herein, in addition to producing high density circuit boards with excellent thermal dissipation and shrinkage control characteristics, helps to obtain a mechanically rugged base. Also, the integrated circuit chips and other components can be attached directly on the metal by providing slots either in the green tape, as shown in Fig.1 and discussed below, or on the opposite surface of the metal base from the multi-layered ceramic. Components can be 1 1 1.
attached by soldering, wire bonding, TAB, flip-chip or adhesive attach. The packages can be hermetic (glass-sealing on metal) or non-hermetic with appropriate encapsulation for component protection.
While it is not intended to limit the multi-layered, co-:ired ceramic-onmetal technology of the present invention to any particular application. its suitability for microelectronic packaging depends on the fired multilayered ceramic exhibiting appropriate electrical properties, in addition to having other appropriate properties for this purpose. In this regard, reference is made to the following Table II, which is an example of electrical and other property value constraints required of the fired multi-layered ceramic in one practical case of microelectronic packaging.
TABLE 11
Property Coef. of Thermal Expansion (25-250OC) Dielectric Constant (1 MHz) Dissipation Factor (1 MHz) Breakdown Voltage Specific (Volume) Resistivity Resistivity of buried conductor Resistivity of via conductor Resistivity of surface conductor Camber Desired Value 90-130X10-7 / oc <6.6 <0.0035 >2 kV/mm >1012 g em <lo m2/square <50 mn/square <50 mR/square <0.00511/inch Long term reliability (HHBT conditions) no shorts In Table II, HHBT conditions, with respect to long term reliability, refers to an accelerated aging test, in which a microelectronic packaging sample, under high humidity and high temperature conditions, withstands a given voltage stress for a given time without electrical breakdown.
The application of the multi-layered, co-fired, ceramic-on-metal technology of the present invention to microelectronic packaging required the development of glass-ceramic (GC) compositions capable of being used in 1 glass-ceramic+filler (GC/F) compositions that meet the constraints set forth above in Table II.
In the past, glass, glass-ceramic, and glass+filler systems have been developed and successfully employed in microelectronics packaging for high density packaging applications. The major advantage of these materials over the conventional ceramics such as alumina is the lower firing temperature, which enables the use of higher electrically conductive Ag, Cu, Au, and AG-Pd as compatible metallizations. There was a proliferation of glass-ceramic and glass+filler systems during these developments; however, emphasis was laid on matching thermal expansion to silicon and in some cases to Ga-As. Thermal expansion coefficients typically ranged from 30-70X10-7/oC. The issues related to controlling dielectric constant, dielectric loss, strength, bulk and surface resistivities, electrical breakdown strength, chemical durability, shrinkage during firing, and compatibility with metallization were addressed in a broad range of borate, boro-silicate, and silicate glass and glass-ceramic systems containing low or intermediate expansion fillers such as alumina, cordierite, forsterite, eucryptite, etc. However, none of these glass, glass-ceramic, and glass+filler systems substantially exhibits the property-value constraints set forth in Table Il. In particular,the expansion coefficient of these prior-art composition systems is too low to be successfully employed in the fabrication of multi-layered, co-fired, ceramic-on-metal, high density circuit boards.
It is one of the objects of the present invention to (1) identify a glassceramic system, and specific glass-ceramic compositions within this system, with suitable thermal, electrical, chemical, and mechanical properties that make them likely candidates for use in fabricating a multi-layered, co-fired, ceramic-on-metal, high density circuit board, and (2) then incorporate appropriate fillers in such likely GC candidates to fine-tune the composite GCIF to substantially meet the property value constraints set forth in Table II.
1 1.
1 is In this regard, Table III, set forth below, is directed to an MgO-B203- S'02 systemcontaining CaO, ZnO, and Sn02 as additives,that was chosen-for the development of likely glass-ceramic (GC) candidates for use in fabricating a multi-layered, co-fired, cerimic-on-metal, high density circuit board. No alkaline oxides are deliberately added to the glasses, but they may be present as impurities in the raw materials. Zr02 was incorporated in all compositions as a nucleating agent for controlled crystallization. The compositions of the different glasses that were prepared and evaluated are shown in Table III. Glass-ceramics were produced by heat-treating the glasses at 850-9500C for 10-30 minutes. The thermal expansion coefficient of the resultant glass-ceramics ranged from 85 to 105X10-7 / Oc over a temperature range from room temperature (RmT) to about 6000C (as specifically exemplified below in Table III by the thermal expansion coefficient of each of glass-ceramics GC-1 to GC-7), which is appropriate for further tailoring by incorporation of fillers. Sensitivity to moisture was evaluated by exposing the glass-ceramics to steam at 15 psi for twelve hours. All the compositions showed no clear evidence of deterioration in moisture.
l.' __11 1 TABLE 111
Candidate Glass-Ceramic Compositions in the MgO-B203-SiO2 System (Weight %) a X 10-7 / OC Mgo ZnO CaO Sn02 BaO Zr02 Cr203 RmT-6000C id. S102 B203 GC-1 17 28 45 8.5 GC-2 17.8 31.0 48.6 - GC-3 16.4 28.5 43.2 9.5 - GC-4 17.5 29.5 43 - 4 GC-5 14.5 25.2 34.7 5.6 4.8 GC-6 14.3 24.8 34.2 - 6.7 GC-7 16.9 30.0 39.1 9.1 3.7 GC-8 15.9 28.3 41.2 9.23 4.2 GC-9 17.5 31.8 43.0 - 6.53 GC-10 16.7 30.4 29.9 - 21.9 GC-11 16.1 28.5 25.1 8.7 20.5 GC-12 16.8 29.8 38.8 9.1 3.6 GC-13 15.8 28.0 34.4 8.5 3.4 GC-14 16.6 30.0 31.8 8.4 3.4 1,.1 1.5 92 2.6.97 1 2.4 105 2.0 86 0 13.0 2.1 84 17.9 2.1 186 1.2 as 1.2 1.2 1.1 1.1 0.9 J.0 8.0 0.4 1.5 7.9 0.4 1.5 1 is Based on the compositions of the glass ceramics GC-1 through GC-14, the following composition ranges (by weight percent) are identified to be suitable for expansion matched glass-ceramics co-fired on CU/ptainless steel/Cu metal cores:
S'02 B203 Mgo ZnO CaO Sn02 BaO 10-20% 20-35% 25-50 0-10% 0-22% 0-18% 0-10% It may be possible to incorporate other oxides, including alkali and heavy metal oxides, in small quantities with minor effect on dielectric constant and dielectric loss. Other nucleating agents such as Ti02 and P205 also may be used instead of Zr02. For example, up to 5% by weight (individual or combined) of these nucleating agents can be included. For obtaining suitable color, up to 3 by weight (individual or combined) of Cr203, Coo, F6203. Cuo, Ce02. and/or Pr203 may be incorporated. Further, the glass-ceramic may include, as other additives, up to 10% by weight (individual or combined),Li20, Na20. K20. A1203f Pbor Bi203, and/or Sro.
Three fillers were chosen as candidates for tailoring the glass-ceramic properties. They are Fluorspar (CaF2), Quartz (Si02), and Cristobalite (S102). The thermal expansion coefficients of Fluorspar, Quartze and Cristobalite in the range of 20 to 6000C are 225, 237. and 271X10-7/OC respectively. Several glassceramic/tiller (GC/F) combinations were processed by standard tape casting procedures. One or more of these fillers, up to 50% by volume, were considered for altering the expansion and dielectric constant of the base glass-ceramics (GC). By varying the 1 amount of filler in the glass-ceramic/filler system, the expansion coefficient of the glass-ceramic/filler (GC/F) systems can be increased up to 130X10-7 / oc.
Five novel glass-ceramic/filler materials (GCIF-1 to GC/F-5) having properties suitable for use in fabricating multi-layered, co-fired, ceramic circuit boards are shown below in Table IV. Of these five glassceramic/filler materials, GC/F-4 and GC/F-5 were found to have the best overall properties for this purpose.
TABLE IV
GC/F-1 GC/F-2 GC/P-3 is Composition 70 GC-7 + 75 GC-8 + 70 GC-9 + (Weight 15 Fluorspar + 25 Fluorspar 15 Quartz + Quartz 15 Fluorspar Expansion Coefficient 116 106 110 (10-7 /0c) (Rm.T.-600OC) Dielectric 6.4 5.6 6.5 Constant (@ 10 KHz) Dissipation 0.2.% 0.2% 0.2% Factor (@ 10 KHZ) GC/F-4 M/F-5 composition 70 GC-12 + 70 GC-13 + (Weight %) 15 Fluorspar + 15 Fluorspar + Quartz 15 Quartz Expansion Coefficient 115-120 120-125 (10-7/OC) (RM. T. -600OC) 1 1.
1 Dielectric 6.2-6.6 6.3-6.9 Constant (@ 1 MHz) Dissipation Factor (@ 10 KHz) 0.1% 0.3% (@ 1 MHz) 0.3% 0.5% Peak Firing 930-935 910-920 Temp. (OC) Moisture Good Good Resistance is HHBT (600Cr9ORH,48V) Pass Volume Resistivity >1012 ncm Pass >1012 ncm A combined weight of up to 50% of the fillers Quartz, Fluorspar and/or Cristobalite can be incorporated for further elevation of the thermal expansion coefficient and improvement of the shrinkage behavior.
An example of microelectronic packaging of a multichip module is shown in Fig. 1. The co-fired cera?nic-on-metal structure 10 comprises the metal base 1 2 having first and second major surfaces 14 and 16 with the cofired, multi-layered ceramic 20 bonded to the first major surface 14 by the glass bonding layer 18. Each layer of the laminated glassceramic/filler tape, prior to firing, may be provided with suitable holes or vias, which, after firing, provide slots 22 in the co-fired, multilayered, ceramic 20, thereby permitting integrated-circuit chips 24 (or other components) to be 1 is attached directly to the metal base 12. An encapsulant 26, covering each of the chips 24, may then be hermetically sealed to the metal base 12. ' The chips 24 are electrically attached, e.g., by wire bonding 28 or similar means, as is known in the art. Alternatively, each of the chips 24 may be protected by a non-hermetic sealed encapsulant 26.
A heat sink 30 is attached to the opposite major surface 16 of the base 12 by an adhesive 32. Further, the microelectronic packaging includes support structure 34 for mounting the multichip module in a device (not shown).
Although not shown in Fig. 1, co-fired, multi-layered ceramic 20 incorporates metallic conductors which currently comprise Ag and Ag/Pd. However, metallic conductors comprising Cu or Au should also be compatible with co-fired, multi-layered, ceramic-on-metal boards of the type disclosed herein.
While the new glass-ceramic (GC) materials shown in Table III and, particularly, the glass-ceramic/filler materials shown in Table IV were developed for use in the microelectronic packaging of a ceramic-on-metal multichip module of the type shown in Fig. 1, these new materials also should be useful for other standard multi-layer ceramic packages, with or without the incorporation of a metal-base.
The novel process, shown in Fig. 2, involves applying the glass bonding layer 18 by, for example, spray coating, to one major surface,, for example, surface 14, of the base 12. A layer of SCC-11 glass that had been made into a slurry, by mixing it with about 60 to 90 volume % of a suitable solvent, such as 2-propanol, acetone, ethanol or terpinol, 2propanol being preferred, is used. The laminated ceramic layer 20 may be formed separately by stacking multi-layers of selectively metalized glapsceramic/filler tape having vias formed therein, and bisque firing the laminated structure to remove the organics therefrom to form a - 14 1 1 1 1 is monolithic ceramic. Alternatively, the ceramic layer 20 may be formed by applying multiple layers of metalized and via punched glassceramic/filler tape to the glass bonding layer 18. In the preferred method, the glass bonding layer 18 is heated to a temperature of about 4500C to pre-flow the glass of the bonding layer to form a thin glass cover having a thickness of about 0.025=m (0.001 inch) on the surface 14. Then, the previously formed ceramic layer 20 is positioned on the glass bonding layer leand the entire structure is co-fired in nitrogen (about 10,000 PPM 02) at a temperature of 900-9300C for about 2 to 20 minutes. The peak firing temperatures selected for co-firing depend upon the metal of the base 12 and the composition of the ceramic layer 20. The adhesion of the ceramic layer 20 to the base 12, resulting from the utilization of the glass bonding layer 18, significantly minimizes the x-y shrinkage of the ceramic layer during co-firing, and the shrinkage in volume of the ceramic is mostly confined to the z thickness dimension.

Claims (33)

1. A co-fired, multi-layered, ceramic-onmetal circuit board comprising a structure having a metal base, a bonding layer of glass on said base, and a ceramic formed from multiple layers of a ceramic tape on said bonding layer, each layer of said multiple layers of ceramic tape comprising a glassceramic/filler composition.
2. The circuit board defined in Claim 1, wherein:
each of said metal and said glassceramic/filler composition exhibits a temperature coefficient of expansion that closely matches one another over a temperature range from room temperature to about 6000C.
3. -The circuit board defined in Claim 1 or Claim 2 wherein said glass-ceramic/filler composition exhibits:
a temperature coefficient of expansion in the range of 90-130x10-7/OC; a dielectric constant of less than 6.9 at MHz; and a dissipation factor of not greater than 0.5% at 1 MHz.
4. The circuit board defined jp any preceding claim, wherein:
said glass-ceramic of said glassceramic/filler composition consists of a selected glass-ceramic of a MgO-B203-SiO2 system of glassceramics.
- 16
5. The circuit board defined in -any preceding claim, wherein: said glass-ceramic/filler composition, by weight,,consists of at least 50% glass-ceramic composition and a filler composition of no greater than 50%, and said filler composition comprises at least one of Quartz, Fluorspar or Cristobalite.
6. The circuit board defined in Claim 5, wherein: said glass-ceramic/filler composition, by weight, consists of substantially 70% of a given glass-ceramic composition and substantially 30% of a given filler composition; said given glass-ceramic composition, by weight, consists of substantially 16.9% Si02, 30.0% B203f 39.2% MgO, 9.1% ZnO, 3.7% CaO, and 1.2% Zr02; and said given filler composition, by weight, consists of substantially 50% Fluorspar and 50% Quartz.
7. The circuit board defined in Claim 5.
wherein: said glass-ceramicIfiller composition, by weight, consists.of substantially 75% of a given glass-ceramic composition and substantially 25% of a given filler composition; said given glass-ceramic composition, by weight, consists of substantially 15.9% Si02, 28.3% B203, 41.2% MgO, 9.23% ZnO, 4.2% CaO, and 1.2% Zr02; and said given filler composition, by weight, consists of substantially 100% Fluorspar.
1
8. The circuit board defined in Claim 5, wherein: said glass-ceramic/filler composition, by weight,_consists of substantially 70% of a given glass-ceramic composition and substantially 30% of a given filler composition; said given glass-ceramic composition, by weight, consists of substantially 17.5% Si02, 31.8% B203, 43.0% MgO, 6.53% CaO, and 1.2% Zr02; and said given filler composition, by weight, consists of substantially 50% Fluorspar and 50% Quartz.
wherein:
9. The circuit board defined in Claim 5, said glass-ceramicIfiller composition, by weight, consists of substantially 70% of a given glass-ceramic composition and substantially 30% of a given filler composition; said given glass-ceramic composition, by weight, consists of substantially 16.8% Si02, 29.8% B203, 38.8% M90, 9.1% ZnO, 3.6% CaO, 0.9% Zr02, and 1.0% Cr203; and said given filler composition, by weight, consists of substantially 50% Fluorspar and 50% Quartz.
10. The circuit board defined in Claim 5, wherein: said glass-ceramic/filler composition, by weight, consists of substantially 70% of a given glass-ceramic composition and substantially 30% of a given filler composition; said glass-ceramic composition, by weight, consists of substantially 15.8% Si02r 28.0% B203o, 34.4% MgO, 8. 5% ZnO, 3.4% CaO, 8.0% BaO, 0.4% Zr02. and 1.5% Cr203; and said given filler composition, by weight, consists of substantially 50% Fluorspar and 50% Quartz.
11. The circuit board defined in any preceding claims, wherein: said metal consists of one of Cu, Al, stainless steel, Ni, low carbon steel, Cu/Invar/Cu, CuMo/Cu, and Cu/stainless steel/Cu.
12. The circuit board defined in any preceding claim, wherein: at least one of the layers of said co- fired, multi-layered ceramic includes printed conductors thereon comprising at least one of Ag, Au, AuPt, Ag/Pd, Ni, and Cu.
13. The circuit board defined in any preceding claims, wherein: said multi-layered ceramic incorporates at least one slot extending therethrough to the metal underlying said slot.
14. The circuit board defined in Claim 13, further comprising: a microelectronic component extending into 3 0 said slot and attached directly to said underlying metal.
15. The circuit board defined in Claim 14, wherein: said microelectronic component comprises an integrated-circuit chip.
16. The circuit board defined in Claim 14, further comprising:
- an encapsulant covering said microelectronic component and said slot, said encapsulant being attached to said multilayered ceramic.
wherein:
17. The circuit board defined in Claim 16, said microelectronic component is hermetically sealed by said covering encapsulant.
18. A composition comprising a selected glass-ceramic of a M90-B203-SiO2 system of glass- ceramics suitable for use in the fabrication of a cofired, multi-layered, ceramic circuit board; wherein: said selected glass-ceramic by itself exhibits a temperature coefficient of expansion in the range of 85-105x,0- 7/oC over a temperature range from room temperature to about 6000C.
19. The composition defined in Claim 18, 2 5 wherein:
said selected glass-ceramic of said MgO- B203-SiO2 system comprises at least one of ZnO, CaO, BaO and Sn02 as an additive.
20. The composition defined in Claim 18-or Claim 19, wherein:
said selected glass-ceramic of said MgO B203-SiO2 system comprises, by weight, 10-20% Si02P 20-35% B203, 25-50% M90, 0-10% ZnO, 0-22% CaO, 0-18% Sn02, and 0-10% BaO.
21. The composition defined in Claim 20, wherein:
- 20 1 is the composition of said selected glassceramic of said MgO-B203-SiO2 system includes a nucleating agent for controlled crystallization of said corpposition, said nucleating agent comprising up to 5%, by weight, of Zr02, T'02 Or 1205, alone or in any combination thereof.
22. The composition defined in Claim 20, wherein:
the composition of said selected glass ceramic of said MgO-B203-SiO2 system includes up to 3%, by weight, Of Cr2031 COO, Fe2031 CuO, Ce02 Or Pr203, alone or in any combination thereof for obtaining a suitable color for said composition.
23. The composition defined in Claim 20, wherein:
the composition of said selected glass- ceramic of said MgO-B203-SiO2 system includes as an additive up to 10%, by weight, of Li20, Na20, K20. Or A1203, PhOr Bi203f or SrO alone or in any combination thereof.
24. The composition defined in any One Of 2 5 Claims 18 to 23, wherein:
said composition further comprises a filler having a temperature coefficient of expansion sufficiently high to increase the temperature coefficient of expansion of said composition from said 3 0 value in the range of 85-105x10-7/oC of said selected glass-ceramic by itself to a value in the range of 90-130x10-7/oC over a temperature range from room temperature to about 6000C.
25. The composition defined in Claim 24, wherein said composition exhibits: a dielectric constant of less than 6.9 at 1 MHz; and a dissipation factor of not greater than 0.5% at 1 MHz.
26.
Claim 25, wherein:
The composition defined in Claim 24 or said composition comprises up to 50%, by weight, of said filler; and said filler comprises at least one of Quartz, Fluorspar or Cristobalite.
27. A method of making a co-fired, ceramic-on-metal circuit board comprising a multilayered ceramic on a metal base, said metal base having oppositely disposed major surfaces, said method including the steps of depositing a glass bonding layer on one of said major surfaces of said metal base, said glass bonding layer having a coefficient of thermal expansion not greater than that of said base, providing said multilayered ceramic on said glass bonding layer, and heating said base, said glass bonding layer and said multi-layered ceramic to a temperature sufficient to securely attach said ceramic to said base.
28- The method as described in claim 27, wherein said glass bonding layer is heated to a 3 0 temperature of about 4500C, to pre-flow the glass of the bonding layer, prior to providing said multilayered ceramic thereon.
29. The method as described in claim 27, wherein said heating step is carried out at a temperature of about 9000C.
30. The method as described in claim 29, wherein said heating step is carried out in a ni trogen atmosphere.
31. A method of minimizing lateral shrinkage in a co-fired, ceramic-on-metal circuit board comprising a multi-layered ceramic on a metal.base, said metal base having oppositely disposed major surfaces, said method including the steps of depositing a glass bonding layer on one of said major surfaces of said metal base. said glass bonding layer having a coefficient of thermal expansion not greater than that of said base.
providing said multi-layered ceramic on said glass bonding layer, each layer of said multi-layered ceramic comprising a glass-ceramic/filler composition having a coefficient of thermal expansion that closely matches that of said base and said glass bonding layer.over a temperature range from room temperature to about 6000C, and co-firing said base, said glass bonding layer and said multi-layered ceramic to an elevated temperature sufficient to securely attach said ceramic to said base, said glass bonding layer having a softening point below that of said ceramic so that said glass of said bonding layer flows and bonds to the metal while minimizing the lateral shrinkage of said ceramic.
32. The method as described in claim 31, wherein said glass bonding layer is heated to a temperature of about 4500C to pre-flow said glass of said glass bonding layer, prior to providing said multilayered ceramic thereon.
1
33. The method as described in claim 31, wherein said co-firing step is carried out at a temperature of about 9000 to 9300C for about 2 to 20 minutes, in a nitrogen atmosphere.
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6233817B1 (en) * 1999-01-17 2001-05-22 Delphi Technologies, Inc. Method of forming thick-film hybrid circuit on a metal circuit board
KR100382416B1 (en) * 1999-09-28 2003-05-01 가부시끼가이샤 도시바 Ceramics circuit board
KR100696861B1 (en) * 1999-12-10 2007-03-19 고등기술연구원연구조합 Metallic Low Temperature Cofired Ceramic Substrate Manufacturing Method
KR100696859B1 (en) * 1999-12-10 2007-03-19 고등기술연구원연구조합 Metallic Low Temperature Cofired Ceramic Substrate Manufacturing Method
DE10148751A1 (en) * 2001-10-02 2003-04-17 Siemens Ag Production of an electronic unit comprises applying a conductor strip system as low melting system on a thin low sinterable flexible ceramic foil, sintering, applying a thin connecting material layer, and further processing
US20100089620A1 (en) * 2006-11-30 2010-04-15 Richard Matz Electronic Component Module and Method for the Production Thereof
CN102822112B (en) 2010-03-30 2014-06-18 株式会社村田制作所 Metal base substrate and manufacturing method thereof
JP6285271B2 (en) * 2014-04-24 2018-02-28 株式会社ノリタケカンパニーリミテド Bonding material and its use
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4291107A (en) * 1979-04-19 1981-09-22 Chloride Silent Power Limited Glass seals for sealing beta-alumina in electro-chemical cells or other energy conversion devices, glasses for use in such seals and cells or other energy conversion devices with such seals

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3954486A (en) * 1974-07-30 1976-05-04 Owens-Illinois, Inc. Solder glass with refractory filler
US4185139A (en) * 1977-12-30 1980-01-22 International Standard Electric Corporation Filler for a glass-ceramic material comprising CaF2 granules overcoated with a silicon dioxide film
US4256796A (en) * 1979-11-05 1981-03-17 Rca Corporation Partially devitrified porcelain composition and articles prepared with same
JPS5911700A (en) * 1982-07-12 1984-01-21 株式会社日立製作所 Ceramic multilayer circuit board
US5047371A (en) * 1988-09-02 1991-09-10 Olin Corporation Glass/ceramic sealing system
US5041695A (en) * 1989-06-01 1991-08-20 Westinghouse Electric Corp. Co-fired ceramic package for a power circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4291107A (en) * 1979-04-19 1981-09-22 Chloride Silent Power Limited Glass seals for sealing beta-alumina in electro-chemical cells or other energy conversion devices, glasses for use in such seals and cells or other energy conversion devices with such seals

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