GB2253277A - Testing programmable logic devices - Google Patents

Abstract

To test a programmable logic device (15), a decoder device (10) is attached (11) to the PLD; each PLD terminal is sequentially tested as in Fig 2 to determine whether it is an input or an output; and all possible input combination are sequentially applied (13) to each input. For each combination the condition of each output is determined (13), and the conditions of the output are processed (14) to determine the function of the output. In Figure 2 the resistors (16) are chosen so that input pins of PLD (15) change state when an input is switched from low to high whereas output pins do not change state when the same switched input is applied thereto. <IMAGE>

Description

PROGRAMMABLE LOGIC DEVICE DECODER The present invention relates to Programmable Logic Device (PLD) Decoders for use in testing programmed PLDs.

Conventionally, circuit designers construct circuits from a plurality of standardised chips each of which contain a plurality of items many of which, in the completed circuit, are redundant. This inevitably results in unnecessary expense and complications. However the characteristics of components constructed in this way are known to all, and can be held in a component tester's library, and facilities are usually available for testing such components.

Recently devices known as Programmable Logic Devices (PLD) have appeared on the market. These devices contain a large number of items and are intended to enable a circuit designer to create his own customised logic circuits on one component. Normally all possible connections between items on a PLD are made. The device is programmed by the designer according to a computer programme which blows all redundant connections, thereby creating a customised circuit.

Normally the software verifies the completed device by checking internal connections. However this verification does not guarantee that the device is functioning as the device may well include faulty elements which are not identified. The characteristics of a customised circuit will be unique and therefore unknown to current component testers. There is an inadequacy in that PLDs cannot be tested after programming.

Furthermore PLDs all look the same, but, once programmed, will function differently. A user must therefore label his devices for identification purposes. When a label is lost the PLD programming software (if still available) can be used to establish the nature of the internal connections, but even with this information specialist knowledge and a great deal of time is necessary to establish the function of the circuit.

A further complication is that PLDs frequently have a security bit which is normally blown once the device has been programmed, after which not even the state of the internal connections can be read.

There is therefore a need for a device for testing programmed PLDs.

According to the present invention a PLD decoder includes means for attachment to a PLD, means for sequentially testing each PLD terminal to determine whether the terminal is an input or an output, means for sequentially applying all possible input combinations to the inputs and, for each combination, determining the condition of each output, and means for processing the conditions in order to determine the function of the output. All input combinations will normally be applied for each output in turn.

The decoder preferably includes a test socket, ideally a zero insertion force variant, capable of accepting devices having a plurality of pins, and means whereby the decoder can be informed of the number of pins on the device so that power supplies can be automatically routed to the correct pins.

Preferably the decoder also contains a versatile interface to the test socket, and a first computer (Z80-based for example) with interconnection by which the decoder can be connected to act in partnership with a second, host computer which has a visual display.

The test programme can be controlled with the aid of a mouse driven menu which offers the facilities to modify the component test conditions, select#specific outputs, manipulate results and load differing device sizes.

According to another aspect of the invention a method of testing a programmed PLD includes the steps of connecting the device to a PLD decoder, sequentially testing each terminal of the device to determine whether it is an input or an output, sequentially applying all possible input combinations to the inputs and, for each combination, determining the condition at the outputs, and processing the conditions to determine the full function of the PLD.

Some embodiments of the invention will now be described, by way of example only, with reference to the accompanying diagramatic drawings, of which: Figure 1 is an elevation of a decoder according to the invention in association with a second computer, Figure 2 is a circuit diagram indicating the method of determining input and output terminals, Figure 3 is a diagram indicating a method of passing information from the decoder to the second computer, and Figure 4 is a diagram of a logic circuit associated with the method of figure 3.

A decoder 10 according to the invention (Figure 1) contains a test socket 11, a Versatile Interface 12 and a first computer 13 which might be, for example, a Z80. The test socket 11 is preferably a zero insertion force variant capable of accepting programmable logic devices of sizes up to, for example, 40 pins.

In use the decoder 10 is connected to a second computer 14 which might be, for example, a IBM XT/AT computer, and a programmed PLD which it is desired to test, 15, is plugged into the test socket 11. The size of the device 15 (for example, 20 pin device, 24 pin device etc.) is declared to the decoder 10 and the test sequence is initiated.

In test sequence the program stored within the first computer 13 systematically applies to each terminal of the device 15 a sequence of high and low (for example, plus 5 volts and zero volts) voltages through resistors 16 (Figure 2). The resistors 16 are of such a size that whichever voltage is supplied to an output pin insufficient current flows to change the state of the pin. By contrast when a pin is an input the pin will be high when connected to the high voltage and low when connected to the low voltage.

A diagram of the device with input and output pins labelled is displayed on a screen of the second computer 14. A user of the decoder is guided by a simple mouse driven menu which offers the facilities to modify the component test conditions by, for example, placing certain input pins to 5 volts or zero volts before testing occurs. The user then clicks the mouse over the output pin(s) of interest and executes the analysis of the component.

The decoder 10 then presents every possible input condition to the device 15 and monitors each response of each output. The first computer 13 applies the input conditions and transfers the response of the output for each, as it gets them, to the second computer 14 for processing. When all input conditions have been applied, the second computer produces a transfer function for each output which is presented in sum of products boolean algebra. A minimisation process such as, for example, the Sharp Product System is used to produce the boolean function.

Knowing the function which the device 15 is intended to perform a user of the decoder 10 will immediately recognise from the transfer functions of the output whether or not the device 15 is functioning correctly.

The tasks of the computers 13, 14 will be such that each will be heavily loaded with tasks at differing times to each other. In a preferred method of passing data from the first computer 13 to the second computer 14, a pseudo ring 20 (Figure 3) of data slots 21 is used. The first computer 13 places data on one element 21 and moves along the ring without hesitation. The second processor 14 follows behind picking off the data at its own pace. Progression of the computers 13, 14 is programmed so that neither can overtake the other. This allows the first computer 13 to proceed with compiling more data when the second computer 14 is temporarily too busy to accept data. Furthermore, it allows the second computer 14 to process piled up data when the first computer 13 has temporarily stopped issuing data. The ring 20 resides in volatile memory, accessible to both computers 13, 14.

A problem with this system is that the second computer 14, which is the master computer must instruct the first computer 13 to leave the circuit when it requires access to the ring 20. Thus a situation may be reached where the second computer 14 is persistantly disturbing the first computer 13 whilst waiting for data, thereby preventing the first computer from computing the data.

To prevent this an external counter circuit (Figure 4) is used.

This circuit allows the second computer 14 to check for waiting data on the ring 20 without accessing the ring 20.

According to this circuit whenever the first computer 13 places data on the ring 20 the counter is incremented, and whenever the second computer 14 takes data off the counter is decremented. The counter always displays the relative position between the two computers 13, 14. When the counter shows zero the second computer 14 must wait, whilst if the counter is showing full displacement then the first computer 13 must wait. When the first computer 13 clocks the counter to the maximum state (that is when information is contained on each element 21) the counter suspends the first computer 13 from operating until the second computer 14 removes information.

Claims (12)

1. What is claimed is: 1. A Programmable Logic Device (PLD) decoder including means for attachment to a PLD, means for sequentially testing each PLD terminal to determine whether the terminal is an input or an output, means for sequentially applying all possible input combinations to the inputs and, for each combination, determining the condition of each output, and means for processing the conditions in order to determine the function of the output.
2. 2. A PLD decoder as claimed in Claim 1 wherein input combinations are applied for each output in turn.
3. 3. A PLD decoder as claimed in Claim 1 or in Claim 2 wherein the decoder includes a test socket capable of accepting devices having a plurality of pins, and means whereby the decoder can be informed of the number of pins on the device so that power supplies can be automatically routed to the correct pins.
4. 4. A PLD decoder as claimed in Claim 3 wherein the test socket is a zero insertion force variant.
5. 5. A PLD decoder as claimed in Claim 3 or in Claim 4 wherein the decoder also contains a versatile interface to the test socket, and a first computer with interconnections by which the decoder can be connected to act in partnership with a second, host computer.
6. 6. A PLD decoder as claimed in Claim 4 or in Claim 5 wherein the first computer is Z80 - based
7. 7. A PLD decoder as claimed in Claim 5 or in Claim 6 wherein the second computer has a visual display.
8. 8. A PLD decoder as claimed in any one of claims 1 to 7 wherein a test programme is controlled with the aid of a mouse driven menu which offers the facilities to modify the component test conditions, select specific outputs, manipulate results and load differing device sizes.
9. 9. A PLD decoder as claimed in any one of Claims 5 to 7 including a pseudo ring of data slots whereby data can be passed between the first and second computers.
10. 10. A method of testing a programmed PLD including the steps of connecting the device to a PLD decoder, sequentially testing each terminal of the device to determine whether it is an input or an output, sequentially applying all possible input combinations to the inputs and, for each combination, determining the condition at the outputs, and processing the conditions to determine the full function of the PLD.
11. 11. A PLD decoder substantially as herein described with reference to Figure 1 to 4 of the accompanying drawing.
12. 12. A method of testing a programmed PLD substantially as herein described with reference to Figuresl to 4 of the accompanying drawings.