GB2252200A - Electrostatic discharge protecting apparatus for semiconductor device - Google Patents
Electrostatic discharge protecting apparatus for semiconductor device Download PDFInfo
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- GB2252200A GB2252200A GB9117736A GB9117736A GB2252200A GB 2252200 A GB2252200 A GB 2252200A GB 9117736 A GB9117736 A GB 9117736A GB 9117736 A GB9117736 A GB 9117736A GB 2252200 A GB2252200 A GB 2252200A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 230000003071 parasitic effect Effects 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 claims description 3
- 230000007547 defect Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The disclosure relates to protecting a semiconductor device against electrostatic discharges occurring between any two of a pad, a ground terminal, and a power source terminal. The protecting device includes a first diffused region 33 of a first conduction type connected to the input/output pad 32; a second diffused region 35 of the first conduction type connected to the power source terminal 38; and a third diffused region 34 of the first conduction type connected to the ground terminal 39. The first to third diffused regions are separated from each other, and are formed on a semiconductor substrate of a second conduction type or within wells of the second conduction type. Where the depths of the diffused regions are thin, the diffused regions can be respectively formed within wells with low concentration of the first conduction type. <IMAGE>
Description
ELECTROSTATIC DISCHARGE PROTECTING APPARATUS FOR
SEMICONDUCTOR DEVICE
The present invention relates to an electrostatic discharge (ESD) protecting apparatus for a semiconductor device, and particularly although not exclusively, to a device in which electrostatic discharge occurring between a pad and a power source terminal Vcc, between the pad and a ground terminal Vss, or between the power source terminal Vcc and the ground terminal Vss can be prevented.
A conventional high density metal-oxide-semiconductor (MOS) integrated circuit is very sensitive to externally created electrical disturbances, and if subjected to such a disturbance the internal structure of the chip can be adversely affected. Particularly, in order to protect a chip from the influence of a momentary electrostatic discharge, a protection circuit is provided at each input/output pad.
The provision of the protection circuit gives many advantageous effects, but in a high density circuit designed with a design rule of less than 1 micro-meter (cm), the electrostatic discharge occurring in the power bus, i.e., in the power source terminal Vcc or the ground terminal Vss, is considerable.
A research on the prevention of electrostatic discharge occurring between a ground terminal and a power source terminal is disclosed under the title of "Internal
Chip ESD Phenomena Beyond The Protection Circuit", in an
IEEE journal, "TRANSACTIONS ON ELECTRON DEVICE", on pages 2133-2139, volume 35, No. 12, Dec. 1988.
Figures 1A and 1B of the accompanying drawings illustrate a part of the contents of the above treatise, and show a sectional view of a conventional inverter.
Figure 1A illustrates an electrostatic discharge occurring from a power source terminal Vcc to a ground terminal Vss, and Figure 1B illustrates an electrostatic discharge occurring from the ground terminal Vss to the power source terminal Vcc.
Referring to Figure 1A of the accompanying drawings, the power source terminal Vcc is connected to a source 3 of a PMOS transistor, and a ground terminal Vss is connected to a source 5 of an NMOS transistor. Thus, if a stress which is positive with respect to the ground terminal Vss is applied to the power source terminal Vcc, a stress current 7 flows through a parasitic p-n-p-n device which exists between the source 3 of the PMOS transistor and the source 5 of the NMOS transistor. This stress causes a defect in the device. The voltage of such an electrostatic discharge is of the order of a few kilovolts (kV), and therefore a defect occurs along the portion where the stress current flows thereby making the device inferior.
Meanwhile, referring to Figure 1B of the accompanying drawings, if a stress which is positive with respect to the power source terminal Vcc is applied to the ground terminal Vss, a stress current 8 flows from the source 5 of the NMOS transistor to the source 4 of the PMOS transistor, thereby causing a defect and device inferiority, as in the case of Figure 1A. To reduce the likelihood of defects occurring, such a stress current caused by the electrostatic discharge has to be guided through a separate path.
Figure 2 of the accompanying drawings is a plan view showing the structure of part of a conventional device which is arranged for reducing an electrostatic discharge occurring between a pad and a ground terminal.
Referring to Figure 2 of the accompanying drawings the conventional device has a p type substrate, a pad 21 and an n+ diffused region 23. The pad 21 and the n+ diffused region 23 are connected by means of metal 22. A field oxide layer 26 is disposed between an n+ diffused region 24 connected to a ground bus 25 and an n+ diffused region 23 connected to the pad 21. In such a structure, if a stress due to an electrostatic discharge is applied to the pad 21, a punch-through occurs from the n+ diffused region 23 connected to the pad 21 to the n+ diffused region 24 connected to the ground bus 25. Thus in this structure, a stress current flows through an parasitic n-p-n bipolar transistor including the p-type substrate, and therefore protection of other parts of the semiconductor device against the electrostatic discharge is provided.
However, with the conventional device as described above, protection can not be provided against electrostatic discharges occurring between the pad and the power source terminal, or between the power source terminal and the ground terminal.
Therefore, it is an object of specific embodiments of present invention to provide means for protecting a semiconductor device against electrostatic discharges occurring between a pad and a power source terminal, between the power source terminal and a ground terminal, as well as between the pad and the ground terminal.
According to one aspect of the present invention there are provided means for protection of circuit elements of a semiconductor device from electrostatic discharge, said semiconductor device having a connection pad a ground terminal and a power source terminal, said means comprising;
a first, a second and a third region each of a first conduction type formed in a substrate region of a second conduction type, the first region being connected to the connection pad, the second region being connected to the power source terminal, and the third region being connected to the ground terminal, said regions arranged such that on application of a said electrostatic discharge, the discharge flows between said regions of the first conduction type in preference to flowing through said elements.
Preferably, said means are arranged such that on application of a said electrostatic discharge, breakdown occurs between one of said first, second or third regions and another one of said first, second or third regions, via said substrate region.
Preferably, said first, second and third regions are separated from each other by said substrate region and by a first insulating layer.
Said first, second or third region may form an an ann±p±n±p±n+, or a p±n-p±n-p+, or a p+ parasitic junction with said substrate region.
Said first second or third region may have a well of a first conduction type separating said first, second or third region from said substrate region.
Said first region may have a corresponding said first well;
said second region may have a corresponding said second well; and
said third region may have a corresponding said third well.
Where a said first secon or third well is provided, preferably a said first second or third region and a corresponding said first second or third well forms an n+n-p, an n±n-p+, an p±p-n or a p±p-n+ junction with said substrate region.
Preferably, said first, second or third region, or where provided, a well region, is a diffused region.
Preferably, said first insulating layer is a field oxide layer disposed on an upper surface of said substrate between said regions of the first conduction type.
Preferably, said second region is arranged between said first and third regions.
Said substrate region may be a substrate well region formed in a semiconductor wafer.
The invention includes an electrostatic discharge protecting apparatus for an integrated semiconductor device having an input/output pad, a power source terminal and a ground terminal, said apparatus comprising:
a first diffused region of a first conduction type connected to said input/output pad;
a second diffused region of the first conduction type separated from said first diffused region by means of a field oxide layer disposed therebetween, said second diffused region being connected to said power source terminal or to said ground terminal; and
a third diffused region of the first conduction type separated from said second diffused region by means of the field oxide layer disposed therebetween, said third diffused region being connected to said power source terminal or to said ground terminal,
said first, second and third diffused regions being formed on a semiconductor substrate of a second conduction type or within wells of the second conduction type.
Preferably, said first, second and third diffused regions are n+ or p+ diffused regions.
The invention also includes an electrostatic discharge protecting apparatus for an integrated semiconductor device having an input/output pad, a power source terminal and a ground terminal, said apparatus comprising:
a first diffused region of a first conduction type connected to said power source terminal or said ground terminal;
a second diffused region of the first conduction type separated from said first diffused region by means of a field oxide layer disposed therebetween, said second diffused region being connected to said input/output pad; and
a third diffused region of the first conduction type separated from said second diffused region by means of the field oxide layer disposed therebetween, said third diffused region being connected to said ground terminal or to said power source terminal, said first, second and third regions being formed on a semiconductor substrate of a second conduction type or within wells of the second conduction type.
The invention further includes an electrostatic discharge protecting apparatus for an integrated semiconductor device having an input/output pad, a power source terminal and a ground terminal, said apparatus comprising:
a first diffused region of a first conduction type connected to said input/output pad;
a second diffused region of the first conduction type separated from said first diffused region by means of a field oxide layer disposed therebetween, said second diffused region being connected to said power source terminal or to said ground terminal;
a third diffused region of the first conduction type separated from said second diffused region by means of the field oxide layer disposed therebetween, said third diffused region being connected to said ground terminal or to said power source terminal; and
first, second and third wells of the first conduction type formed respectively under said first, second and third diffused regions, said first, second and third wells being separated from each other.
Preferably, doping concentrations of said first, second and third wells are lower than those of said first, second and third diffused regions.
The invention further includes an electrostatic discharge protecting apparatus for an integrated semiconductor device having an input/output pad, a power source terminal and a ground terminal, said apparatus comprising:
a first diffused region of a first conduction type connected to said power source terminal or to said ground terminal;
a second diffused region of the first conduction type separated from said first diffused region by means of a field oxide layer disposed therebetween, said second diffused region being connected to said input/output pad;
a third diffused region of the first conduction type separated from said second diffused region by means of the field oxide layer disposed therebetween, said third diffused region being connected to said ground terminal or to said power source terminal; and
first, second and third wells of the first conduction type formed respectively under said first, second and third diffused regions, said first, second and third wells being separated from each other.
Preferably, a doping concentration of said first, second or third wells are lower than those of said first, second or third diffused regions.
The invention includes a semiconductor device having an electrostatic discharge protecting apparatus or having means for protection of circuit elements as herein described.
The invention includes electrostatic discharge protecting apparatus in semiconductor devices having an input/output pad, a power source terminal and a ground terminal , in which: a first diffused region of a first conduction type connected to the input/output pad; a second diffused region of the first conduction type separated with a given distance from the first diffused region by means of a field oxide layer, the second diffused region being connected to the power source terminal; and a third diffused region of the first conduction type separated with a given distance from the second diffused region by means of the field oxide layer, the third diffused region connected to the ground terminal. In this case, the first to third diffused regions may be formed on a semiconductor substrate of a second conduction type, or in a well of the second conduction type.Further, in the case where the depths of the first to third diffused regions are thin, the above diffused regions can be formed in low concentration wells of the first conduction type.
For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which:
Figures 1A and 1B illustrate the mechanism of electrostatic discharges occurring in a conventional semiconductor device;
Figure 2 illustrates a plan view of a conventional known invention;
Figure 3A illustrates a plan view of a first specific embodiment according to the present invention;
Figure 3B is a sectional view taken along the line X
Y of Figure 3A; and
Figure 3C is a sectional view of a second specific embodiment according to the present invention.
Referring to Figures 3A and 3B of the accompanying drawings, a pad 31 is connected by means of metal 32 to an n+ diffused region 33 formed on a semiconductor substrate 30. A power source bus 39 and a ground bus 38 are respectively connected to n+ diffused regions 34 and 35 formed on the semiconductor substrate 30. The power source bus 39 and the ground bus 38 are made of metal, and field oxide layers 40 are formed between the n+ diffused regions 33, 34 and 35. Contacts between the diffused regions 33, 34 and 35 and the metals 32, 39 and 38 respectively are made through contact holes 42 which are formed after formation of the field oxide layers 40 and the diffused regions 33, 34 and 35, and a covering thick intermediate insulating layer 41.
If the above described first specific embodiment is used, even if stress currents are produced between the pad 31 and the power source terminal or between the power source terminal and the ground terminal, the protection is expanded compared with the conventional device, owing to the existence of the current paths formed by the punchthrough phenomena between the n+ diffused regions 33, 34 and 35.
Accordingly, for the case of an electrostatic discharge between the pad and the power source terminal, protection may be provided even against a discharge voltage of over 3000 volts. Further, for the case of an electrostatic discharge between the power source terminal and the ground terminal, protection may also be provided against a discharge voltage of over 3000 volts. Those who are skilled in the art will easily understand that the substrate 30 can be substituted for by a substrate well having a conduction type which is opposite to a conduction type of the diffused regions.
Figure 3C of the accompanying drawings illustrates a second specific embodiment of the present invention, which is applicable where thin n+ diffused regions 42, 43, 44 are present on a substrate 30.
Referring again to the conventional device of Figure 2B of the accompanying drawings, if the n+ diffused regions 33, 34 and 35 are thin, the flow of the current caused by the punch-through phenomena between the n+ diffused regions is weakened, and a large electric field is loaded on an p junction between the substrate 30 and the n+ diffused regions 33, 34 and 35, with the result that a large amount of heat is generated. In order to prevent such phenomenon, in the second specific embodiment, as shown in Figure 3C, of the accompanying drawings, the n+ diffused regions 42, 43 and 44 with thin depths are respectively formed within n-type wells 45, 46 and 47.
Referring again to Figure 3C of the accompanying drawings, a junction portion is formed between the n-type wells 45, 46 and 47 each of which have lower concentrations relative to the above described n+ diffused regions, and therefore the effect of the large field effect can be alleviated. Further, owing to the n-type wells 45, 46 and 47, there are formed not only punchthrough paths between the n+ diffused regions but also punch-through paths between the n-type wells, with the result that a large current can be allowed to flow therethrough, thereby alleviating the short-comings of the thin n+ diffused regions.
It will be appreciated by those skilled in the art that the first, second and third regions can be spaced apart from each other by distances which are dictated by design rule limitations and the breakdown characteristics and thermal conductivity characteristics of the substrate material, the first, second or third regions, and the interfaces between the substrate and the first second or third regions. Similarly, such considerations may dictate the depth of the firsty, second or third regions or their shape.
According to the specific embodiments of the present invention as described above, there can be inhibited stresses which are caused by electrostatic discharges occurring between a pad and a power source terminal, or between the power source terminal and a ground terminal, as well as between the pad and the ground terminal.
While the invention has been particularly shown and described with reference to preferred specific embodiments, it will be understood by those skilled in the art that modifications in detail may be made without departing from the spirit and scope of the invention.
The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.
All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.
Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.
Claims (20)
1. Means for protection of circuit elements of a semiconductor device from electrostatic discharge, said semiconductor device having a substrate region a connection pad a ground terminal and a power source terminal, said means comprising;
a first, a second and a third region each of a first conduction type formed in a substrate region of a second conduction type, the first region being connected to the connection pad, the second region being connected to the power source terminal, and the third region being connected to the ground terminal, said regions arranged such that on application of a said electrostatic discharge, the discharge flows between said regions of the first conduction type in preference to flowing through said elements.
2. Means according to claim to 1, arranged such that on application of a said electrostatic discharge, breakdown occurs between one of said first, second or third regions and another one of said first, second or third regions, via said substrate region.
3. Means according to claim 1 or 2, wherein said first, second and third regions are separated from each other by said substrate region and by a first insulating layer.
4. Means according to any one of claims 1 to 3 wherein said first, second or third region forms an n±p-n±p-n+, an n±p±n±p±n+, or a p±n-p±n-p+, or a parasitic junction with said substrate region.
5. Means according to any one of claims 1 to 4, wherein said first second or third region has a well of a first conduction type separating said first, second or third region from said substrate region.
6. Means according to claim to 5, wherein said first region has a corresponding said first well;
said second region has a corresponding said second well; and
said third region has a corresponding said third well.
7. A semiconductor device according to claim 5 or 6, wherein a said first second or third region and a corresponding said first second or third well forms an n-p, an n±n-p+, an p±p-n or a p±p-n+ junction with said substrate region.
8. Means according to any one of claims 1 to 7, wherein said first, second or third region, or a well region is a diffused region.
9. Means according to any one of claims 1 to 8, wherein said first insulating layer is a field oxide layer disposed on an upper surface of said substrate between said regions of the first conduction type.
10. Means according to any one claims 1 to 9, in which said second region is arranged between said first and third regions.
11. Means according to any one of claims 1 to 10, wherein said substrate region is a substrate well region formed in a semiconductor wafer.
12. An electrostatic discharge protecting apparatus for an integrated semiconductor device having an input/output pad, a power source terminal and a ground terminal, said apparatus comprising:
a first diffused region of a first conduction type connected to said input/output pad;
a second diffused region of the first conduction type separated from said first diffused region by means of a field oxide layer disposed therebetween, said second diffused region being connected to said power source terminal or to said ground terminal; and
a third diffused region of the first conduction type separated from said second diffused region by means of the field oxide layer disposed therebetween, said third diffused region being connected to said power source terminal or to said ground terminal,
said first, second and third diffused regions being formed on a semiconductor substrate of a second conduction type or within wells of the second conduction type.
13. An electrostatic discharge protecting apparatus as claimed in claim 12, wherein said first, second and third diffused regions are n+ or p+ diffused regions.
14. An electrostatic discharge protecting apparatus for an integrated semiconductor device having an input/output pad, a power source terminal and a ground terminal, said apparatus comprising:
a first diffused region of a first conduction type connected to said power source terminal or said ground terminal;
a second diffused region of the first conduction type separated from said first diffused region by means of a field oxide layer disposed therebetween, said second diffused region being connected to said input/output pad; and
a third diffused region of the first conduction type separated from said second diffused region by means of the field oxide layer disposed therebetween, said third diffused region being connected to said ground terminal or to said power source terminal, said first, second and third regions being formed on a semiconductor substrate of a second conduction type or within wells of the second conduction type.
15. An electrostatic discharge protecting apparatus for an integrated semiconductor device having an input/output pad, a power source terminal and a ground terminal, said apparatus comprising:
a first diffused region of a first conduction type connected to said input/output pad;
a second diffused region of the first conduction type separated from said first diffused region by means of a field oxide layer disposed therebetween, said second diffused region being connected to said power source terminal or to said ground terminal;
a third diffused region of the first conduction type separated from said second diffused region by means of the field oxide layer disposed therebetween, said third diffused region being connected to said ground terminal or to said power source terminal; and
first, second and third wells of the first conduction type formed respectively under said first, second and third diffused regions, said first, second and third wells being separated from each other.
16. An electrostatic discharge protecting apparatus as claimed in claim 15, wherein doping concentrations of said first, second and third wells are lower than those of said first, second and third diffused regions.
17. An electrostatic discharge protecting apparatus for an integrated semiconductor device having an input/output pad, a power source terminal and a ground terminal, said apparatus comprising:
a first diffused region of a first conduction type connected to said power source terminal or to said ground terminal;
a second diffused region of the first conduction type separated from said first diffused region by means of a field oxide layer disposed therebetween, said second diffused region being connected to said input/output pad;
a third diffused region of the first conduction type separated from said second diffused region by means of the field oxide layer disposed therebetween, said third diffused region being connected to said ground terminal or to said power source terminal; and
first, second and third wells of the first conduction type formed respectively under said first, second and third diffused regions, said first, second and third wells being separated from each other.
18. An electrostatic discharge protecting apparatus as claimed in claim 18, wherein a doping concentration of said first, second or third wells are lower than those of said first, second or third diffused regions.
19. An electrostatic discharge protecting apparatus substantially as herein described with reference to
Figures 3A and 3B or Figures 3B and 3C of the accompanying drawings.
20. A semiconductor device having an electrostatic discharge protecting apparatus or having means for protection of circuit elements as herein before claimed.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910001128A KR920015549A (en) | 1991-01-23 | 1991-01-23 | Electrostatic Discharge Protection Device for Semiconductor Devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9117736D0 GB9117736D0 (en) | 1991-10-02 |
| GB2252200A true GB2252200A (en) | 1992-07-29 |
Family
ID=19310210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9117736A Withdrawn GB2252200A (en) | 1991-01-23 | 1991-08-16 | Electrostatic discharge protecting apparatus for semiconductor device |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH04249373A (en) |
| KR (1) | KR920015549A (en) |
| DE (1) | DE4126047A1 (en) |
| FR (1) | FR2671911A1 (en) |
| GB (1) | GB2252200A (en) |
| IT (1) | IT1251010B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR940009605B1 (en) * | 1991-09-16 | 1994-10-15 | 삼성전자 주식회사 | Electrostatic Discharge Protection Device for Semiconductor Memory |
| KR100494343B1 (en) * | 2000-12-27 | 2005-06-13 | 주식회사 하이닉스반도체 | Method of manufacturing a field transistor in a semiconductor memory device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3590340A (en) * | 1967-02-27 | 1971-06-29 | Hitachi Ltd | Breakdown preventing circuit and an integrated device thereof for a semiconductor device having an insulate gate electrode |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1242532A (en) * | 1984-05-03 | 1988-09-27 | Chong M. Lin | Input protection arrangement for vlsi intergrated circuit devices |
| JPS62285460A (en) * | 1986-06-03 | 1987-12-11 | Toshiba Corp | input protection circuit |
| US4825280A (en) * | 1986-10-01 | 1989-04-25 | Texas Instruments Incorporated | Electrostatic discharge protection for semiconductor devices |
| JPH061802B2 (en) * | 1989-03-14 | 1994-01-05 | 株式会社東芝 | Semiconductor device |
-
1991
- 1991-01-23 KR KR1019910001128A patent/KR920015549A/en not_active IP Right Cessation
- 1991-07-15 FR FR9108874A patent/FR2671911A1/en not_active Withdrawn
- 1991-08-06 DE DE4126047A patent/DE4126047A1/en not_active Ceased
- 1991-08-13 IT ITMI912252A patent/IT1251010B/en active IP Right Grant
- 1991-08-16 GB GB9117736A patent/GB2252200A/en not_active Withdrawn
- 1991-08-20 JP JP3207933A patent/JPH04249373A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3590340A (en) * | 1967-02-27 | 1971-06-29 | Hitachi Ltd | Breakdown preventing circuit and an integrated device thereof for a semiconductor device having an insulate gate electrode |
Also Published As
| Publication number | Publication date |
|---|---|
| DE4126047A1 (en) | 1992-08-06 |
| ITMI912252A0 (en) | 1991-08-13 |
| KR920015549A (en) | 1992-08-27 |
| JPH04249373A (en) | 1992-09-04 |
| ITMI912252A1 (en) | 1993-02-13 |
| IT1251010B (en) | 1995-04-28 |
| FR2671911A1 (en) | 1992-07-24 |
| GB9117736D0 (en) | 1991-10-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |