GB2247987A - Metallic interconnections for semiconductor devices - Google Patents
Metallic interconnections for semiconductor devices Download PDFInfo
- Publication number
- GB2247987A GB2247987A GB9119025A GB9119025A GB2247987A GB 2247987 A GB2247987 A GB 2247987A GB 9119025 A GB9119025 A GB 9119025A GB 9119025 A GB9119025 A GB 9119025A GB 2247987 A GB2247987 A GB 2247987A
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- GB
- United Kingdom
- Prior art keywords
- interlayer insulation
- insulation film
- conductor layer
- film
- conductive pillar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A first layer insulation film 79 and a planarising film (81 Fig 1H) are formed in turn on an insulating film 67 and a lower conductive layer 65 on which an electrically conductive pillar 77 is formed. The surface of the planarising film is more planar than the surface of the first interlayer insulation film 79. The surface of the planarising film and part of the surface of the first interlayer insulation film 79 are then etched away to expose the head of the conductive pillar 77. An upper conductive layer 83 is then formed on the head of the conductive pillar 77. Thus, the upper and lower conductive layers are connected with each other using fewer steps than those required in a conventional method. <IMAGE>
Description
1 METHOD OF CONNECTING UPPER AND LOWER INTERCONNECTIONS
TITLE OF THE INVENTION
Method of Connecting Upper and Lower Interconnections BACKGROUND OF THE INVENTION Field of the Invention
The present invention relates generally to methods of manufacturing semiconductor devices and, more particularly, to a method of connecting an upper interconnection and a lower interconnection. Description of the Background Art
A description will be made on one example of conventional methods of connecting upper and lower interconnections with reference to Figs. 2A 2G.
A silicon substrate 1 isTprepared as shown in Fig. 2A.
Then, a silicon oxide film 3, a first aluminum interconnection layer 5, an interlayer insulation film 7 formed of a silicon oxide film and a photoresist 9 are formed in turn over the entire surface of a main surface of ----'.',,-on substrate 1, as shown in Fig. 2B.
Photoresist 9 is then subjected to a predetermined patterning, with reference to Fig. 2C.
Interlayer insulation film 7 is subjected to an isotropical etching with photoresist 9 used as a mask, as shown in Fig. 2D. The etching is stopped when interlayer insulation film 7 is etched away to a predetermined depth.
- 1 1 1 With photoresist 9 employed as a mask, interlayer insulation film 7 is subjected to an anisotropical etching, to complete a contact hole 11 as shown in Fig. 2E.
Referring to Fig. 2F, photoresist 9 is removed. A second aluminum interconnection layer 13 is formed over the entire main surface of silicon substrate 1.
Second aluminum interconnection layer 13 is then subjected to a predetermined patterning as shown in Fig. 2G.
A portion of second aluminum interconnection layer 13 formed on interlayer insulation film 7 is an upper interconnection. First aluminum interconnection layer 5 is a lower interconnection.
As shown in Fig. 2G, upper sidewalls of contact hole 11 are inclined. This provides an excellent adhesion of second aluminum interconnection layer 13 on the sidewalls of contact hole 11.
It is possible that the connect.ion the upper and lower interconnections becomes defective when an aspect ratio of the contact hole, i.e., a ratio of the depth of the contact hole to the lateral dimension of the contact hole becomes high. This will now be described with reference to Figs. 3 and 4.
Fig. 3 is a cross-sectional view showing a connecting 1 portion between the upper and lower interconnections in the case where the aspect ratio is 1 or less. The dimension shown by a reference character A is the lateral dimension of the contact hole. The dimension shown by a reference character B is the depth of the contact hole. If the aspect ratio is 1 or less, then an excellent electrical connection is provided between second aluminum interconnection layer 13 serving as the upper interconnection and first aluminum interconnection layer 5 serving as the lower interconnection. If the aspect ratio is higher than 1, however, there is a case that an excellent electrical connection is not provided between second aluminum interconnecti6n layer 13 and first aluminum interconnection layer 5, as shown in Fig. 4. This is because the opening of contact hole 11 is covered with aluminum deposited on the upper sidewalls of contact hole 11 before the bottom of contact hole 11 is filled with the aluminum.
As the Luagree of integration of semiconductor devices becomes higher, the lateral dimension of contact holes becomes smaller. On the contrary, the thickness of an interlayer insulation film cannot be reduced to a thickness lower than or equal to a predetermined value in consideration of the danger of producing pinholes or the like. Thus, the aspect ratio is liable to increase.
1 r, As a method which ensures the electrical connection between upper and lower interconnections even if the aspect ratio increases, a method is provided in which the electrical connection between the upper and lower interconnections is made by employing a metal formed by a selective CVD method. This method will be described with reference to Figs. 5A - 5G.
A silicon substrate 15 is prepared as shown in Fig. 5A.
Referring to Fig. 5B, a silicon oxide film 17, a first aluminum interconnection layer 19, an interlayer insulation film 21 formed of a silicon oxide film, and a photoresist 23 are formed-in turn over the entire surface of a main surface of silicon substrate 15.
Photoresist 23 is then subjected to a predetermined patterning as shown in Fig. 5C.
Interlayer insulation film 21 is subjected to an anisotropical etching with photoresist 23 used as a mask, to form a contact hole 25, as shom in Fig. 5D.
Referring to Fig. 5E, tungsten 27 is selectively formed in contact hole 25 by employing a CVD (Chemical Vapor Deposition) method. The reason why tungsten 27 is selectively formed only in contact hole 25 is that a material gas including tungsten reacts with aluminum and does not easily react with a silicon oxide film. Since the material gas including tungsten reacts a little with the silicon oxide film, a thin film made of tungsten 27 is formed on a main surface of interlayer insulation film 21.
Tungsten 27 formed on interlayer insulation film 21 is etched away, as shown in Fig. 5F.
Referring to Fig. 5G, a second aluminum interconnection layer 29 is formed on interlayer insulation film 21. Second aluminum interconnection layer 29 is then subjected to a predetermined patterning.
The selective CVD method is disclosed in an article, for example, IEEE June 13 - 14, 1988, pp. 125 - 134.
The selective CVD method is, however, still under research and hence has not yet been utilized for manufacture of semiconductor devices.
As an approach which can solve the above-described two problems, a method disclosed in Japanese Patent Laying-Open No. 61-116834 is proposed. This method will now be described with reference to Figs. 6A - 6F.
As shown in Fig. bi,., field oxide films 33 are formed on opposite ends of a main surface of a substrate 31. A source region 37 and a drain region 39 are formed to be spaced apart from each other in the vicinity of the main surface of substrate 31 interposed between field oxide films 33. An insulator film 43 is formed on the main surface of substrate 31 between source and drain regions
37 and 39. A gate electrode 41 is formed on insulator film 43.
A polysilicon layer 35 is formed on the one field oxide film 33. A buffer oxide layer 45 is formed over the entire main surface of substrate 31. A contact hole 47a is formed in buffer oxide layer 45 formed on polysilicon layer 35. A contact hole 47b is formed in buffer oxide layer 45 formed on source region 37. A contact hole 47c is formed in buffer oxide layer 45 formed on drain region 39. - Referring to Fig. 6B, a first aluminum interconnection layer 49 is formed over the entire main surface of substrate 31. A EFhotoresist 51 is formed on first aluminum interconnection layer 49.
As shown in Fig. 6C, photoresist 51 is subjected to a predetermined patterning. With photoresist 51 used as a mask, first aluminum interconnection layer 49 is selectively etched away, to form electrically conductive pillars 53a, 53b and 53c.
A phospho-silicate glass 55 and a resist 57 are formed in turn over the entire main surface of substrate 31, with reference to Fig. 6D.
Referring to Fig. 6E, resist 57 is subjected to ashing. The ashing is performed until phospho-silicate glass 55 formed on conductive pillars 53a, 53b and 53c is 6 exposed. Then, with resist 57 used as a mask, interlayer insulation films 55a, 55b and 55c formed respectively on conductive pillars 53a, 53b and 53c are selectively etched away. The remaining resist 57 is removed thereafter.
A second aluminum interconnection layer 59 is formed over the entire main surface of substrate 31, as shown in Fig. 6F. Second aluminum interconnection layer 59 is then subjected to a predetermined patterning.
Referring to Fig. 6C, changing the lateral dimension of resist 51 serving as a mask makes it possible to freely control the lateral dimensions of conductive pillars 53a, 53b and 53c. This ensures the electrical connection between upper and lower inter6onnections even if the degree of integration of semiconductor devices becomes higher.
In addition, since the electrical connection between the upper and lower interconnections is made by employing a general-use technology, semiconductor devices can be manufactured immediatel,.
The method disclosed in Japanese Patent Laying-Open No. 61-116834, however, has some problems as follows. As shown in Fig. 6E, the heads of conductive pillars 53a, 53b and 53c are exposed through the following steps (1) - (3).
(1) Resist 57 is kept ashed until interlayer insulation films 55a, 55b and 55c formed respectively on conductive pillars 53a, 53b and 53c are exposed.
(2) Interlayer insulation films 55a, 55b and 55c are etched away with resist 57 used as a mask, so as to expose the respective heads of conductive pillars 53a, 53b and 53c.
(3) The remaining resist 57 is removed.
In this method, the heads of conductive pillars 53a, 53b and 53c are exposed through the foregoing three steps. Therefore, it takes time to electrically connect the upper and lower interconnections.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method in which the electricai connection between an upper interconnection and a lower interconnection can simply be made.
Another object of the present invention is to provide a method in which erosion of a lower interconnection can be avoided in the case of the electrical connection between an upper inteiconnection and the lower interconnection.
A further object of the present invention is to provide a method in which melting of a lower interconnection can be avoided.
A method of connecting upper and lower interconnections in accordance with the present invention 1 includes the steps of: forming a second interlayer insulation film on a first conductor layer; forming a contact hole by selectively etching away the second interlayer insulation film, to expose a portion of the first conductor layer; forming a third conductor layer on the second interlayer insulation film including the exposed first conductor layer; selectively etching away the third conductor layer, to form on the contact hole an electrically conductive pillar formed of the third conductor layer electrically connected with the first conductor layer; forming a first interlayer insulation film on the second interlayer insulation film including the conductive pillar; forming on the first interlayer insulation film a planar film, the formed surface of which 15 becomes more planar than the surface of the first interlayer insulation film; etching back a layer formed of the planar film and the first interlayer insulation film, to expose a head of the conductive pillar; and forming a second conductor layer, electrically connected with the conductive pillar, on the exposed head of the conductive pillar.
In the method of connecting the upper and lower interconnections in accordance with the present invention, the layer including the planar film and the first interlayer insulation film is etched back, so as to expose 9 the head of the conductive pillar. Therefore, according to the present invention, the head of the conductive pillar can be exposed through a smaller number of steps as compared with the steps required in the method disclosed in Japanese Patent Laying-Open No. 61-116834, in which with a resist used as a mask, the interlayer insulation film on the conductive pillar is removed to expose the head of the conductive pillar.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
Figs. 1A - 1K are cross-sectional views showing in the order of steps one embodiment of a method of connecting upper and lower interconnections in accordance with the present invention; Fig. 1L is a cro8s-sectional view showing the state where a portion of an aluminum interconnection is eroded; Figs. 2A - 2G are cross-sectional views showing in the order of steps one example of conventional methods of connecting upper and lower interconnections; Fig. 3 is a cross-sectional view showing a connecting portion between upper and lower interconnections in the - case where an aspect ratio is lower than or equal to 1; Fig. 4 is a cross-sectional view showing the connecting portion between upper and lower interconnections in the case where the aspect ratio is higher than 1; Figs. 5A - 5G are cross-sectional views showing in the order of steps another example of a method of connecting upper and lower interconnections; and Figs. 6A - 6F are cross-sectional views showing in the order of steps a method disclosed in Japanese Patent Laying-Open No. 61-116834. DESCRIPTION OF THE PREFERRED EMBODIMENTS
A description will now be made on one embodiment of a method of connecting upper and lower interconnections in accordance with the present invention, with reference to Figs. 1A - 1K.
A silicon substrate 61 is first prepared as shown in Fig. 1A.
A silicon oxide film 63 is then turm-d over the entire surface of a main surface of silicon substrate 61 by employing a CVD method, as shown in Fig. 1B. A first aluminum interconnection layer 65 is formed on silicon oxide film 63 by sputtering. A second interlayer insulation film 67 formed of a thin TEOS (tetraethyl orthosilicate) film is formed on first aluminum 11 - interconnection layer 65. The TEOS film is employed because the film can be formed at a temperature not higher than a melting point of aluminum, thereby to prevent transformation of first aluminum interconnection layer 65.
A photoresist 69 is formed on second interlayer insulation film 67. Photoresist 69 is then subjected to a predetermined patterning.
As shown in Fig. 1C, with photoresist 69 used as a mask, second interlayer insulation film 67 is selectively etched away, so as to form a contact hole 71. Photoresist 69 is then removed.
A third aluminum interconnection layer 73 is formed on second interlayer insulatiodfilm 67 by sputtering, as shown in Fig. 1D.
A photoresist 75 is formed on third aluminum interconnection layer 73 and then subjected to a predetermined patterning, with reference to Fig. 1E.
With phoi.oresist 75 used as a mask, third aluminum interconnection layer 73 is selectively etched away, to form an electrically conductive pillar 77, as shown in Fig. 1F.
Photoresist 75 formed on conductive pillar 77 is then removed, as shown in Fig. 1G.
Referring to Fig. 1H, a first interlayer insulation film 79 formed of the TEOS film is-formed over the entire 12 - 1 main surface of silicon substrate 61. The reason why first interlayer insulation film 79 is formed of the TEOS film is the same as the reason in the case with second interlayer insulation film 67. A positive resist 81 is then formed over the entire main surface of silicon substrate 61. The surface of positive resist 81 is made more planar than the surface of first interlayer insulation film 79. This is because unless the surface of positive resist 81 is more planar than the surface of first interlayer insulation film 79, it is possible that first aluminum interconnection layer 65 is exposed before exposure of conductive pillar 77. In order that the surface of positive resist 81-is made more planar than that of first interlayer insulation film 79, positive resist 81 having a lower viscosity than that of first interlayer insulation film 79 is employed.
As shown in Fig. 1I, a layer including positive resist 81 and first interlayer insulation film 9 is etched back employing a mixed gas containing a.6F6 gas, CH2F2 gas and CQ 2 gas, so as to expose the head of conductive pillar 77. A flow rate ratio of the gases is as follows:
SF6: CH2F2: C 2 0. 6: 0. 7 Positive resist 81 remaining on first interlayer insulation film 79 is then removed.
13 - 1 Referring to Fig. 1J, a second aluminum interconnection layer 83 is formed over the overall main surface of silicon substrate 61 by sputtering. A photoresist 85 is formed on second aluminum interconnection layer 83 and then subjected to a predetermined patterning.
As shown in Fig. 1K, second aluminum interconnection layer 83 is selectively etched away with photoresist 85 used as a mask. Photoresist 85 formed on second aluminum interconnection layer 83 is then removed. One embodiment of the manufacture method of the semiconductor device according to the present invention is thus completed through the foregoing process.-_ The thickness of second interlayer insulation film 67 shown in Fig. 1K is preferably 1000A or more. This is because if the thickness of second interlayer insulation film 67 is smaller than 1000AF, it is possible that pinholes are produced in second interlayer insulation film 67.
An aspect ratio of contact hole 71 shown in Fig. 1K is preferably I or less. If the aspect ratio of contact hole 71 is higher than 1, then conductive pillar 77 and first aluminum interconnection layer 65 might cause a defective connection. The reason for the occurrence of the defective connection between conductive pillar 77 and 14 first aluminum interconnection layer 65 has already been described in the explanation of Fig. 4.
it is preferable that conductive pillar 77 is formed so that a sidewall 78 of conductive pillar 77 shown in Fig. 1K may be located on second interlayer insulation film 67. This is because if conductive pillar 77 is formed so that sidewall 78 of conductive pillar 77 may not lie on second interlayer insulation film 67 as shown in Fig. U, then a portion of first aluminum interconnection layer 65 is eroded by etching. The eroded portion is denoted with a reference numeral 87.
In this embodiment, as shown in Fig. lK, aluminum is employed for materials of-uppbr and lower interconnections and the conductive pillar. Te present invention is, however, not limited to the aluminum, and hence other electrically conductive members, e.g., polysilicon may be employed.
The TEOS film is employed for first and second interlayer insulation films 79 and 67 shown in Fig. 111%.. The present invention is, however, not limited to the TEOS film, and hence any films that can be formed at a temperature not higher than the melting point of aluminum may be employed. The possible films are, for example, a plasma silicon nitride film, a plasma chemical vapor deposited silicon oxide film, a spin-on glass film, etc.
is - In the method of connecting upper and lower interconnections in accordance with the present invention, the layer formed of the planar film and the first interlayer insulation film is etched back so as to expose the head of the conductive pillar. This makes it possible to expose the head of the conductive pillar through a smaller number of steps than the steps required in the conventional method. Accordingly, the productivity of semiconductor devices can be enhanced in accordance with the present invention.
Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitatfon, the spirit and scope of the present invention being limited only by the terms of the appended claims.
16 1
Claims (7)
1. A method of electrically connecting a first conductor layer (65) being a lower interconnection and a second conductor layer (83) being an upper interconnection, comprising the steps of: forming a second interlayer insulation film (67) on said first conductor layer (65); forming a contact hole (71) by selectively etching away said second interlayer insulation film (67), to expose a portion of said first conductor layer (65); forming a third conductor layer (73) on said second interlayer insulation film (0) and on exposed said first conductor layer (65); selectively etching away said third conductor layer (73), to form on said contact hole (71) an electrically conductive pillar (77) formed of said third conductor layer (73) electrically connected with said first conductor layer (65); forming a first interlayer insulation film (79) on said second interlayer insulation film (67) and on said conductive pillar (77); forming on said first interlayer insulation film (79) a planar film (81) having a formed surface made more planar than a surface of said first interlayer insulation 17 a I- film (79); etching away the overall surface of a layer including said planar film (81) and said first interlayer insulation film (79), to expose a head of said conductive pillar (77)r said planar film (81) and said first interlayer insulation film (79) being materials to be employed in etching back; and forming said second conductor layer (83) electrically connected with said conductive pillar (77), on the exposed head of said conductive pillar (77).
2. The method of claim 1, wherein said conductive pillar (77) forming step includes the steps of: forming a photoresist (75) on said third conductor layer (73), patterning said photoresist (75) so as to locate a sidewall of said photoresist (75) on said second interlayer insulation film (67), and with said photoresist (75) used as a mask, selectively etching away said third conductor layer (73), so as to form said conductor pillar (77) having a sidewall (78) located on said second interlayer insulation film (67).
3. The method of claim 1, wherein said first and second interlayer insulation films (79, 67) are formed by employing a plasma M method.
4. The method of claim 1, wherein said first, second and third conductor layers (65, 83, 73) include aluminum or polysilicon.
5. The method of claim 1, wherein said second interlayer insulation film (67) has a thickness larger than or equal to 1000A.
6. The method of claim wherein said contact hole (71) has an aspect ratio of 1 or lower.
7. A method of semiconductor processing for producing interconnected conductor layers, said process being performed substantially as described hereinbefore with reference to figures 1A to 1K of the drawings.
- 19 Published 1992 at The Patent Office, Concept House, Cardiff Road, Newport. Gwent NP9 IRH. Further copies may be obtained from Sales Branch, Unit 6. Nine Mile Point, Cwmfelinfach, Cross Keys, Newport. NP I 7HZ. Printed by Multiplex techniques lid. St Mary Cray, Kent.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2244511A JPH04123458A (en) | 1990-09-14 | 1990-09-14 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9119025D0 GB9119025D0 (en) | 1991-10-23 |
| GB2247987A true GB2247987A (en) | 1992-03-18 |
Family
ID=17119771
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9119025A Withdrawn GB2247987A (en) | 1990-09-14 | 1991-09-05 | Metallic interconnections for semiconductor devices |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH04123458A (en) |
| DE (1) | DE4130535A1 (en) |
| GB (1) | GB2247987A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950006343B1 (en) * | 1992-05-16 | 1995-06-14 | 금성일렉트론주식회사 | Fabricating method of semiconductor device |
| JPH0697288A (en) * | 1992-09-09 | 1994-04-08 | Kawasaki Steel Corp | Manufacture of semiconductor device |
| KR0140646B1 (en) * | 1994-01-12 | 1998-07-15 | 문정환 | Mancefacture of semicouductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0215542A2 (en) * | 1985-05-13 | 1987-03-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device including forming a multi-level interconnection layer |
| EP0285410A1 (en) * | 1987-04-01 | 1988-10-05 | Fairchild Semiconductor Corporation | Forming metal interconnects on uneven substrates |
| EP0317770A1 (en) * | 1987-11-23 | 1989-05-31 | Texas Instruments Incorporated | Self aligned planar metal interconnection for a VLSI device |
| JPH10116834A (en) * | 1996-10-11 | 1998-05-06 | Toshiba Corp | Method of manufacturing semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4892845A (en) * | 1984-08-31 | 1990-01-09 | Texas Instruments Incorporated | Method for forming contacts through a thick oxide layer on a semiconductive device |
-
1990
- 1990-09-14 JP JP2244511A patent/JPH04123458A/en active Pending
-
1991
- 1991-09-05 GB GB9119025A patent/GB2247987A/en not_active Withdrawn
- 1991-09-13 DE DE4130535A patent/DE4130535A1/en not_active Ceased
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0215542A2 (en) * | 1985-05-13 | 1987-03-25 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device including forming a multi-level interconnection layer |
| EP0285410A1 (en) * | 1987-04-01 | 1988-10-05 | Fairchild Semiconductor Corporation | Forming metal interconnects on uneven substrates |
| EP0317770A1 (en) * | 1987-11-23 | 1989-05-31 | Texas Instruments Incorporated | Self aligned planar metal interconnection for a VLSI device |
| JPH10116834A (en) * | 1996-10-11 | 1998-05-06 | Toshiba Corp | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04123458A (en) | 1992-04-23 |
| GB9119025D0 (en) | 1991-10-23 |
| DE4130535A1 (en) | 1992-03-19 |
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| Date | Code | Title | Description |
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| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |