GB2247577A - Power supply arrangement - Google Patents

Abstract

A load such as a microprocessor (22) is fed by a voltage regulator (42) which has an output enable terminal (HLD) and a low-output warning terminal (ERR) in addition to an input (BAT), an output (REG) and ground (GND) terminals. The output enable terminal (HLD) can be held in its active state by an external user pressing a push button (34), by a discharged capacitor (36), or by two FETs (38, 40) which are connected in series both conducting. These FETs behave as a NAND gate and operate to cause the output enable terminal (HLD) of the regulator to be in an inactive state in response to operation of a push button (20) and thus the off-request signal (DIS) being in an active state thereby causing the output (REG) voltage of the regulator to decrease causing the low-output warning terminal (ERR) to assume its active (error) state. Once the off-request terminal (DIS) has been activated no further control of the power supply is available to the microprocessor. This has the advantage that the microprocessor can initiate its own power off without fear that any erratic behaviour of its output lines as the regulator output (REG) falls will cause the reconnection of the power supply. <IMAGE>

Description

DESCRIPTION POWER SUPPLY ARRANGEMENT The present invention relates to a power supply arrangement which is concerned with electronically switching the power supplied to an electrical load, having particular, but not exclusive, application to a battery management system for use with portable equipment.

Electronic control of the power supply lines to electronic equipment is becoming increasingly common as it has a number of advantages over a mechanical switch. These advantages include a saving in mechanical wear, the possibility of shut-down with falling battery voltage and remote control. A block diagram of a microprocessor circuit including an electronically controlled power supply is shown in Figure 1 of the accompanying drawings. A battery 10 has a positive terminal which is connected to one terminal of a mechanical push switch 12 and to one terminal of an electronic switch 14. These two switches are both single pole single way devices and their remaining terminals are both connected to the input of a voltage regulator 16. The switch 14 is activated by a signal on a control line (shown dotted) which signal is provided by a microprocessor 22.The battery 10 has a negative terminal which is connected to the ground terminal of the voltage regulator 16, to one terminal of a push switch 20 and to the negative supply line of the microprocessor 22. The positive output of the voltage regulator 16 is connected to a first terminal of a resistor 18 and to the positive supply line of the microprocessor 22. The remaining terminal of the resistor 18 is connected to the remaining terminal of the switch 20 and to an input line to the microprocessor. The microprocessor will naturally possess, among others, address, data and clock lines although these are not shown in Figure 1. At switch-on an operator presses the push switch 12 and the voltage regulator 16 supplies a voltage to the microprocessor 22.The microprocessor 22 will commence a power up routine and when it is operational it will execute the appropriate software and provide a signal to close the switch 14 thus maintaining its supply of power. The circuit cannot be powered off except by the microprocessor opening the switch 14 or by the removal of the battery 10. If the user wishes to switch the circuit off he presses the switch 20 and this applies an off-request signal to the microprocessor which causes it to perform a power off routine which culminates in the opening of the switch 14.

This direct control of the power supply by the microprocessor has two main disadvantages. Firstly, as the circuit powers off, the voltage supplied to the microprocessor will fall over a finite time interval and a point will be reached when the output lines of the microprocessor will start to behave erratically due to the low supply voltage. At this point the switch 14 may be closed again by the erratic behaviour of the output line from the microprocessor which controls it and the circuit will re-enter a power-up routine. This can make it difficult or impossible to switch the circuit off. Secondly, certain microprocessors provide a delay at power on, which in the case of the Fujitsu MB89715 is 60 ms, in order to allow an external clock oscillator crystal to stabilise prior to an attempt to execute any software.During this period the microprocessor causes its output lines to float and thus it cannot provide the signal to close the switch 14. If the user releases the push switch 12 before the end of this period the circuit will power off.

It is an object of the present invention to provide a power supply arrangement which allows a reliable and smooth switch off to be obtained.

According to the present invention there is provided a power supply arrangement comprising a first input terminal and a second input terminal for connection to a power source, a first output terminal and a second output terminal for connection to a load, a connecting means coupled between the first input terminal and the first output terminal, a connecting means coupled between the second input terminal and the second output terminal, at least one of these connecting means being a switched connecting means which is also fed with a control signal and which is rendered conductive in response to a first state of the control signal and rendered non-conductive in response to a second state of the control signal, a low-output voltage detection means connected between the first and second output terminals which detection means compares the voltage between these terminals with a reference voltage and provides an indicator signal having at least a first state indicating that the voltage between the output terminals is greater than the reference voltage and a second state indicating that the voltage between the output terminals is less than the reference voltage, at least one off-request means for providing an off-request signal having at least a first state indicating that an off-request has been received and a second state indicating that no off-request has been received, a control means which accepts the indicator signal from the low-output voltage detection means and the off-request signal from the off-request means and which provides the control signal for the switched connecting means, whereby the control signal provided by the control means is in said second state in response to the off-request signal being in said first state thereby causing the voltage between the first and second output terminals to decrease causing the indicator signal from the low output voltage detection means to assume its second state.

In many cases the load circuitry to be switched by the arrangement will include a microprocessor and the off-request signal will be fed from a control line (be it active high or active low) provided by the microprocessor. Frequently a regulating means will be included after, or integrally with, the switch.

To switch the power supply arrangement on, an on-request means can be included in the arrangement which is operable to override the indicator signal from the low-output detection means. This can be achieved in a number of ways, for example by activating the switched connecting means directly, by disconnecting the indicator signal from the control means or by providing a temporary additional conductive path in parallel with the at least one switched connecting means. Switch-on could be initiated for example by a user pressing a switch or by remote control.

If it is desired to switch the arrangement on when a new battery is fitted, for example so that a piece of portable equipment can keep a record of its power reserves, this can be achieved by connecting a capacitor or other charge storage device between the output of the on-request means and an output of a means for providing a voltage which is substantially the same as an active signal on the on-request line. This means for providing a voltage must provide an output whenever the input terminals are supplied with a voltage and independently of the condition of the switched connecting means. Thus when a power source is removed from the input terminals the charge storage device discharges via leakage paths and provides a low impedance path from the output of the on-request means to an active level voltage when a power source is reconnected to the input terminals.If this charge storage device is capable of holding the on-request line active until the voltage at the output terminals attains regulation, the arrangement will switch on.

The present invention provides a power supply arrangement comprising input terminals for connection to a power source, a series regulator connected to the input terminals, the regulator having an output terminal for connection to a load, a capacitor connected to the input terminals and to means responsive to the capacitor being charged for inhibiting the operation of the regulator, first and second semiconductor switching devices having their conductive paths connected in series across the capacitor, a control electrode of the first switching device being connected to the output terminal of the regulator and to means for turning-off the regulator, a control electrode of the second switching device being connected to means for sensing that the regulator is losing regulation, whereby in operation the regulator is turned on by discharging the capacitor which is maintained discharged by the first and second switching devices being rendered conductive and is turned-off by rendering the first switching device non-conductive which enables the capacitor to charge causing the regulator to lose regulation and in so doing the regulator sensing means renders the second switching device non-conductive which inhibits discharging of the capacitor.

The present invention will now be explained and described, by way of example, with reference to Figure 2 of the accompanying drawings, wherein: Figure 2 shows an embodiment of a power supply arrangement made in accordance with the present invention.

In Figure 2 a battery 10 has a positive terminal connected to a first terminal of a resistor 30 and to an unregulated input terminal BAT of a series regulator 42. The regulator 42 is a National Semiconductors LP2951 which, in addition to the unregulated input terminal BAT, a regulated output terminal REG and a ground terminal GND, also possesses an output enable terminal HLD and an error terminal ERR. The HLD terminal acts as an input to an enabling means within the regulator, when this terminal is held at a low logic level the output of the regulator is enabled. The ERR terminal is an output of a low-output detection means within the regulator, when it is at a low logic level it signifies that the output of the regulator has lost regulation.The battery 10 has a negative terminal connected to a first terminal of a push switch 34, to a first electrode of a capacitor 36, to the drain electrode of an N-channel FET 40, to the ground terminal of the voltage regulator 42, to the ground terminal of a microprocessor 22, to the first terminal of a push switch 20 and to ground. The remaining terminal of the resistor 30, is connected to a first terminal of a resistor 32, to the remaining electrode of the capacitor 36, to the source electrode of an N-channel FET 38 and to the HLD terminal of the voltage regulator. The remaining terminal of the resistor 32 is connected to the remaining terminal of the push switch 34. The source electrode of the FET 40 is connected to the drain electrode of the FET 38.The gate electrode of the FET 38 is connected to an output terminal DIS of the microprocessor 22 and to a first terminal of a resistor 46. The gate electrode of the FET 40 is connected to the ERR terminal of the regulator 42 and to a first terminal of a resistor 44. The remaining terminals of the resistors 44 and 46 are connected to the REG output of the regulator 42, to a 5V input of the microprocessor 22 and to a first terminal of a resistor 18. The remaining terminal of the resistor 18 is connected to an active low input terminal OFF to the microprocessor and to the remaining terminal of the push switch 20.

When the circuit shown in Figure 2 is in a dormant off state the HID terminal of the regulator 42 is held at a high level by the resistor 30. The capacitor 36, which has a typical value of 68nF, is trickle charged to the full voltage of the battery 10 by means of the resistor 30. Leakage paths within and around this capacitor cause it to discharge within a few seconds if the trickle charging is stopped, for example by removal of the battery 10. The output terminal REG of the regulator is at a low level and the microprocessor 22 is switched off. Since the output REG is low the error terminal ERR is low and so the FET 40 is non-conductive, the output terminal DIS of the microprocessor is low and so the gate electrode of the FET 38 is also low and this device is non-conductive.

To switch the arrangement on, in other words to apply power to the microprocessor 22, an operator presses the push switch 34 which has the effect of holding the HLD terminal of the regulator at a low potential and of discharging the capacitor 36 via the resistor 32. The regulator 42 thus starts to switch on although the output REG takes a finite time (about lms) to attain regulation. Once REG achieves regulation the ERR signal goes to a high logic level which supplies a signal to the gate electrode of the FET 40 and enables this FET to conduct. As REG has gone high the gate electrode of the FET 38 is held high via the resistor 46 and so this FET is also enabled to conduct. The microprocessor 22 now has a power supply and so enters its power up routine.As stated previously there can be a switch-on delay of 60ms or more for certain microprocessors before execution of programmed instructions can take place.

Once the switch-on is complete the microprocessor output lines become active and it has control of the DIS terminal. Being of a lower impedance than the resistor 46, the DIS terminal now has control of the gate electrode of the FET 38 and DIS is then held high by the microprocessor and the FET 38 is maintained in a conductive state. The two FETs 38,40 being conductive maintain the HLD terminal of the regulator at a low level which maintains the operation of the regulator.

To switch the arrangement off the operator presses the push switch 20 which, in combination with the resistor 18 provides an active low off-request signal OFF to the microprocessor. A power off routine is then entered by the microprocessor and it should be noted that this routine could be initiated in a number of other ways for example by remote control or due to a failing battery voltage. The microprocessor makes the DIS line low and this turns the FET 38 off which causes the HLD terminal of the regulator to be high, or disabled. The capacitor 36 is charged via the resistor 30. The output terminal REG of the regulator 42 starts to fall and as this output loses regulation the ERR terminal goes to a low logic level which inhibits the conduction of the FET 40. As the voltage REG continues to fall the microprocessor output terminals start to behave erratically and may cause the FET 38 to conduct.

Unlike the circuit shown in Figure 1 however this cannot result in the arrangement re-powering itself since the FET 40 is held firmly non-conductive by the low ERR signal.

There is one additional feature provided by this illustrated power supply arrangement which is an automatic power-on with the fitting of a new battery 10. If the battery 10 is removed, the capacitor 36 discharges via leakage paths and so when a new battery is fitted the discharged capacitor holds the HLD terminal of the regulator low for an instant. Before the capacitor can charge appreciably via the resistor 30, the regulator 42 is switched on and attains regulation, the FETs 38 and 40 are conductive and the power-on procedure described above ensues. The resistor 30 must therefore have a high enough value to prevent the capacitor 36 from charging too quickly. By contrast the resistor 32 should have a very low value to ensure a swift discharge of the capacitor 36 when the push switch 34 is pressed.However this resistor must have a value which is high enough to avoid damage to the capacitor during such a swift discharge. The microprocessor receives a power supply and once it is operational can make a check on the battery voltage and/or reset a counter (not shown). This feature can be valuable to portable equipment which must keep an up to date record of the energy remaining in its batteries. If this feature is not required then the capacitor 36 can be omitted.

The FETs 38,40 used in this embodiment of the present invention can have alternative solid state switching devices substituted for them provided that any necessary changes in the drive circuitry are implemented and they could also be replaced by a two input NAND gate whose inputs are fed from the lines ERR and DIS and whose output is connected to the line HLD. To function correctly this NAND gate would have to receive its power supply from the unswitched voltage of the battery.

The power supply arrangement could be used for circuitry which does not include a microprocessor, for example the OFF line could be connected directly to the DIS line with a capacitor connected across the switch 20. In a similar manner as the capacitor 36 is used for switch on, the capacitor connected across the switch 20 would maintain the gate electrode of the FET 38 at a low level until the FET 40 is switched off due to a low ERR signal from the regulator 42. This arrangement would provide a smooth off control.

From reading the present disclosure, other variations will be apparent to persons skilled in the art. Such variations may involve other features which are already known in the design, manufacture and use of power supply arrangements and component parts thereof and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims (12)

1. A power supply arrangement comprising a first input terminal and a second input terminal for connection to a power source, a first output terminal and a second output terminal for connection to a load, a connecting means coupled between the first input terminal and the first output terminal, a connecting means coupled between the second input terminal and the second output terminal, at least one of these connecting means being a switched connecting means which is also fed with a control signal and which is rendered conductive in response to a first state of the control signal and rendered non-conductive in response to a second state of the control signal, a low-output voltage detection means connected between the first and second output terminals which detection means compares the voltage between these terminals with a reference voltage and provides an indicator signal having at least a first state indicating that the voltage between the output terminals is greater than the reference voltage and a second state indicating that the voltage between the output terminals is less than the reference voltage, at least one off-request means for providing an off-request signal having at least a first state indicating that an off-request has been received and a second state indicating that no off-request has been received, a control means which accepts the indicator signal from the low-output voltage detection means and the off-request signal from the off-request means and which provides the control signal for the switched connecting means, whereby the control signal provided by the control means is in said second state in response to the off-request signal being in said first state thereby causing the voltage between the first and second output terminals to decrease causing the indicator signal from the low output voltage detection means to assume its second state.

2. An arrangement as claimed in Claim 1, further comprising a voltage regulating means coupled between said first input terminal and said first output terminal.

3. An arrangement as claimed in Claim 1 or Claim 2, further comprising an on-request means for providing an on-request output signal at a first voltage level corresponding to an active state and a second voltage level corresponding to an inactive state, said on-request signal being coupled to the control means.

4. An arrangement as claimed in Claim 3, wherein the control means is operative to provide an output to the switched connecting means in response to an on-request signal from the on-request means at the first said voltage level regardless of the state of the indicator signal from the low-output detection means.

5. An arrangement as claimed in Claim 3 or Claim 4, wherein said on-request means provides an on-request signal at the first said voltage level in response to a user input.

6. An arrangement as claimed in Claim 3, Claim 4 or Claim 5, wherein the power source comprises a battery connected to the first and second input terminals and wherein a charge storage device is connected to the on-request means, said charge storage device being discharged when the on-request output signal is at the first voltage level thereby providing a control signal in said first state.

7. An arrangement as claimed in Claim 6, further comprising means for charging the charge storage device from said battery when the on-request output signal is at the second voltage level.

8. An arrangement as claimed in any one of Claims 2 to 7, wherein said voltage regulating means incorporates said switched connecting means and said low-output detection means.

9. An arrangement as claimed in any one of the Claims 1 to 8, wherein the power supply for said off-request means is coupled to the first and second output terminals.

10. An arrangement as claimed in any one of Claim 1 to 8, wherein the load includes a microprocessor which incorporates the off-request means and provides the off-request signal.

11. A power supply arrangement comprising input terminals for connection to a power source, a series regulator connected to the input terminals, the regulator having an output terminal for connection to a load, a capacitor connected to the input terminals and to means responsive to the capacitor being charged for inhibiting the operation of the regulator, first and second semiconductor switching devices having their conductive paths connected in series across the capacitor, a control electrode of the first switching device being connected to the output terminal of the regulator and to means for turning-off the regulator, a control electrode of the second switching device being connected to means for sensing that the regulator is losing regulation, whereby in operation the regulator is turned on by discharging the capacitor which is maintained discharged by the first and second switching devices being rendered conductive and is turned-off by rendering the first switching device non-conductive which enables the capacitor to charge causing the regulator to lose regulation and in so doing the regulator sensing means renders the second switching device non-conductive which inhibits discharging of the capacitor.

12. A power supply arrangement constructed and arranged to operate substantially as hereinbefore described with reference to and as shown in Figure 2 of the accompanying drawings.