GB2245394A - Video framestore selective addressing system - Google Patents

Abstract

A frame of video image data is stored in a memory 2 and is addressed by an address counter 4. The address counter is responsive to clock pulses supplied thereto to count incrementally through addresses in the memory. An access controller 8 supplies control signals comprising at least a start address and a run-length to the address counter, the run- length being dependent on the number of addresses through which the address counter is to count. Controllers 10, 6 are provided for writing data to and reading data from memory locations addressed by the address counter. <IMAGE>

Description

VIDEO FRAMESTORE A#SS Field of the Invention This invention relates to addressing circuitry for accessing data stored in a memDry and in particular to the real-time manipulation of digital video data transfer to and from a dedicated rnarcry or "framestore".

BackqnvunS of the Invention Dedicated memories for storing video image data are well knawn. They are commonly referred to as "framestores".

One type of framestore is arranged such that it has either fixed or partially adjustable addressing schemes where there is a set correspondence between the address of a pixel in the framestore memory and its position on the screen these have very little flexibility in terms of outputting particular areas of the framestore and at most they have the ability to swap between areas of the framestore thereby moving a "window" to view a portion of the total image in the framestore.

Other types of framestore are known which implement oomplicated schemes whereby image transformations can be implemented from a knowledge of the location of every pixel in the framestore. The individual pixels can be mapped to different locations in the output frame using appropriate transformations.

It will be appreciated that special effects such as zooms, vertical and horizontal flips, and oompressions of the image in the framestore can be acheived using the latter of the two types of framestore but the individaal mapping of each pixel makes these operations complex.

Summary of the Invention The present invention provides a memDry means for storing a frame of video image data having addressing circuitry such that strings of pixels are selectively addressable. This enables blocks of picture data to be read in and out of the memory means or framestore in any desired order. In a preferred embodiment a specific address including line number and pixel number is given to each pixel of the framestore and a read or a write is initiated at a start line and start pixel address. The line and pixel addresses are then incremented or deeremented in a predetermined manner to write in or read out pixel data. Preferably the ability to skip pixel addresses is also included by varying the incremental and decremental step lengths.

De#aiied Description of the Preferred Embodiment The invention will now be described in detail by way of example with reference to the drawings in which: Figure 1 shows a block diagram of a framestore and its associated accessing circuitry embodying the invention; Figure 2 shows a block diagram of an address counter for use in the circuitry of figure 1; and Figures 2 to 8 show various transformations which can be performed on data when writing into or reading from a framestore.

The circuitry of figure 1 shows a framestore memory 2 the addressing of which for reading and writing to and from the memory is controlled by an address counter 4. Data can be read fran the framestore memory 2 via a read video data controller 6 which also receives a data control signal from a video access controller 8. The read video data controller 6 has an output compatible with a display for the video data stored in the framestore.

The video access controller also has a further data controller output coupled to a write video data controller 10. This has a plurality of data inputs 12 and an output coupled to the framestore memory.

The video access controller supplies a video run start address and other address counter control signals to the address counter 4. These are then used by the address counter to access particular portions of the frarnestore memory such that data may be written in or read out in any desired order. The video access controller produces the video run start address and the address counter control signals in response to coarnands loaded into it from a video segment command memory 14. The selection of video segment commands takes place under the control of a user preferably via same form of electronic controller such as a micro computer.

The video segment commands comprise specific information oonoerning the manner of addressing of the framestore memory 2 such as start address, zoom factor, direction of address counting, and the run length or number of pixels to be addressed. When a video segment command is executed by the video access controller 8 the video run start address is supplied to the address counter 4 along with various address counter control signals such as the run length and the direction of counting.At the same time data control signals are supplied by the video access controller to either the write video data controller 10 or the read data controller 6 in accordance with whether a write to or a read from the framestore zn#tcry 2 is to be performed. The ewrite or the read starts from the start address supplied by the video access controller and is either incremented or decremented for the number of pixel addresses specified in the run length in the and Y directions in the framestore.Whilst this is taking place the next video segment command is loaded into the video access controller ready to supply a start address and the address counter control signals for the next frame of data to be written to or read from the framestore memory 2. In this manner flexible, prcgrammable, contiguous access to any section of the framestore memory is achieved.

The control signals supplied by the video access controller 8 to the write video data controller 10 and the read video data controller 6 are used to synchronise input and output data with the sequence of framestore addresses supplied by the address counter 4.

A block diagram of the address counter 4 is shown in figure 2 and this oowprises a pixel counter 16, a line counter 18, a run length decoder 20, and a pixel/line increment selector switch 22.

The video run start address is supplied to the address counter 4 in the form of a pixel start address and a line start address which comprise inputs to the pixel counter 16 and the line counter 18 respectively. The eaddress counter control signals comprise a pixel increment which can be set to any desired miter such that the pixel counter can be configured to count in incremental steps of, for example 1, 2, 3, 4, 5 or more pixels. There is also a pixel increment direction signal which determines whether addresses should be incremented or decremented from the pixel start address. The line counter 18 receives corresponding line increment and line increment direction signals.There is a run-length signal which comprises an input to the run-length decoder 20 which has a pixel run-length output and a line run-length output which are cooped to further inputs of the pixel counter 16 and the line counter 18 respectively. The remaining signal is a pixel line increment selection signal which controls the selector switch 22 to supply a clock (CALK) signal to either the pixel counter 16 or the line counter 18. The eoutputs of the pixel counter 16 and the line counter 18 oomprise the framestore address for framestore memory 2.

In operation a pixel start address and line start address are supplied by the video access controller in response to a video segment oatrnand and are loaded into the pixel counter and the line counter. The pixel increment, pixel increment direction, and pixel run-length are also loaded into the pixel counter 16 whilst the line increment the line increment direction, and the line run-length are loaded into the line counter.

Assuming that addressing is to take place on a line by line basis the pixel/line increment selection signal controls the switch 22 to supply the clock signal to the pixel counter 16 initially. The epixel counter 16 will provide addresses along the first line of the block of memory to be addressed in steps determined by the pixel increment and a direction determined by the pixel increment direction for the run-length supplied by the run-length decoder 20. When the pixel counter 16 has counted through this run length the switch 22 will be controlled to supply the clock signal to the line counter so that the address supplied thereby can be incremented in accordance with the line increment and in the specified line increment direction.

Mbenwhile the pixel counter having clocked through its specified run-length resets to the pixel start address. After a single increment of the line counter the switch 22 is controlled to again supply clock pulses to the pixel counter so that a second line of pixels in the framestore memory 2 are addressed.

This process continues until both the pixel run-length and the line run-length have reached their ends.

Clearly there is no requirement for the pixel counter to always operate in preference to the line counter and their order of operation could be reversed such that vertical lines of memory in the framestore are addressed.

Using the addressing scheme shown in figures 1 and 2 enables arbitrary user alterable control of video data into and out of the framestore memory 2. In a preferred embodiment separate video access controllers are used for controlling reads from and writes to the framestore memory 2 although this is not shown in figure 1. The use of the pixel and line increment signals enables pixel skipping to be performed during writing to framestore memDry and pixel duplication during reading from framestore memory. This provides scope for effects such as image compresses and expands and these will be controlled by the video access controller in response to an appropriate video segment command.

The e remaining figures show examples of the type of effects which can be performed when using the arrangsment of figure 1.

Figure 3 shows a simple output of a full screen of video data.

This will involve the pixel start address and line start address being set to the top left of the framestore memory and being incremented sequentially across and down the screen.

The e pixel and line increments will both be set to one in this case.

Figure 4 shows a duplication of the lines in the top half of the framestore memory into the bottom half of an output video frame. In the example of figure 4 the video access controller would first supply signals to read the top half of the framestore memory into the top half of the output video frame and then supply signals to read the top half of the framestore memory into the bottom half of the output video frame.

In figure 4 an output expand, i.e. a zoom, is shown this is achieved by either reading each line twice and doubling the horizontal length of each line by pixel duplication or by setting the pixel increment and the line increment to be greater than one and then having some form of interpolation performed on the output video data to provide a full screen of video.

Figure 6 shows an input compression of video data achieved by skipping pixels under the control of the pixel and line increments thereby reducing the vertical and horizontal size of the input video frame. If a straight output of the framestore memory is performed as illustrated the input video frame will appear as a small rectangle in the top left hand corner of the output video display.

Figure 7 shows a horizontal flip of data stored in the framestore memory which is achieved by reversing the pixel increment direction. A corresponding vertical flip is shown in figure 8 and this is achieved by reversing the line increment direction.

Various ones of these effects can be combined. For example, the caS5ination of an input oompression with an output expand results in a mosaic effect on the displayed output. The codbination of a horizontal and vertical flip results in 1800 rotation. If a plurality of video sources are coupled to the write video data controller and are read into the framestore memory 2 under coOpression then a plurality of windows of video displays from each source can be stored in the memory.

It will be appreciated that this type of run length encoded addressing of the framestore memory gives considerable advantages over the prior art framestore addresses where the type of effects illustrated here require individual mapping of each piral location to a new location.

Claims (14)

1. A memory means for storing a frame of video image data having addressing circuitry oomprising, an address counter responsive to clock pulses supplied thereto to count incrementally through addresses in the memory means, the address oounter receiving at least a start address and a run-length from a control means, the run-length being dependent on the number of addresses through which the address counter is to count, and means for writing data to and reading data from memory locations addressed by the address counter.

2. A memory means according to claim 1 in which the address counter comprises first means for counting through addresses in a first direction along lines of memory locations, and second means for counting in a second direction across lines of memory lcoations.

3. A memory means according to claim 1 or 2 in which the address counter is responsive to a control signal supplied by the control means to set the incremental step length between addresses.

4. A memory means according to claim 2 in which both counting means are responsive to control signals supplied by the control means to set the incremental step lengths in the first and second directions independently.

5. A memory means according to claim 1 in which the address counter is responsive to control signals supplied by the control means to reverse the direction in which the address counter counts.

6. A memDry means according to claim 2 in which both counting means are responsive to control signals supplied by the control means to reverse the directions in which they count ifld#e#y.

7. A memory means according to claim 2 in which the address counter includes selecting mEans responsive to a control signal supplied by the control means to selectively apply clock signals to the first and second counting means.

8. A memory means according claim 1 in which the means for writing data to the memory means has a plurality of inputs coupled to different sources of image data.

9. A memory means according to claim 1 in which the means for reading data from the memory means has an output coupled to a display means.

10. Addressing circuitry according to claim 1 in which the control means is responsive to user selected caarmands to supply at least the start address and the run-length to the address counter.

11. A memory means for storing a frame of video image data having addressing circuitry substantially as herein described with reference to the figures.

12. A method for addressing a memory means for storing a frame of video image data comprising the steps of allocating a start address and a run-length and incrementally counting through memory locations in the memory means, the first location being determined by the start address and the number of locations addressed being dependent on the run-length.

13. A method for addressing a frame of video image data stored in a memory means substantially as herein described.

14. A memory means for storing a frame of video image data having addressing circuitry comprising means for selectively addressing strings of memory locations in the memory means.