GB2243468A

GB2243468A - IC card

Info

Publication number: GB2243468A
Application number: GB9018318A
Authority: GB
Inventors: Hisashi Ohno; Kazuo Asami
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1990-04-20
Filing date: 1990-08-21
Publication date: 1991-10-30
Anticipated expiration: 2010-08-21
Also published as: GB2243468B; FR2661269A1; GB9018318D0; JPH043282A; FR2661269B1; JP2527251B2

Abstract

An IC card includes a CPU 11 for processing data, a data receiving circuit 12 for receiving data from the outside and inputting it to the CPU, a data transmitting circuit 13 for transmitting data from the CPU to the outside, a reset receiving device 17 for receiving an external reset signal from the outside, a monitor timer 18 for generating an internal reset signal when there is no next response, even if a prescribed time has elapsed after the data receiving circuit has received a response from the outside, and a discrimination circuit 16 for discriminating which signal is input when either one of an external reset signal from the reset receiving device or an internal reset signal from the monitor timer is input, holding the discrimination result, and resetting the CPU. The aim is to provide a card in which the cause of a reset may be more readily determined. <IMAGE>

Description

IC CARD BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an IC card and, in particular, to an IC card having a monitor timer.

Descriotion of the Related Art The structure of a conventional IC card is shown in Fig. 4. A stop signal output circuit 2 is connected to a CPU 1. A reset receiving circuit 3 and a monitor timer 4 are connected to the stop signal output circuit 3. In addition, this IC card has a data receiving circuit and a data transmitting circuit (not shown) connected to the CPU 1 for respectively receiving and transmitting data between this card and a terminal device (not shown).

In operation, after data from the terminal device is received in the data receiving circuit, it is input to the CPU 1 where a prescribed process is performed.

Subsequently, transmission data is transmitted to the terminal device from the data transmitting circuit as required.

Now suppose that a certain failure occurs in an IC card system which includes the terminal device and the IC card and an external reset signal is issued from the terminal device#in order-to stop the CPU 1. when this external reset signal is received by the reset receiving circuit 3 of the IC card, a reset signal S1 is output to the stop signal output circuit 2 from the reset receiving circuit 3. The stop signal output circuit 2 then outputs a stop signal S3 to the CPU 1, causing the CPU 1 to be reset.

The monitor timer 4 connected to the stop signal output circuit 2 measures the time up to the next response after the reception of a response of data transmission or the like from the terminal device. This monitor timer 4 overflows when there is no next response from the terminal device even if a preset time has elapsed, then it outputs a reset signal S2 to the stop signal output circuit 2 to stop the CPU 1.

The stop signal output circuit 2 that has received the reset signal S2 from the monitor timer 4 outputs the stop signal S3 to the CPU 1 in the same manner as when it receives the reset signal S1 from the reset receiving circuit 3. As a result, the CPU 1 enters the stopped state.

Since the stop signal output circuit 2 outputs a stop signal S3 like this both when it receives the reset signal S1 from the reset receiving circuit 3 and when it receives the reset signal S2 from the monitor timer 4, it cannot be determined which reset signal has caused the CPU 1 to be reset.

That is, it is difficult in the conventional IC card to analyze whether, when a failure occurs and the CPU 1 is reset, this reset is caused by the reception of an external reset signal from the terminal device, or by the operation of the monitor timer 4, or whether noise is mixed in and a reset signal is erroneously received in the reset receiving circuit 3. As a result, there exists a problem in that the work to recover to a normal state takes a great deal of time and effort.

SUMMARY OF THE INVENTION The present invention has been devised to solve the above-mentioned problems. Accordingly, an object of the present invention is to provide an IC card in which the cause of a failure can easily be analyzed when a CPU is reset due to the failure.

The IC card of the present invention comprises a CPU for processing data, a data receiving circuit for receiving data from the outside and inputting it to the CPU, a data transmitting circuit for transmitting data from the CPU to the outside, a reset receiving means for receiving an external reset signal from the outside, a monitor timer for generating an internal reset signal when there is no next response even if a prescribed time has elapsed after the data receiving circuit has received a response from the outside, and a discrimination circuit for discriminating which signal is input'when either an external reset signal from the reset receiving means or an internal reset signal from the monitor timer is input, holding the discrimination result, and resetting the CPU.

In the present invention, when the discrimination circuit receives an external reset signal from the reset receiving means or an internal reset signal from the monitor timer, it discriminates which signal it is, holds the discrimination result, and resets the CPU.

These and other objects, features and advantages of the present invention will become clear in the following description of the preferred embodiments of the present invention, together with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram illustrating an IC card in one embodiment of the present invention; Fig. 2 is a circuit diagram illustrating the internal structure of a discrimination circuit in the embodiment; Fig. 3 is a block diagram illustrating another embodiment; and Fig. 4 is a block diagram illustrating a conventional IC card.

- DESCRIPTIONe O~ THE PREFERRED EMBODIMENTS Embodiments of the present invention will be explained hereinunder with reference to the accompanying drawings.

In Fig. 1, the IC card has a CPU 11, to which a data receiving circuit 12 and a data transmitting circuit 13 for respectively receiving and transmitting data between this card and a terminal device (not shown) are connected. A memory 15 is connected to the CPU 11 via a data bus 14, and a discrimination circuit 16 is connected to the CPU 11 and the data bus 14. In addition, a reset receiving circuit 17 and a monitor timer 18 are connected to the discrimination circuit 16.

The reset receiving circuit 17 is to receive an external reset signal S4 from the terminal device and output it to the discrimination circuit 16. The monitor timer 18 measures the time up to the next response after the reception of a response of data transmission or the like from the terminal device and outputs an internal reset signal Ss to the discrimination circuit 16 when there is no next response from the terminal device even if a prescribed time has elapsed.When the discrimination circuit 16 receives an external reset signal S4 from the reset receiving circuit 17 or an internal reset signal Sg from the monitor timer 18, it outputs a stop signal S6 to the CPU 11 and discriminates which signal of either the external reset signal4 or the inteRnal reset signal S5 it is.

Fig. 2 shows the internal structure of the discrimination circuit 16. The discrimination circuit 16 comprises NOR circuits 21 to 23 and an inverter circuit 24.

The first NOR circuit 21 receives an external reset signal S4 from the reset receiving circuit 17 and an output signal from the second NOR circuit 22. The second NOR circuit 22 receives an internal reset signal S5 from the monitor timer 18 and the output signal of the first NOR circuit 21. The third NOR circuit 23 receives an external reset signal S4 and an internal reset signal Ss. The inverter circuit 24 is connected to the output end of the second NOR circuit 22 and the output end of this inverter circuit 24 is connected to a "0" bit line of the data bus 14. When an discrimination circuit read signal S8 is input-to the inverter circuit 24, the level of the output end of the second NOR circuit 22 is reversed and then output to the data bus 14 as a discrimination signal S7. The output signal of the third NOR circuit 23 is input to the CPU 11 as a stop signal Sg.

The IC card of Fig. 1 sends data to and receives data from the terminal device using electromagnetic waves. The data receiving circuit 12, the data transmitting circuit 13 and the reset receiving circuit 17 each have an antenna circuit. Also, these circuits 12, 13 and 17 may instead have one antenna circuit in common.

Next, the operatfon of the embodiment will be explained. First, when data is transmitted from the unillustrated terminal device, this data is received in the data receiving circuit 12, then it is input to the CPU 11 where a prescribed processing is performed. Next, data which has been processed by the CPU 11 is stored in the memory 15 via the data bus 14 as required or transmitted to the terminal device from the data transmitting circuit 13.

Now suppose that an external reset signal is issued from the terminal device. When this external reset signal is received by the reset receiving circuit 17 of the IC card, a reset signal S4 of "H" level is output to the discrimination circuit 16 from the reset receiving circuit 17. Then, since the output of the first NOR circuit 21 is turned to "L" level in Fig. 2, the output of the second NOR circuit 22 becomes to "H" level and is input to the inverter circuit 24. On the other hand, the output of the third NOR circuit 23 is turned to "L" level and input to the CPU 11 as a stop signal Sg, causing the CPU 11 to be reset.

Next, in order to recognize the discrimination result, the CPU 11 is activated again to specify a specific address and to output a discrimination circuit read signal Sg to the inverter circuit 24 of the discrimination circuit 16. Then, the output of the second NOR circuit 22 is reversed to "L" level and is output to the "0" bit line of the data bus 14.

Therefore, by reading'the level of the "0" bit line of this specific address data, it can be recognized that, because it is at "L" level, the reset is caused by the external reset signal S4.

On the other hand, when the monitor timer 18 overflows because there is no next response from the terminal device even when a prescribed time has elapsed after the reception of a response of data transmission or the like from the terminal device, the monitor timer 18 outputs the internal reset signal S5 of "H" level to the discrimination circuit 16 in order to stop the CPU 11. Then, the output of the second NOR circuit 22 is turned to "b" level and is input to the inverter circuit 24. On the other hand, the output of the third NOR circuit 23 becomes to "L" level in the same manner as when the above-mentioned reset signal S4 of "H" level is input, and is input to the CPU 11 as a stop signal S6, which causes the CPU 11 to be reset.

Next, the CPU 11 is activated again to recognize the discrimination result, and the above-mentioned specific address is specified and the discrimination circuit read signal Sg is output to the inverter circuit 24 of the discrimination circuit 16 from the CPU 11. Then, the output of the second NOR circuit 22 is reversed to "H" level and is output to the "0" bit line of the data bus 14 as a discrimination signal S7. Thus, by reading the level of the "0" bit line of this specific address data, it can be recognized that the reset is caused by the internal reset signal Ss because the level of the "0" bit line is at "H".

As mentioned above, in this embodiment, when the discrimination circuit 16 receives either one of the external reset signal S4 or the internal reset signal Ss, it discriminates which signal it has received and holds the discrimination result as the level of the output signal of the second NOR circuit 22. In addition, the discrimination result can be read via the inverter circuit 24 by using the discrimination circuit read signal Sg. That is, in a case where a failure occurs and the CPU 11 is reset, it can easily be determined whether this reset is caused by the reception of an external reset signal from the terminal device or by the operation of the monitor timer 18.

Therefore, the work to remove the cause of a failure and to return to a normal state is easy and speedy.

The IC card of Fig. 1 is a non-contact type IC card using electromagnetic waves. It may be a contact type IC card using a connector 31, as shown in Fig. 3. The CPU 11 is connected to the connector 31 via a data input circuit 32 and a data output circuit 33. The data input circuit 32 and the data output circuit 33 correspond to the data receiving circuit 12 and the data transmitting circuit 13 of Fig. 1 respectively. Because this contact type card inputs data from and outputs data'to a terminal device (not shown) via the connector 31, an antenna circuit is not required and therefore the circuits 32 and 33 have no antenna circuit.

The connector 31 has an external reset signal input terminal 31a connected to the discrimination circuit 16. The contact type IC card designed as described above has advantages similar to the non-contact type IC card of Fig. 1. In this case, an external reset signal S4 is directly input to the discrimination circuit 16 from the terminal device via the input terminal 31a of the connector 31.

Many widely different embodiments of the present invention can be made without departing from the spirit and scope thereof, therefore it is to be understood that this invention is not limited to the specific embodiments thereof except as defined in the appended claims.

Claims

CLAIMS-

1. An IC card, comprising: a CPU for processing data; a data receiving circuit for receiving data from the outside and inputting it to said CPU; a data transmitting circuit for transmitting data from said CPU to the outside; a reset receiving means for receiving an external reset signal from the outside; a monitor timer for generating an internal reset signal when there is no next response, even if a prescribed time has elapsed after said data receiving circuit has received a response from the outside; and a discrimination circuit for discriminating which signal is input when either one of an external reset signal from said reset receiving means or an internal reset signal rom said monitor timer is input, holding the discrimination result, and resetting said CPU.

2. An IC card according to claim 1, further comprising: a memory for storing data; and a data bus for connecting said CPU to said memory.

3. An IC card according to claim 2, wherein said discrimination circuit outputs said discrimination result to said data bus.

4. An IC card according to Claim 3, wherein said discrimination circuit incudes a first NOR circuit, a second NOR circuit which inputs the output of said monitor timer and the output of said first NOR circuit, a third NOR circuit which inputs the output of said monitor timer and the output of said reset receiving means, and an inverter circuit which inputs the output of said second NOR circuit, said first NOR circuit accepting the output of said reset receiving means and the ouput of said second NOR circuit, the output of said third NOR circuit being connected to said CPU, and the output of said inverter circuit being connected to said data bus.

5. An IC card according to any preceeding claim, wherein said reset receiving means is a reset receiving circuit for receiving an external reset signal transmitted from the outside in a form of an electromagnetic wave.

6. An IC card according to any preceeding claim, further comrprising a connector for obtaining an electrical contact with the outside, said reset receiving means including one terminal of said connector for receiving said external reset signal.

7.- An IC card, substantially as herein described with reference to Figures 1 and 2 or Figure 3 of the accompanying drawings.