GB2229344A

GB2229344A - Converter circuit for video adaptor of computer

Info

Publication number: GB2229344A
Application number: GB8823628A
Authority: GB
Inventors: Anthony John Matthews
Original assignee: Research Machines PLC
Current assignee: Research Machines PLC
Priority date: 1988-10-07
Filing date: 1988-10-07
Publication date: 1990-09-19
Anticipated expiration: 2008-10-07
Also published as: EP0363204A3; EP0363204B1; DE68925775D1; DE68925775T2; EP0363204A2; GB8823628D0; GB2229344B

Description

1.

GENERAT ION OF RASTER SCAN VIDEO SIGNALS FCR AN ENHANCED RESCUTION MONICR This invention relates to the generation of raster scan video signals for an enhanced resolution monitcr in either a high resolution mode c.r a lew resolution mode.

The increasing power of personal computers has led to an interest in providing higher resolution dislay systems, particularly suited to windowing environments, computer aided design and engineering, spread sheets and desk top publishing.

1 In the past, this area has been catered for by specialised display adaptors typically containing circuitrv such as a dedicated video memory to contain the enhanced resolution image and a dedicated video timing signal generatcr as well as dedicted logic for interfacing the adaptor to the systems bus ci the personal computer.

There is also often the requirement to provide compatibility with the native video modes of the personal computer. In the past, this has been achieved by means of a dedicated circuit providing limited capabilities for the display of a normal personal computer video mode on an enhanced resolution monitor or a second display adaptor and monitor to provide compatibility independent from the enhanced resolution display system.

In small computers and data processors, it is particularly important to reduce the complexity and expense of the hardware required to perform such functions and this invention aims to reduce or eliminate the need for the additional expensive circuitry described above and, in one particular arrangement, to provide a plug-in convertor circuit to podify a normal, industry standard video adaptor to operate In accordance with the invention.

According to a first aspect of the Invention, there is provided a converter circuit for connection to a video adaptor of a computer to provide for the generation of a raster scan video signal to an enhanced resolution monitor in either a first, high resolution mode or a second, low resolution mode, the converter circuit comprising: a video timing generator for connecting to - 'I - r_ receive timing signals from the video adaptor; a multiplexer for connecting to receive a video output signal from the video adaptor; a video 'Line bufter for connecting to receive the video output signal from the videc, adaptor and connected to the multiplexer; and output means connected to receive a video output signal from the multiplexer for providing a video output signal to an enhanced resolution monitor, the converter circuit being selectively operable in a first mode in which video information from the video adapter is converted by the multiplexer for a high resolution, monochrome display and then provided to the output means, and a second mode in which video information for a low resolution, multicolour display is received by the multiplexer from the video controller via the buffer such that each pixel of information is read out twice from the bu,fer and each line of information is read out twice to provide the output means with a video output signal of a low resolution display to be produced on an enhanced resolution monitor.

According to a second aspect of the invention, there is provided a videc adaptor for a computer for providing a raster scan video signal to anenhanced resolution monitor in either a first, high resolution rode or a second, low resolution mode, the video adaptor comprising: a video controller for connecting to a system bus of a computer; a video memory connected to the video controller; a video timing generator connected to receive timing signals from the video controller; a multiplexer connected to receive a video output signal from the video controller; a video line buffer connected to receive the video output signal from the video controller 'and connected to the multiplexer; and output means connected to receive a video output signal from the multiplexer for providing a video output signal to an enhanced resolution monitor, the video adaptor being selectively operable in a first mode in which video information from the video controller is converted by the multiplexer for a high resolution, monochrome display end then provided to the output means, and a second mode in which video Information for a low resolution, multicolour display is received by the multiplexer from the video controller via the buffer such that each pixel of Information is reed out twice from the buffer and each line of information is read out twice to provide the output means with a video output signal of a low resolution display to be produced on an enhanced resolution monitor.

According to a third aspect of the invention, there is provided a computer having the facility for providing a raster scan video signal to an enhancea resolution monitor in either a first, high resolution mode or a seconj, low resolution mode, the computer having a processor responsive to a display request to provide instructions on a system bus to a video adaptor, the video adaptor comprising: a video controller connected to the system bus; a video memory connected to the video controller; a video timing generator connected to receive timing signals from the video controller; a multiplexer connected to receive a video output signal from the video controller; a video line buffer connected to receive the video output signal from the video controller and connected to the multiplexer, and output means connected to receive a video output signal from the multiplexer for provid:Lr,Lz a video output siRnal to an enhanced resolution monitor, the video ada-,tc,r be.n-z selective!v oDerable in response to instructions received on the system bus in a first mode in which video information from the video controller is converted by the multiplexer for a high resolution, monochrome cisplay and then Droviced to the output means, and a second mode Ln. wnlc!l video -t:,-i,,"ormation for a low resolution, multi-colour display is received by the multiDlexer from the video controller via the buffer such that each pixel of information is read out twice from the buffer and each line of information is read out twice to provide the output means with a video output signal of a low resolution display to be produced on an enhanced resolution monitor.

According to a fourth aspect of the invention, there is provided a method of providing a raster scan video signal from a video adaptor of a computer to an enhanced resolution monitor in either a first, high resolution mode or a second, low resolution mode, the method comprising the steps of: in the first mode, routing video information from the video adaptQr for conversion by a multiplexer for a high resolution, monochrome display and then to output means connected to a high resolution monitor and, in the second mode, passing video information for a low resolution, multi-colour display to a buffer and then reading this into the multiplexer, under the control of a video timing generator connected to receive timing signals from the video adaptor, such that each pixel of information is reed out twice and each line of information is reed out twice so as to provide the output means with a 1X f 1. - video output signal of a low resolution display to be produced on an enhanced resolution monitor.

Preferred features of the invention will. be a,.oarent frcra the following t. description and from the subsidiary claims of the specification.

The' invention will new be destribed, merely by way of example, with reference to the accompanying drawings, in which:

FiRure 1 is a block diagram for explaining the function of an embodiment of the invention; FiE n r ure 2 is a schematic crcuit ciaRram of parts of the system E; l_n Figure 1; ana Figure 3 is an assembler lisr-ting of the content: of one of the components shown in the Figures 1 and -9.

Fijzure 1 snows a block diagram of a conventlonal video adaptor 1 mountee on a mother board and connected to a systems bus 2 of a personal computer (PC). The systems bus 2 carries address, cata and control signals and is used by the PC to communicate with input/output G/0) devices such as the video adaDtor 1. The video adaptor 1 is used to provide the primary point for communication of output information to the human operator.

X A plug-in convertor circuit 3 mounted on a daughter card is connected to the video adaptor 1. As will be described below, this provides for the generation of a raster scan video signal to an enhanced resolution monitor (not shown) in either a first, high resolution mode such as may be needed for the applications mentioned above and a second, low resolution mode for use with the native video modes of the PC. A plug-in video adaptor may also be used rather than mounting it on the mother board.

In the embodiment shown, the video adaptor 1 comprises a video controller 4 such as a PVGA1A device (detailed in IPVGA1A User Manual' published by Western Digital (Paradise Systems) Corporation, Brisbane, CA).The video 1 1 controller 4 is configured with 256k bytes ot page mode cynamic random. access memory (DRAM) 5 such as a Mitsubi-shi M5M4464 as deiined in the recommended applications in the user manual mentionecl above.

The converter circuit 3 comprises a video line buf fer 6 such as an NEC uPD41 101 device (detailed in the 'NEC memory data book' published by NEC Electronics (UK) Ltd. Milton Keynes, UK), a video timing generator 7 implemented using standard FAST series logic devices 74FOO, 74F153, 74F163, 74F174 and 74F257 (detailed in 'Fairchild Advanced Schottky TTL' publishea by Fairchild Semiconductor Ltd., Potter's Bar, Herts, UK) ana a PALI6R8A device (detailed in the 'LS1 data book' published by Monolithic Memories Incorporated, Santa Clara, CA) and a control register 8 implemented cv a Fast series logic device 74F194 (also detailed in 'Fairchild Aivanced Schottky TW), The convertor circuit 3 also comprises a video digital to analog (D/A, convertor 9. a clock divider 1-0 and a multiplexer 11 wnich are implemented together using a Brooktree BT454 device (detailed in 'Brooktree Product Databook' published by Brooktree Corporation, San Diego, California). A 110MHz clock 12 is connected to both the divider 10 and D/A convertor 9. Depending on the type of monitor used, other output means can be used in place of the D/A converter 9.

These components are connected as shown in Figure 1 with the video timing generator 7 connected to receive timing signals from the video controller 4 and connected to control transfer of video data into and out of line bufier 6 and the D/A convertor 9. The multiplexer 11 is connected to route video output signals either directly from the video controller 4 or via the line buffer 6 and to pass signals on to the D/A convertor 9. The register 8 is connected to receive instructions from the system bus 2 to control the mode in which the multiplexer 11 and hence the convertor circuit 3 operates.

Software within the PC may control the convertor circuit in one of three modes, a high resolution mode, a low resolution mode and a third optional mode described further below.

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:r f7------ In the first, hig.li resolution mode, the full capabilities oi the enhanced resolution monitor, eg displaying 1280 x 960 pixels, are used. In this mode. the video adaptor 1 is programmed via the systems bus 2 to output one byte of video information every two 27.5 MHz clocks with a line rate of 66KHz. This programming consists of chaining all memory planes together to form one 'Large, linear bit-map. Consecutive bytes presented at the video output are taken from consecutive memory locations. The built-in video timing -generator is programmed to produce 128 bytes per video line at 66kHz with 960 active lines per frame. Trie line buffer 6 is bypassed using the multiplexer 11 and the eight bits of information are presented one after another to the the DIA convertor 9.

The multiplexer 11 is thus presented with 8 bits of video information at!3.75 M1-'7 (256 colours). The multiplexer 11 converts this first to 4 bits at 27.5 Y.Hz (16 colours) and then 1 bit at 110 MHz (monochromel. The byte is presented so that the f irst pixel is bit 7, the second pixel is bit 6 and so on to the eighth pixel being the bit 0. This allows an enhanced resolution monochrome (eg black and white) display to be produced on tne enhanced resoluticn monitor without exceeding the limited band width available from the memory 5 and the video controller 4.

It should be noted that all horizontal and vertical SY1QC and BLANK signalls are derived from the output signals of the video controller 4 using a minimal amount of logic within the video timing generator 7. Also, the sequencing and control of accesses to the memory 5 is controlled by the video controller 4. The enhanced resolution image s also held within the memory 5. None of the above mentioned functions are duplicated on the daughter card so enabling the cost of the system to be considerably reduced compared to prior art systems.

The second, low resolution mode, provides compatibility of the system when using the enhanced resolution monitor with the set of modes supported by the standard video adaptor 1 as would be used when driving a standard video graphics array (VGA) monitor. These modes are detailed in the WGA1A User Manual' mentioned above.

In this rode, the video adaptor 1 presents digital,!6 colour video information along with ELANK and SYNC signals derived from the 110MHz clock 12 divided by the divider 10. However, the video adaptor 1 generates video lines at a rate of 3-,,KHz whereas the enhanced resolution monitor requires video lines at 66kHZ. The video timing generator 7 thus synchronises to the BLANK signals from the video adaptor 1 and generates BLANK and SYNC signals at the monitor line rate of 66KkHz. The input and output BLANK signals are used to control the line buffer 6. Each line from the video adaptor 1 is written into the buffer as it arrives (at 3kHz) and the video information is read out at twice the input rate producing two identical lines on the enhanced resolution monitor (at 66kHz) containing the video information produced. by the video adaptor 1. Each pixel of information is also read out twice so each line comprises adjacent pairs of identical information.

ihe video tining generator 7 Eamples the E-AMW signals from the vide,:,7 adazl"er 1. in lhe middle of each line to extract the vertical blanKing inf ormat ion. It ther. skews trie timing of its BLANK output siEral bY one line relative to the input signal to ensure that the line buffer 6 is full when the first displayed 'Line Is output from the buffer.

The D/A convertor 9 combines the 4 bit (16 colour) display information and the output SYNC and BLANK signals to form a 1 volt peak to peak analog feed signal to the enhanced resolution monitor.

g The net result of the above operation is to cause each pixel output from the video adaptor 1 to be displayed as two consecutive pixels on a line and on two consecutive lines, ie as a square of four pixels. This effectively converts the enhanced monitor resolution from 1280. x 960 pixels to 640 x 480 pixels to match the video adapter capabilities in the standard video modes. This allows the PC native video modes to be displayed on the enhanced resolution monitor without exceeding the limited bandwidth available from the memory 5 and video controller 4 and without requiring a second (low resolution) monitor. If the equipment allows, other resolution conversions, eg from one pixel to a 3 x 3 square of pixels, could be similarly performed.

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1%, A Of course. when a monochrome monitor is used. the different colours in the display can be represented by various snales as well known in the art. References to colours within this specifica"i.-.,n should be unjerstood to include such different shading.

in the optional third mode mentioned above, the converter circuit 2 on the daughter card is effectively disabled so that the video adaptor can be used to drive directly a standard, 'Low resolution monitor (not shown) with the video adapter 1 operating as normal. in this mode, the video timing generator 7 idles, holding the enhanced resolution monitor blank and generating a 66kHz signal to prevent whistling regardless of the operation of the videc, adaptor 1.

Figure 2 is a circuit dia.; 1 ram of the components shown on +he daughter card Lri Figure 1. However, it should be noted that since Figure i is a functional. representation of t,,e circuit a Pre.-ise one-tc,-one relationship does not exist between the boxes s",-ijw,-i in Figure I an.d the components shewn in F.Eure 2.

Figure 3 iS an assembler listing of the contents of the PAL16RSA device used in the video timing: generator 7.

The features of the circuit shown in Figure 2 and of the listing in Figure 3 will be apparent to these skilled in the art in the light of the above description so will not be described further.

As will be appreciated, the arrangement described above eliminates the need for dedicated circuitry to provide an enhanced resolution display by making maximum usage of the facilities provided by a normal, standard PC video adapter together with a minimum amount of logic and.special programming.

The arrangement described also reduces or eliminates the dedicated circuitry (or second monitor) required in the prior art to provide compatibility with the native video modes of the PC by utilising the circuitry of the video adapter and converting its output signals for use on an enhanced resolution monitor.

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h i; h The arrangement described makes use of a lower resolution, higher colour count standard 'PC video adapter to reduce or eliminate the necessity of using expensive. separate, dedicated video memory and video timing generation for the high resolution image. The logic cescribed allows the number of colours to be converted into the enhanced resolution.

The arrangement also uses a minimum amount of logic to synchronise the video timing generator to the PC video adapter so avoiding the need to provide a separate video timing generator for the high resolution moce.

Although the arrangement described above comprises a plug-in converter circuit for connecting to a standard K video adapter, it W1K be a;prec. ated that it would be possible to build a video adapter incorporating the features of the plug-in circuit so as to operate in tne manner describe,-. ' above.

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Claims

1. A converter circuit for connection to a video adaptor of a computer to provide for the generation of a raster scan vicleo signal to an enhanced resolution monitor in either a first, high resolution mode or a second, low resolution mode, the converter circuit comprising: a video timing Seneratcfor connecting to receive timing signals from the video adaptor; a multiplexer for connecting to receive a video output signal from the video adaptor. a video line buffer for connecting to receive the video output si.grta't from the video acaptor and connected to the multiplexer; and output means connected to receive a video output signal from the multiplexer for providing a video output signal. to an enhanced resolution monitor, the converter circuit being selectively operable in a first mode in which video information from the video adapter is converted by the multiplexer for a high resolution, monochrome display and then provided to the output means, and a second mode in which video information for a low resolution, multicolour display is received by the multiplexer irom the video controller via the buffer such that eacn pixel of information is read out twice from the buffer and each line of information is read out twice to provide the outDut means with a video output signal of a low resolution display to be produced on an enhanced resolution monitor.

2. A video adaptor for a computer for providing a raster scan video signal to an enhanced resolution monitor in either a first, high resolution mode or a second, low resolution mode, the video adaptor comprising: a video controller for connecting to a system bus of a computer; a video memory connected to the video controller; a video tiring generator connected to receive timing signels from the video controller; a multiplexer connected to receive a video output signal from the video controller; a video line buffer connected to receive the video output signal from the video controller and connected to the multiplexer; and output means connected to receive a video output signal from the multiplexer for providing a video output signal to an enhanced resolution monitor, the video adaptor being selectively operable in a first mode in which video information from the video controller is converted by the multiplexer for a high resolution, monochrome display and then provided to the output means, and a second mode in which video 1 information for a low resolution, multi-colour display is received by the multiplexer from the video controller via the buffer such that each pixel of information is read out twice from the buffer and each line of information is read out twice to provide the output means with a video output signal of a low resolution display to be produced on an enhanced resolution monitor.

3. A computer having the facility for providing a raster scan video signal to an enhanced resolution monitor in either a first. high resolution mode or a second. low resolution mode, the computer having a processor responsive to a display request to provide instructions on a system bus to a video adaptor, the video adaptor comprising: a video controller connected to the system bus; a video memory connected to the video controller; a video timing generator connectee to receive timing signals from the video control.ler; a multiplexer connected to receive a video output signal from tine video controller; a video line buffer connected to receive the video output signal from the video controller and connected to the multiplexer,. and output means connected to receive a video output signal from the multiplexer for providing a video output signal to an enhanced resolution monitor, the video adaptor being selectively operable in response to instructions received on the system bus in a first mode in which video information from the video controller is converted by the multiplexer for a high resolution, monochrome display and then provided to the output means, and a second ir.de in which video information for a 'Low resolution, multicolour display Is received by the multiplexer from the video controller via the buffer such that each pixel of information is read out twice from 'the buffer and each line of information is read out twice to provide the output means with a video output signal of a low resolution display to be produced on an enhanced resolution monitor.

4. A method of providing a raster scan video signal from a video adaptor of a computer to an enhanced resolution monitor in either a first, high resolution mode or a second, low resolution mode, the method comprising the steps of: in the first mode, routing video information from the video adaptor for conversion by a multiplexer for a high resolution, monochrome display and then to output means connected to a high resolution monitor and, in the second mode, passing video information for a low resolution, multi-collour display to a buffer and then reading this into the multiplexer, under the control of a video timing generator connected to receive timing signals fron the video adaptor, such that each pixel of information is read out twice and each line of information is read out twice so as to provide the output means with a video output signal of a 'Low resolution display to be produced on an enhanced resolution monitor.

5. A converter circuit, video adaptor or computer as claimed in claim 1, 2 or 3 which is operable in a third mode in which the video timing generator, multiplexer, video line buffer and output means are effectively disabled so that the video adaptor can drive directly a low resolution monitor.

6. A video a-dentor as claimed ir claim 2 or claim 5 when dependent thereon in which the video controller and video memory are part of an industry standard video adaptor and the video timing generator, multiplexer, wideo line buffer anc output, means comprise a plug-in cenverter circuit connected thereto.

7. A method as claimed in claim 4 in which the video adaptor comprises a video controller and a video memcry and,:Ln the high resolution mode, the sequence and control of accesses to the video memory are controlled by the video controller.

8. A method as claimed in claim 7 in which, in the high resolution mode, the enhanced resolution image is held in the video memory of the video adaptor.

9. A method as claimed in claim 4, 7 or 8 In which, in the high resolution mode, the multiplexer reduces the word length of the video date received from the video adaptor and Increases the rate at which it Is presented to the output means, eg by converting 8 bits of video date at 13.75 MHz f irst to 4 bits at 27.5 MHz and then to 1 bit at 110 MHz.

10. A method as claimed in claim 4 or any of claims 7 to; 9 in which, in the low resolution mode, the line rate of the video infoaction received by the L.

a 1 %.

line buffer Is increased by reading It out from the buffer at a higher rate than It Is supplied thereto.

11. A method as claimed in claim 4 or any of claims 7 to 10 in which, in both the high and low resolution modes, the timing signals produced by the video timing generator are derived from output signals of the video adaptor.

12. A converter circuit substantially as hereinbefore described with reference to the accompanying drawings.

13. A video adaptor substantially as hereinbefore described with reference to the accompanying drawings.

14. A computer substantially as hereinbefore described with reference to the accompanying drawings.

15. A method of providing a raster scan. video signal from a video adaptc. r of a computer to an enhanced resolution monitor substantially as hereinbefore described.

Published 1990 at The Patent Ofrice, State House. 66 71 High Holborn. London WC1R 4TP. PurLher copies maybe obtained from The Patent Office "as BrLneh, St Mary Cray. Orpington, Kent BRS 3RD. Printed by Uultlplex technIques ltd. St Uary Cray, Kent, Con. 1.187 1 1 If -- 1. '