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GB2225670B - Carrier substrate and method for preparing the same - Google Patents

Carrier substrate and method for preparing the same

Info

Publication number
GB2225670B
GB2225670B GB8926971A GB8926971A GB2225670B GB 2225670 B GB2225670 B GB 2225670B GB 8926971 A GB8926971 A GB 8926971A GB 8926971 A GB8926971 A GB 8926971A GB 2225670 B GB2225670 B GB 2225670B
Authority
GB
United Kingdom
Prior art keywords
preparing
same
carrier substrate
carrier
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
GB8926971A
Other versions
GB2225670A (en
GB8926971D0 (en
Inventor
Hidetaka Shigi
Takashi Takenaka
Fumiyuki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of GB8926971D0 publication Critical patent/GB8926971D0/en
Publication of GB2225670A publication Critical patent/GB2225670A/en
Application granted granted Critical
Publication of GB2225670B publication Critical patent/GB2225670B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
GB8926971A 1988-11-30 1989-11-29 Carrier substrate and method for preparing the same Expired - Lifetime GB2225670B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63302396A JPH02148862A (en) 1988-11-30 1988-11-30 Circuit element package, carrier substrate and manufacturing method

Publications (3)

Publication Number Publication Date
GB8926971D0 GB8926971D0 (en) 1990-01-17
GB2225670A GB2225670A (en) 1990-06-06
GB2225670B true GB2225670B (en) 1992-08-19

Family

ID=17908409

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8926971A Expired - Lifetime GB2225670B (en) 1988-11-30 1989-11-29 Carrier substrate and method for preparing the same

Country Status (5)

Country Link
JP (1) JPH02148862A (en)
KR (1) KR930006274B1 (en)
CN (1) CN1015582B (en)
DE (1) DE3939647A1 (en)
GB (1) GB2225670B (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2503725B2 (en) * 1990-05-18 1996-06-05 日本電気株式会社 Multilayer wiring board
DE69304617T2 (en) * 1992-06-15 1997-03-27 Gnb Ind Battery Co Modular housing structure for batteries
US5378927A (en) * 1993-05-24 1995-01-03 International Business Machines Corporation Thin-film wiring layout for a non-planar thin-film structure
JPH07221462A (en) * 1994-02-03 1995-08-18 Murata Mfg Co Ltd Composite circuit part
US6614110B1 (en) 1994-12-22 2003-09-02 Benedict G Pace Module with bumps for connection and support
EP0804806A1 (en) * 1994-12-22 1997-11-05 Benedict G. Pace Device for superheating steam
US5904499A (en) * 1994-12-22 1999-05-18 Pace; Benedict G Package for power semiconductor chips
US6384344B1 (en) 1995-06-19 2002-05-07 Ibiden Co., Ltd Circuit board for mounting electronic parts
FR2747780B1 (en) * 1996-04-22 1998-06-05 Cogema DEVICE FOR TAKING HARMFUL LIQUID SAMPLES, ESPECIALLY LOADED WITH SOLID PARTICLES
EP0883173B1 (en) 1996-09-12 2007-09-12 Ibiden Co., Ltd. Circuit board for mounting electronic parts
JPH10308565A (en) * 1997-05-02 1998-11-17 Shinko Electric Ind Co Ltd Wiring board
JP3973340B2 (en) * 1999-10-05 2007-09-12 Ｎｅｃエレクトロニクス株式会社 Semiconductor device, wiring board, and manufacturing method thereof
JP4023076B2 (en) 2000-07-27 2007-12-19 富士通株式会社 Front and back conductive substrate and manufacturing method thereof
JP2005045073A (en) 2003-07-23 2005-02-17 Hamamatsu Photonics Kk Back-illuminated photodetection element

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3875479A (en) * 1973-05-07 1975-04-01 Gilbert R Jaggar Electrical apparatus
US4023197A (en) * 1974-04-15 1977-05-10 Ibm Corporation Integrated circuit chip carrier and method for forming the same
US4202007A (en) * 1978-06-23 1980-05-06 International Business Machines Corporation Multi-layer dielectric planar structure having an internal conductor pattern characterized with opposite terminations disposed at a common edge surface of the layers
EP0016306A1 (en) * 1979-03-23 1980-10-01 International Business Machines Corporation Method of manufacturing a multi-layered glass-ceramic package for the mounting of semiconductor devices
EP0035093A2 (en) * 1980-01-25 1981-09-09 International Business Machines Corporation Arrangement for packing several fast-switching semiconductor chips
EP0043029A2 (en) * 1980-06-30 1982-01-06 International Business Machines Corporation Sintered multi-layer ceramic substrate and method of making same
US4407007A (en) * 1981-05-28 1983-09-27 International Business Machines Corporation Process and structure for minimizing delamination in the fabrication of multi-layer ceramic substrate
EP0099544A1 (en) * 1982-07-22 1984-02-01 International Business Machines Corporation Method for forming conductive lines and via studs on LSI carrier substrates
US4437140A (en) * 1978-06-28 1984-03-13 Mitsumi Electric Co. Ltd. Printed circuit device
EP0145599A2 (en) * 1983-12-08 1985-06-19 Eurofarad Efd Alumina interconnection substrate for an electronic component, and method for its production
EP0152794A2 (en) * 1984-02-17 1985-08-28 International Business Machines Corporation Multi-layered electrical interconnection structure
EP0171783A2 (en) * 1984-08-17 1986-02-19 Hitachi, Ltd. Module board and module using the same and method of treating them
US4647148A (en) * 1983-03-31 1987-03-03 Tokyo Shibaura Denki Kabushiki Kaisha Fiber optic receiver module
EP0249755A2 (en) * 1986-05-19 1987-12-23 Nippondenso Co., Ltd. Hybrid integrated circuit apparatus
EP0258056A2 (en) * 1986-08-27 1988-03-02 Nec Corporation Integrated circuit package having coaxial pins
EP0260857A2 (en) * 1986-09-08 1988-03-23 Nec Corporation Multilayer wiring substrate
GB2197540A (en) * 1986-11-12 1988-05-18 Murata Manufacturing Co Circuit substrate

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3382208D1 (en) * 1982-12-15 1991-04-18 Nec Corp MONOLITHIC MULTILAYER CERAMIC SUBSTRATE WITH AT LEAST ONE DIELECTRIC LAYER MADE OF A MATERIAL WITH PEROVSKIT STRUCTURE.
JP2610487B2 (en) * 1988-06-10 1997-05-14 株式会社日立製作所 Ceramic laminated circuit board

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3875479A (en) * 1973-05-07 1975-04-01 Gilbert R Jaggar Electrical apparatus
US4023197A (en) * 1974-04-15 1977-05-10 Ibm Corporation Integrated circuit chip carrier and method for forming the same
US4202007A (en) * 1978-06-23 1980-05-06 International Business Machines Corporation Multi-layer dielectric planar structure having an internal conductor pattern characterized with opposite terminations disposed at a common edge surface of the layers
US4437140A (en) * 1978-06-28 1984-03-13 Mitsumi Electric Co. Ltd. Printed circuit device
EP0016306A1 (en) * 1979-03-23 1980-10-01 International Business Machines Corporation Method of manufacturing a multi-layered glass-ceramic package for the mounting of semiconductor devices
EP0035093A2 (en) * 1980-01-25 1981-09-09 International Business Machines Corporation Arrangement for packing several fast-switching semiconductor chips
EP0043029A2 (en) * 1980-06-30 1982-01-06 International Business Machines Corporation Sintered multi-layer ceramic substrate and method of making same
US4407007A (en) * 1981-05-28 1983-09-27 International Business Machines Corporation Process and structure for minimizing delamination in the fabrication of multi-layer ceramic substrate
EP0099544A1 (en) * 1982-07-22 1984-02-01 International Business Machines Corporation Method for forming conductive lines and via studs on LSI carrier substrates
US4647148A (en) * 1983-03-31 1987-03-03 Tokyo Shibaura Denki Kabushiki Kaisha Fiber optic receiver module
EP0145599A2 (en) * 1983-12-08 1985-06-19 Eurofarad Efd Alumina interconnection substrate for an electronic component, and method for its production
EP0152794A2 (en) * 1984-02-17 1985-08-28 International Business Machines Corporation Multi-layered electrical interconnection structure
EP0171783A2 (en) * 1984-08-17 1986-02-19 Hitachi, Ltd. Module board and module using the same and method of treating them
EP0249755A2 (en) * 1986-05-19 1987-12-23 Nippondenso Co., Ltd. Hybrid integrated circuit apparatus
EP0258056A2 (en) * 1986-08-27 1988-03-02 Nec Corporation Integrated circuit package having coaxial pins
EP0260857A2 (en) * 1986-09-08 1988-03-23 Nec Corporation Multilayer wiring substrate
GB2197540A (en) * 1986-11-12 1988-05-18 Murata Manufacturing Co Circuit substrate

Also Published As

Publication number Publication date
CN1015582B (en) 1992-02-19
DE3939647A1 (en) 1990-05-31
JPH02148862A (en) 1990-06-07
KR930006274B1 (en) 1993-07-09
CN1043407A (en) 1990-06-27
GB2225670A (en) 1990-06-06
KR900008664A (en) 1990-06-03
GB8926971D0 (en) 1990-01-17

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee