GB2220828A - Address producing circuit for zoom function - Google Patents

Abstract

Disclosed is an address producing circuit for a zoom function in which a plurality of horizontal and vertical addresses are provided to permit wider selection of a partial picture around a plurality of locations disposed on the screen of a monitor device. Image data stored in a predetermined address region according to the selection is road out to display on the screen, so that the picture of the selected partial region can be magnified to a whole screen picture. Two multiplexers are respectively fed with a plurality of row and column addresses defining the starting point of the plurality of regions. The pair of addresses are selected using a microprocessor (13) and command decoder (14) controlling the multiplexers (15), (16). The zoom function is produced by addressing the field memory at sub-rates of the color sub-carrier and horizontal sync. frequencies. <IMAGE>

Description

ADDRESS PRODUCING CIRCUIT FOR ZOOM FUNCTION The present invention relates to a digital image processing system having a zoom function for magnifying a picture from a partial region of a single frame displayed on a monitor screen to a whole sized screen, and particularly to a circuit for controlling a picture of a partial region which it is desired to magnify, according to selection of an operator.

Usually, the operation of a digital image processing system is comprised of storing temporarily image data of one field in a field memory, reading out the image data stored in the memory, and thereafter converting the data to an analog image signal to display on a monitor screen through a monitor driver. The zoom function means, in the art, a pictorial operation magnifying a picture of a partial region of one frame displayed on the monitor screen to a full-sized picture of one frame. In order to carry out such a function, the digital image processing system reads out image data stored in an address corresponding to a selected partial area of total image data in a field memory, converts the read-out data to an analog image signal, thereafter outputting to the monitor through the monitor driver, by which it becomes magnified to a full-size screen on the monitor.However, a conventional zoom function as shown in Fig.l of the accompanying drawings, has the drawback that selection of a desired picture portion to magnify is considerably limited because it is constructed so as to be operated by magnifying selectively the partial picture around only five fixed locations.

Preferred embodiments of the present invention aim to provide an address producing circuit for a zoom function in which horizontal and vertical addresses are provided to make more free selection of a partial picture around a plurality of locations disposed on a screen of a monitor device, and image data stored in a predetermined address region according to the selection is read out to display on the screen, so that the picture of the selected partial region can be magnified to a whole screen picture.

According to a first aspect of the invention, an address producing circuit for zoom function is comprised of: a micro-processor for controlling and processing image data; a command decoder for producing a zoom control signal and first and second zoom-position selection data by receiving and thereafter decoding a zoom command and zoom-position data from said micro-processor; a first multiplexer for inputting a plurality of row addresses, and thereby outputting a row address selected from said plurality of row addresses in response to a logic state of the first zoom-position selection data applied from said command decoder; a second multiplexer for inputting a plurality of column addresses, and thereby outputting a column address selected from said plurality of column addresses in response to a logic state of the second zoom-position selection data applied from said command decoder;; a third multiplexer for inputting a colour subcarrier signal and its frequency-divided signal from the frequency divider, to thereby output either one of the colour sub-carrier or said frequency divided signal thereof in response to a logic state of the zoom control signal; a fourth multiplexer for inputting a horizontal synchronizing signal and its frequency-divided signal from the frequency divider, to thereby output either one of the horizontal synchronizing signal or said frequency divided signal in response to a logic state of the zoom control signal;; a vertical counter for inputting the output of said first multiplexer in accordance with a vertical synchronizing signal applied from the frequency divider through a load terminal, and thereby outputting to the field memory row-address data, by adding a numeral "1" to data provided from said first multiplexer whenever the horizontal synchronizing signal or its frequency-divided signal is received to a clock terminal from said fourth multiplexer; and a horizontal counter for inputting the output of said second multiplexer in accordance with a horizontal synchronizing signal applied from the frequency divider through a load terminal, and thereby outputting to the field memory column-address data, by adding a numeral "1" to data provided from said second multiplexer whenever the colour sub-carrier signal or its frequency-divided signal is received to a clock terminal from said third multiplexer.

According to a second aspect of the invention, there is provided a digital image processing system having a zoom function, the system including an address producing circuit, the arrangement being such that a portion of a whole image can be selected and enlarged, the address producing circuit being arranged to permit at least one row address and column address of a number of pre-selected row and column addresses to be chosen as start points for the enlargement of part of a whole image.

The address-producing circuit may comprise: a micro-processor, a command decoder, first and second multiplexers, and first and second counters, the micro-processor being arranged to generate controlling data and address data, the command decoder being arranged to decode said controlling and address data, first and second multiplexers being arranged to output row and column addresses respectively in response to said address data, and first and second counters being arranged to increment from one row address to the next, at a frequency which is a proportion of that of the horizontal synchronizing pulses and to increment from one column address to the next, at a frequency which is a proportion of that of the colour sub-carrier.

For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which: FIG.1 is a schematic diagram showing an arrangement of central points of partial regions to be magnified in a zoom function known in the art; FIG.2 is a block diagram of a preferred embodiment of the present invention; and FIG.3. is a schematic diagram showing arrangements of central points and start points of partial regions to be magnified in a zoom function according to the circuit of FIG.2.

Referring to FIG.2, in an image processing system having a field memory (not shown) and a frequency divider (not shown), an address producing circuit for a zoom function comprises a micro-processor 13 for controlling and processing image data. A command decoder 14 produces a zoom control signal and first and second zoom-position selection data by receiving and thereafter decoding a zoom command and zoom-position data from the microprocessor 13. A first multiplexer 15 inputs a plurality of row addresses, and thereby outputs a row address selected from the plurality of row addresses in response to a logic state of the first zoom-position selection data applied from said command decoder 14. A second multiplexer 16 inputs a plurality of column addresses, and thereby outputs a column address selected from the plurality of column addresses in response to a logic state of the second zoom-position selection data applied from said command decoder 14. A third multiplexer 17 inputs a colour sub-carrier signal and its frequencydivided signal from the frequency divider, to thereby output either one of the colour sub-carrier or the frequency divided signal thereof in response to a logic state of the zoom control signal. A fourth multiplexer 18 inputs a horizontal synchronizing signal and its frequency-divided signal from the frequency divider, to thereby output either one of the horizontal synchronizing signal or said frequency divided signal in response to a logic state of the zoom control signal.

A vertical counter 19 inputs the output of said first multiplexer 15 in accordance with a vertical synchronizing signal applied from the frequency divider through a load terminal LD, and thereby outputs to the field memory row-address data, by adding a numeral "1" to data provided from said first multiplexer 15 whenever the horizontal synchronizing signal or its frequency-divided signal is received to a clock terminal CLK from said fourth multiplexer.A horizontal counter 20 inputs the output of said second multiplexer 16 in accordance with a horizontal synchronizing signal applied from the frequency divider through a load terminal LD, and thereby outputs to the field memory column-address data, by adding a numeral "1" to data provided from said second multiplexer 16 whenever the colour sub-carrier signal or its frequency-divided signal is received to a clock terminal CLK from said third multiplexer.

Referring to FIG.3, the leftmost schematic diagram shows the arrangement of central points of a plurality of partial regions for selecting and magnifying on the screen of a monitor in the case that the frequencies of horizontal synchronizing signal and the colour sub-carrier are made a half of their original frequencies applied, and the rightmost is a schematic diagram shows various locations of the start points with respect to the leftmost diagram.

Hereinafter, the operation of the preferred embodiment circuit will be described in detail with reference to FIGS. 2 and 3.

At first, assuming that there are three rowaddresses and three column-addresses, that are of different values to each other, in the first and second multiplexers 15,16, and that the colour sub-carrier (Fsc) and its divided-by-2 frequency sub-carrier (hereinafter designated as FSC/2) are input to the third multiplexer 17, and that the horizontal synchronizing signal and its divided-by-2 frequency horizontal synchronizing signal (hereinafter designated as HSYN/2) are input to fourth multiplexer 18, then a size of a partial screen which may be magnified to a full size of monitor screen becomes a region corresponding to 1/4 of that of the monitor screen. When a start point of a partial screen to magnify is set by row address and column address, the partial screen and its central point for magnifying to the full screen of monitor will be as shown in FIG.3.

Then, microprocessor 13, when information with respect to the zoom function and a desired partial region to be magnified on the monitor screen are input thereto upon reception of a given television broadcasting program, produces a zoom functional command and zoom position data, thereby synchronizing to the clock pulse and transferring to the command decoder 14 in series form, and then applies a strobe signal to the command decoder 14. At this moment, the command decoder 14 input with the zoom functional command and zoom position data by the clock pulse and strobe signal from the microprocessor 13, decodes said zoom functional command and zoom position data to thereby produce a zoom control signal by said zoom functional command, and also to produce first and second position selection data by said zoom position data.Thus, the zoom control signal outputs through line 1 to the third and fourth multiplexer 17, 18, the first position selection data to the first multiplexer 15, and the second zoom position selection data to the second multiplexer 16, respectively.

The first multiplexer 15 receiving the preset row addresses having respectively different values through three bus lines 2-4, selects a row address from the said preset row addresses designated by said first zoom position selection data, according to the logic state of two bits of the first zoom position selection data applied to the two selection terminals LSl, LS2 from the command decoder 14, and thereby outputs to the input port of the vertical counter 19.And, the second multiplexer 16 also receiving two bits of second zoom position selection data from said command decoder 14 to its selection terminals LS3, LS4 selects a column address from the preset column addresses of different values input through three bus lines 5-7, in accordance with the logic state of said second zoom position selection data, and thereafter outputs to the input port of the horizontal counter 20.

Meanwhile, the third multiplexer 17 receiving the zoom control signal to its selection terminal from said command decoder 14 through the line 1, selects either one of the two colour sub-carriers Fsc and Fsc/2 input respectively to the two input terminals from the frequency divider through two lines 8, 9, according to the logic state of said zoom control signal, and thereafter outputs to the clock terminal of horizontal counter 20. The fourth multiplexer 18 also receiving the two horizontal synchronizing signals HSYN and HSYN/2 respectively to the input terminals from the frequency divider through two lines 10, 11 selects either one of the two inputs in accordance with the logic state of the zoom control signal input to its selection terminal through line 1 from said command decoder 14, and thereafter outputs to the clock terminal of vertical counter 19.

Then, the vertical counter 19 receives the preset row address (i.e. one of the three row addresses) applied to the input port from said first multiplexer 15 during a time period corresponding to the blanking interval of the vertical synchronizing signal applied to the load terminal LD from the frequency divider through the line 12, and thereafter adds a numeral "1" to said preset row address every time that the signal HSYN/2 is applied to the clock terminal from said fourth multiplexer 18 during the vertical scanning period. And it produces a row address changed by a numeral "1" at every two successive horizontal scanning intervals, and then outputs to the field memory through the output port.

In the meanwhile, the horizontal counter 20 receives the preset column address (i.e., one of the three column addresses) applied to the input port from said second multiplexer 16 during a time period corresponding to the blanking interval of the horizontal synchronizing signal applied to the load terminal LD from the frequency divider through the line 11, and thereafter adds a numeral "1" to said preset column address at every time that the signal Fsc/2 is applied to the clock terminal from said third multiplexer 17 during the horizontal scanning period.In addition, it produces a row address increased by a numeral "1" at every two successive periods of the colour sub-carrier signal, and then outputs to the field memory through the output port. Then the field memory reads out, throughout a time period of one field, the image data stored in address area corresponding to the one-fourth (1/4) of the full screen in accordance with the column and row addresses of the horizontal and vertical counters 20 and 19, in which the reading-out operation of said image data may be carried out at every two successive horizontal scanning period and at every two periods of the colour sub-carrier.

The start points of FIG.3 are determined by said preset row addresses and column addresses, which are shown by the following table.

TABLE Column Addresses First Second Third Row First STl(DA1) ST2(DA2) ST3(DA3) Addresses Second ST4(DA4)' ST5(DA5) ST6(DA6) Third ST7(DA7) ST8(DA8) ST9(DA9) In the above table, "ST" is used to designate start points of FIG.3, and 'tDA" is used to mean various center points of the partial regions to be magnified.

The above described embodiment of the invention has an advantage that the number of partial screen regions that may be selected to be magnified upon application of the zoom function may be extended, since it is possible to provide for the first and second multiplexers a plurality of preset row addresses and preset column addresses having different values to each other to select therefrom a desired respective address, and further control the counting periods of the horizontal and vertical counters.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims (5)

1. In an image processing system having a field memory and a frequency divider, an address producing circuit for zoom function comprises: a micro-processor arranged to control and process image data; a command decoder arranged to produce a zoom control signal and first and second zoom-position selection data by receiving and thereafter decoding a zoom command and zoom-position data from said microprocessor; a first multiplexer arranged to input a plurality of row addresses, and thereby output a row address selected of said plurality of row addresses in response to the logic state of the first zoomposition selection data applied from said command decoder;; a second multiplexer arranged to input a plurality of column addresses, and thereby output a column address selected of said plurality of column addresses in response to the logic state of the second zoom-position selection data applied from said command decoder; a third multiplexer arranged to input a color sub-carrier signal and its frequency-divided signal from the frequency divider, to thereby output either one of the color sub-carrier or said frequency divided signal thereof in response to the logic state of the zoom control signal; a fourth multiplexer arranged to input a horizontal synchronizing signal and its frequencydivided signal from the frequency divider, to thereby output either one of the horizontal synchronizing signal or said frequency divided signal in response to the logic state of the zoom control signal;; a vertical counter arranged to input the output of said first multiplexer in accordance with a vertical sync#hronizing signal applied from the frequency divider through a load terminal, and thereby output to the field memory row-address data, by adding a numeral "1" to data provided from said first multiplexer whenever the horizontal synchronizing signal or its frequency-divided signal is received to a clock terminal from said fourth multiplexer; and a horizontal counter arranged to input the output of said second multiplexer in accordance with a horizontal synchronizing signal applied from the frequency divider through a load terminal, and thereby output to the field memory column-address data, by adding a numeral "1" to data provided from said second multiplexer whenever the color sub-carrier signal or said its frequency-divided signal is received to a clock terminal from said third multiplexer.

2. An address producing circuit substantially as herein described with reference to Figure 2 and/or 3 of the accompanying drawings.

3. A digital image processing system having a zoom function, the system including an address-producing circuit, the arrangement being such that a portion of a whole image can be selected and enlarged, the address producing circuit being arranged to permit at least one row address and column address of a number of preselected row and column addresses to be chosen as start points for the enlargement of part of a whole image.

4. A system as claimed in Claim 3, wherein the address-producing circuit comprises: a micro-processor, a command decoder, first and second multiplexers, and first and second counters, the micro-processor being arranged to generate controlling data and address data, the command decoder being arranged to decode said controlling and address data, first and second multiplexers being arranged to output row and column addresses respectively in response to said address data, and first and second counters being arranged to increment from one row address to the next, at a frequency which is a proportion of that of the horizontal synchronizing pulses and to increment from one column address to the next, at a frequency which is a proportion of that of the colour sub-carrier.

5. A system substantially as herein described with reference to Figure 2 and/or 3 of the accompanying drawings.