GB2211986A - Electrodes for semiconductor devices - Google Patents

Abstract

The manufacture of semiconductive devices is described in which a semiconductive material having a metallised electrode 10 and bond pad 11 connected by a coplanar bridging connector 19 is wet etched to isolate the bond pad by etching material from beneath the bridging connector to form a trench, and in which the bridging connector has, over the trench position, orthogonal parts 19b, 19c to prevent continuous unetched ridges due to uneven etching extending from beneath the electrode to beneath the bond pad. <IMAGE>

Description

AN IMPROVED SEMIICONDUCTIYE DEVICE This invention relates to semi-conductive devices, particularly integrated optical devices using Groups III - V semiconductor materials, but the invention also has application in other integrated circuits using semi-conductive devices.

Many important electronic and optoelectronic devices such as Gallium Arsenide field effect transistors, pin photodetectors, Gallium Arsenide/Gallium Aluminium Arsenide electro-optic modulators, incorporate a reverse biased rectifying electrode. The area of this electrode, for highest speed operation, is optimised. However, external electrical contact must be made thereto. Figure 1 of the accompanying drawings diagrammatically illustrates an electrode 10 of this type and, approximately to scale, a conventional bond pad 11 electrically associated therewith. Unless special steps are taken to avoid it, the bond pad 11 will have the same capacitance per unit area as the electrode. In view of the disparity in size between the electrode 10 and the pad 11, the inordinate capacitance of the pad 11 will have an extremely deleterious effect on the high speed capability of the electrode.

Figure 2 of the accompanying drawings shows, in diagrammatic cross-section, one method used heretofore to reduce the capacitance effect of the pad 11. In this arrangement, the electrode 10 is mounted on an undoped epitaxial semiconductive layer 12. The layer 12 is grown on a layer 13 doped + which, in turn, is formed in the surface of an p+ or S.I. substrate 14. A polymer buffer layer 15 is formed on the surface of the layer 12. The layer 15 is of a material such as a polyimide of low dielectric constant. The metal contact or bond pad 11 is formed on this buffer layer 15 and a metal connection 16 formed between the pad 11 and the electrode 10.

Such a structure is non-planar with the consequent difficulty of ensuring that the metal connection is continuous.

Another method of overcoming the problem (illustrated in Figure 3), is to provide a pre-etched well 17 down to the substrate 14 wherein the pad 11 is deposited. Again, such an arrangement is non-planar and difficulties have been experienced in assuring the metal connection between the electrode 10 and the pad 11.

Additionally, to avoid electrical breakdown in the #+ doped layer 13, an insulator layer 18 must be provided beneath the connection 16.

A more recent approach to this problem has been described in "Electronic Letters" Pages 415 and 416 of Volume 23 Number 8 dated 9th April 1987 by D. Wake, R.H. Walling, S.K. Sargood and I.D.

Henning. This approach may be termed an wair bridge" in that the bond pad, the electrical connection (equivalent to the connection 16 described above) and the electrode are constituted by planar metallisation and, thereafter, the layer supporting the electrical connection is wet etched away to provide the necessary electrical isolation. Wet etching effectiveness is dependant upon the nature of the etchable material and the orientation of the device thereon. It has been found that there is a possibility of remanent nonetched ridges co-linearly beneath the electrical connection, forming an electrical bridge between active layers beneath the electrode and the bond pad.

The present invention is directed to the formation of air bridges wherein the aforesaid possibility is minimised or eleminated According to the present invention, there is provided a semiconductive device comprising a substrate including a doped layer, an electrode positioned above the doped layer, a bond pad on the doped layer connected by a bridge connector to the electrode, and a trench in the doped layer isolating that portion of the doped layer beneath the bond pad, and wherein the bridge connection comprises a first part extending over the trench in a first direction and a second part extending over the trench in a substantially orthogonal direction.

The invention will be described further, by way of example, with reference to Figures 4 to 8 of the accompanying drawings, in which: Figure 4 is a diagrammatic side elevation of a semiconductive device according to the present invention; Figure 5 is a plan view of the device of Figure 4; Figures 6a and 6h are detached sections illustrating possible etch results, in depenance upon crystal orientations of the device of Figures 4 and 5; Figure 7 is a perspective view of the device of Figures 4 and 5; and Figure 8 is a plan view of an alternative form of the device of Figures 4 and 5.

Referring now to Figures 4 to 7, a semiconductive device according to the present invention is formed on an SI (Semi Insulating) substrate 14, for example, Gallium Arsenide. The substrate 14 includes a doped layer 13 and a m - V semiconductor material layer 12 epitaxically grown on the surface of the substrate 14. Metallisation, to form an electrode 10, a bond pad 11 and a bridge connection 19 is then deposited on the substantially planar surface of the layer 12. An etch mask of, for example, a photoresist is formed on the metal and on the surface of the layer 12 except for the area 20 shown in Figure 5.

A wet etch is applied, for example, by immersion, to the device to form a deep trench 21 surrounding the pad 11 and beneath the bridge connection 19 ie in the unmasked region 20.

Etches tend to etch crystal structures selectively and the bridge connection 19 serves to protect the layers 12 and 13 therebeneath.

As can be seen, from Figures 6a and 6E, depending on the orientation of the sub-jacent crystal structure, ridges 22 or 23 or 24 may be left. If the bridge connection 19 were to be merely a linear strip, as in the prior art, there is a possibility of an unetched ridge connecting between the heavily doped regions of the layer 13 beneath the electrode 10 and beneath the bond pad 11.

In accordance with the present invention, this possibility is elimentated in that the metallisation forming the bridge connections 19 is forked (Figures 5 and 7) or trident shaped (Figure 8). The fork shaped connection 19 provides effective etch masking in two orthogonal directions in different areas thereby eliminating the possibility of a continuous bridging ridge to remain. For a first crystal lattice orientation (Figures 6# (and less than optimum etching) a first ridge 22 extends beneath a first limb 19# of the forked bridge connection 19 and two further ridges 23 extend beneath the prongs 19h of the connection 19 but no continuous ridge is formed.For a second orthogonal crystal lattice orientation (Figure 6O, only a single ridge 24 is left beneath the cross piece 19 of the bridge connector 19 and again no continuous bridging ridge can be formed. At relative orientations of the crystal lattice of the layer 12 (relative to the device) between these two extremes, shorter partial ridges will be formed in both directions but, again, the possibility of a continuous bridging ridge is minimised.

Isolation of the bond pad 11 using the air bridge technique of the present invention results in more devices reaching specification and the substantially complete elimination of parasitic capacitance effects due to the pad 11.

Figure 8 shows a second embodiment of an air bridge connector according to the present invention. Again it shows a connection 26 having portions extending orthogonally to prevent the formation of continuous bridging ridges due to etch masking by the bridge connection.

The invention is not confirmed to the precise details of the foregoing examples and variations may be made thereto.

For instance, it is preferred that the metallisation forming the bridge connection be thicker than conventional, for mechanical strength, and narrower than conventional, to permit better etching of the subjacent material.

Any metallisation pattern which provides the orthogonal or substantially orthogonally directed portions will suffice to ensure that a continuous bridging ridge cannot be left extending from the doped layer 13 beneath the electrode 10 to the doped layer 13 beneath the bond pad 11. However, it is preferred that the pattern be such as to add to rather than detract from the mechanical strength of the bridge connection as is the case using a fork or a trident shaped connection.

Claims (9)

CLAIMS: ~

1. A semiconductive device comprising a substrate including a doped layer, an electrode positioned above the doped layer, a bond pad on the doped layer connected by a bridge connector to the electrode, and a trench in the doped layer isolating that portion of the doped layer beneath the bond pad, and wherein the bridge connection comprises a first part extending over the trench in a first direction and a second part extending over the trench in a substantially orthogonal direction.

2. A device as claimed in claim 1 wherein the bridge connection includes a third part extending in the first direction and connecting the second part to the electrode or bond pad.

3. A device as claimed in claim 2 wherein the bridge connection is fork shaped, there being two of the third parts connected by the second part to the first part.

4. A device as claimed in claim 2 wherein the bridge connections comprises a plurality of first parts and a plurality of third path, each third part being connected to the second part in off-set relationship to the connection of a first part to the second part.

5. A device as claimed in any preceding claim wherein, immediately below the electrode and the bond pad, is an epitaxially grown group III - V material.

6. A semiconductive device substantially as hereinbefore described with reference to an as illustrated in Figures 4 to 7 or Figures 4 to 7 as modified by Figure 8 of the accompanying drawings.

7. A method of forming a semiconductive device having an electrode and a bond pad disposed on a semi insulating substrate including a doped layer, comprising the steps of depositing metal on the surface of the substrate in a pattern to form the electrode and the bond pad and a bridging connection therebetween, masking the surface except in a region surrounding the bond pad, and wet etching the unmasked region to undercut the bridging connection to a depth greater than that of the doped layer, and wherein the metal pattern is arranged so that the bridging connection comprises two substantially orthogonally disposed parts.

8. A method as claimed in claim 7 including the step of epitaxially growing a group 111 - V material layer on the surface of the substrate before the metal is deposited thereon.

9. A method of forming a semi-conductive device as claimed in claim 7 and substantially as hereinbefore described.