GB2208966A

GB2208966A - Junction field effect transistor

Info

Publication number: GB2208966A
Application number: GB8819747A
Authority: GB
Inventors: Kathirkamathamby Kandiah
Original assignee: UK Atomic Energy Authority
Current assignee: UK Atomic Energy Authority
Priority date: 1987-08-21
Filing date: 1988-08-19
Publication date: 1989-04-19
Also published as: GB8719841D0; GB8819747D0

Abstract

A junction field-effect transistor (JFET) is provided, of the type in which the source, drain and gate regions each comprises a plurality of parallel doped strips (50, 52, 54) all of which are substantially coplanar, but in which metal conductors (42, 44) do not cross over any active pn junctions, and are remote from active surface regions of the transistor. The source (52), gate (50) and drain (54) are covered by an oxide layer, electrical contact to them being made remote from the active surface parts. Such a JFET can be expected to produce much less random telegraph signal (RTS) noise than conventional JFETS. <IMAGE>

Description

Transistor This invention relates to transistors and in particular to junction field-effect transistors (JFETs).

A junction field-effect transistor or JFET (otherwise known as a junction-gate field effect transistor) includes a doped semiconductor region with highly doped zones referred to as the source and the drain, and an intervening doped zone referred to as a gate doped so that there are rectifying (p-n) junctions between it and both the source and the drain. The voltage applied to the gate m#ay be used to control the current flow between the source and the drain. JFETs may be used in amplifiers, and are especially useful in low noise amplifiers. Nevertheless it has been found in some cases that noise signals may be generated by a JFET itself.A particularly difficult type of noise to accommodate is that referred to as random telegraph signal (RTS) noise, where a signal switches at random intervals between two well-defined levels which may exceed the noise level due to other causes by ten or twenty times; where a JFET is used in an alarm system (eg a fire alarm) the occurrence of such an RTS noise signal can lead to a false alarm, so that even if the interval between successive RTS noise signals is several days it is not satisfactory.

According to the present invention there is provided a junction field-effect transistor comprising source, drain and gate zones each comprising a plurality of parallel doped strips all of which strips are substantially coplanar, the transistor having no metal conductors crossing over junctions, and no metal conductors near active surface regions of the transistor, and wherein any metal connection to the gate, the source or the drain zone is spaced at least 1 micrometre away from the edge of the said zone, in a direction parallel to the surface.

Preferably any such connection is spaced 5 micrometres from the edge of the zone. In the present specification, the term active surface region means a region adjacent the surface of the doped semiconductor and between any two zones, such as between the gate and the source, where the distance between the zones is less than about 25 micrometres. Although the source, drain and gate strips are substantially coplanar, it should be understood that they may differ in thickness.

Such a JFET can be expected to produce far less RTS noise than a conventionally-designed JFET, as there is much less likelihood of unwanted impurity atoms diffusing into the active surface regions of the device where it is believed they may cause RTS noise, and of a conductor lying over a junction increasing the generation of RTS noise.

The invention will now be further described by way of example only and with reference to the accompanying drawings, in which: Figure 1 shows a diagrammatic plan view of a prior art JFET; Figure la shows a graphical representation of noise in a prior art JFET; Figure 2 shows a diagrammatic plan view of a JFET of the invention; and Figure 3 shows a sectional view on the line III-III of Figure 2.

Referring to Figure 1 there is shown a diagrammatic plan view of a prior art JFET defined on a silicon wafer 10. It will be appreciated that the entire surface of the wafer 10 is covered by a layer of insulating silicon dioxide (which is not shown for clarity) except where U-shaped metallic contacts 12 and 14 are on the surface.

The n-channel JFET comprises a generally rectangular epitaxial region 16 of n-type silicon below which is a substrate and around which is an isolating wall 18 of p+ extending up from the substrate. Near the surface of this rectangular region 16 are three parallel p+ gate strips 20 extending across the width of the region 16 and contacting the isolating wall 18 at each of their ends; and four n+ strips 22 and 24, which act as source and drain zones respectively. The two source strips 22 are covered by the limbs of the U-shaped metal contact 12, which makes electric contact to the strips 22 through slots in the oxide layer of width just less than that of the strips 22; the other portions of the contact 12 are separated by the oxide layer from the underlying silicon.Similarly the two drain strips 24 are covered by the limbs of the other U-shaped metal contact 14, which makes electrical contact to the strips 24 through slots in the oxide layer of width just less than that of the strips 24; the other portions of the contact 14 are insulated by the oxide layer from the underlying silicon.

The JFET of Figure 1 is liable to create RTS noise in operation. This is believed to be due to three factors:firstly to the presence of metal conductors crossing over junctions: where marked A, the metal contact 12 crosses over the region between a source zone 22 and the wall 18 to which the gate strips 20 are connected, which is effectively a source/gate junction; similarly the regions marked B are effectively drain/gate junctions. Secondly the limbs of the contacts 12 and 14 are, in this example, wider than the corresponding source and drain zones 22 and 24 and consequently the metal is adjacent to the active surface regions of the JFET between source and drain zones 22 and 24 and the adjacent gate strips 20 (although separated from those regions by oxide).Thirdly, the slots in the oxide layer whereby the limbs of the contacts 12 and 14 make electrical contact with the corresponding source and drain zones 22 and 24 are so wide that the edges of the slots are less than a micrometre from the edges of the underlying zones 22 and 24; consequently contamination such as metal ions may diffuse from the slot to the active surface region along the interface below the oxide layer.

Referring to Figure la there is shown the variation of gate current with time observed with a commercially available small n-channel low-leakage JFET. The JFET is held at a steady temperature of 291 K (18 OC), the source is held at earth potential, the drain at a steady 5.1 volts, and the gate at a steady -0.4 V. For this particular JFET the mean gate leakage current was 31 femtoamps. Two types of noise are clearly present, one causing variations of no more than about 0.5 fA, and the other, much less frequent, and causing changes at random intervals between two current values differing by about 3 fA. The latter type of noise is that referred to as RTS noise.

Referring now to Figures 2 and 3, a JFET of the invention is shown, defined on a silicon wafer 30. As with the JFET of Figure 1, most of the surface of the wafer 30 is covered by an insulating layer 31 of silicon dioxide, which is not shown in Figure 2 for clarity. The JFET comprises a rectangular region 36 of epitaxial n-type silicon below which is a p+ substrate 37 and around which is an isolating wall 38 of p+ extending up from the substrate 37. Within the rectangular region 36 are also defined further p+ isolating pillars 39, 40, 41 extending up from the substrate 37: two pillars 39 extend inwardly from the wall 38 directly opposite each other, a third pillar 40 is midway between the pillars 39, and two other pillars 41 are spaced apart on a line parallel to but spaced away from the line between the pillars 39.A gate strip 50 is defined near the surface of the region 36 extending along a zig-zag line connecting all the pillars 39, 40, 41 in succession.

A source 52 is defined by an n+ zone near the surface of the region 36, U-shaped in plan, whose limbs extend between portions of the gate strip 50 towards the pillars 41. A drain 54 is defined by another n+ zone, E-shaped in plan, whose outer limbs extend between portions of the gate strip 50 and the wall 38 towards the pillars 39, and whose central limb extends between portions of the gate strip 50 towards the pillar 40. The oxide layer 31 covers the region 36 including the pillars 39, 40, 41, the gate strip 50, and the source and drain zones 52 and 54.

Electrical contact to the source and drain zones 52 and 54 is provided by two square metal contacts 42 and 44 respectively, which overlie the oxide layer 31 above the region 36 and the portions of the zones 52 and 54 remote from their limbs, there being in each case a rectangular slot 46, 48 through the oxide to provide an electrical connection, the edge of the slot 46, 48 being about 4 micrometres away from the edge of the underlying zone 52 or 54 in the direction parallel to the surface.

The JFET of Figures 2 and 3 operates in the same manner as that of Figure 1, external electrical connections being made to the contacts 42 and 44 (for connection to the source and drain) and to the substrate 37 (for connection to the gate 50 via the pillars 39, 40, 41). The active surface regions of the device are the portions of region 36 near the surface, between the source or drain zones, 52 or 54, and the gate strip 50 - for example the portion marked P. The portions of region 36 between the non-limb part of the source or drain zone, 52 or 54, and the isolating wall 38 are not active surface regions because the separations involved are too large - typically more than 20 micrometres - for example the portion marked Q.

It will be observed that the metal contacts 42 and 44 do not cross over any p/n junctions, and are not near the active surface regions of the device.

It will be appreciated that the exact dispositions, numbers of limbs, and sizes of the source, gate and drain may differ from those shown in Figures 2 and 3. In particular a modified version of the JFET (not shown) differs from that shown only in that the n+ zones defining the source and drain 52 and 54 extend over a larger area, slightly larger than the size of the contacts 42 and 44 (the limbs and the slots 46 and 48 being unchanged), so that over its whole area each contact 42 or 44 overlies only the respective zone 52 or 54.

Claims

1. A junction field-effect transistor comprising source, drain and gate zones each comprising a plurality of parallel doped strips all of which strips are substantially coplanar, the transistor having no metal conductors crossing over junctions, and no metal conductors near active surface regions of the transistor, and wherein any metal connection to the gate, the source or the drain zone is spaced at least 1 micrometre away from the edge of the said zone, in a direction parallel to the surface.

2. A junction field-effect transistor substantially as hereinbefore described with reference to, and as shown in, Figures 2 and 3 of the accompanying drawings.