GB2206445A - Method of manufacturing dielectrically isolated integrated circuits and circuit elements - Google Patents
Method of manufacturing dielectrically isolated integrated circuits and circuit elements Download PDFInfo
- Publication number
- GB2206445A GB2206445A GB08715499A GB8715499A GB2206445A GB 2206445 A GB2206445 A GB 2206445A GB 08715499 A GB08715499 A GB 08715499A GB 8715499 A GB8715499 A GB 8715499A GB 2206445 A GB2206445 A GB 2206445A
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- United Kingdom
- Prior art keywords
- layer
- semiconductive
- substrate
- semiconductive material
- meltable
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000463 material Substances 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000012777 electrically insulating material Substances 0.000 claims abstract description 4
- 238000002844 melting Methods 0.000 claims abstract description 4
- 230000008018 melting Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 41
- 230000004888 barrier function Effects 0.000 claims description 13
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 12
- 239000005360 phosphosilicate glass Substances 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims description 2
- 239000011261 inert gas Substances 0.000 claims description 2
- 238000010884 ion-beam technique Methods 0.000 claims description 2
- 150000004767 nitrides Chemical group 0.000 claims description 2
- 238000003486 chemical etching Methods 0.000 claims 1
- 239000011521 glass Substances 0.000 claims 1
- 238000001020 plasma etching Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 235000012431 wafers Nutrition 0.000 description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 229910002804 graphite Inorganic materials 0.000 description 2
- 239000010439 graphite Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000003190 augmentative effect Effects 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021426 porous silicon Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000011819 refractory material Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000011029 spinel Substances 0.000 description 1
- 229910052596 spinel Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
A method of manufacturing a dielectrically isolated integrated circuit or circuit element comprises the steps of:- a) providing a layer (2) of a semiconductive material of a predetermined resistivity and type on a substrate (1) of a relatively low resistivity, b) providing a layer (3) of a meltable, electrically-insulating material on the semiconductive material, the meltable material having a softening temperature lower than the melting point of the semiconductive material, c) providing a carrier (5) for the dielectrically isolated circuit or circuit element, d) bonding the carrier to the layer of meltable material, e) removing a majority of the substrate on which the layer of semiconductive material is provided, and f) removing a predetermined pattern of the semiconductive material to isolate different regions of the semiconductive layer. <IMAGE>
Description
METHOD OF MANUFCTURING DIELECTRICALLY ISOLATED
INTEGRATED CIRCUITS AND CIRCUIT ELEMENTS
This invention relates to a method of manufacturing dielectrically isolated integrated circuits and circuit elements.
It is, of course, well known to effect dielectric isolation in integrated circuits and circuit elements but the methods which have been adopted to date suffer from one or more disadvantages. For example, most known techniques involve precision lapping and polishing to define dielectrically isolated areas; thick layers of polysilicon have to be deposited which is a lengthy process and often inconvenient and likely to cause warpage; the temperature at which integrated circuit processing subsequent to the basic manufacture of the isolation has had to be lower than is convenient.
Furthermore, to retain the integrity of the isolation, ion leakage and relatively short lifespan of minority carriers is another problem with known methods, as is the ability to produce integrated circuits or circuit elements in reasonably sized batches which thus increases the cost of manufacture.
Known methods of manufacturing integrated circuits and circuit elements which suffer from the above advantages are as follows:1. Depositing polysilicon on a semiconductor slice previously formed with oxide patterns and using it as a handle and lapping off the substrate to expose dielectrically isolated areas.
2. Depositing polysilicon on a dielectric and recrystallising by lateral epitaxy.
3. Implanting oxygen or nitrogen to form a buried isolating layer.
4. Porous silicon technology.
5. Epitaxial growth on insulators such as sapphire, spinel, etc.
6. Direct silicon-silicon bonding.
7. Bonding silicon oxide to silicon oxide using an electric field.
The object of the present invention is to provide a method of manufacturing integrated circuits and circuit elements in respect of which the disadvantages associated with known methods are obviated or minimised.
According to the present invention there is provided a method of manufacturing a dielectrically isolated integrated circuit or circuit element comprising the steps of:
a) providing a layer of a semiconductive material of a predetermined resistivity and type on a substrate of a relatively low resistivity,
b) providing a layer of a meltable, electrically-insulating material on the semiconductive material, the meltable material having a softening temperature lower than the melting point of the semiconductive material.
c) providing a carrier for the dielectrically isolated circuit or circuit element,
d) bonding the carrier to the layer of meltable material,
e) removing a majority of the substrate on which the layer of semiconductive material is provided, and
f) removing a predetermined pattern of the semiconductive material to isolate different regions of the semiconductive layer.
Once such dielectrically isolated areas for an integrated circuit or circuit element have been manufactured in accordance with the method of the present invention, the circuit or element can then be processed in a conventional manner.
Preferably, a diffusion barrier is provided between the semiconductive material and the layer of meltable material.
It will be appreciated that the carrier provides the final substrate for the integrated circuit or circuit element once the orginal substrate on which the semiconductive layer has been provided has been removed.
Accordingly, the nature of the substrate is immaterial although it has to be compatible with bonding (both as regards composition and temperature) to the layer of meltable material and is conveniently of low resistivity silicon. In this regard, it is preferable to provide a composite carrier in the form of an electrical insulator provided with a layer of a meltable material compatible, and preferably the same as, the layer of meltable material associated with the semiconductive layer. Thus, the two layers of meltable material are brought together and are readily bonded by bringing to an appropriate temperature, preferably in a vacuum.The meltable material is chosen so that the temperature at which it flows or softens does not exceed the melting point of the semiconductive material which is being employed. ks already mentioned, the insulator of the carrier may be silicon but any inert material, such as a refractory material, may be employed.
The semiconductive material may be silicon, for example, and may be provided on the substrate in the form of a grown epitaxial layer of desired type and resistivity. The substrate may be any electrically insulating material but is conveniently a heavily doped substrate. The diffusion barrier, such as silicon nitride, is provided to prevent any further doping of the substrate or wafer by a constituent part of the meltable material. The meltable material is preferably phospho silicate glass (PSG) or boro phospho silicate glass (BPSG) with the phosphorous content of the PSG preferably being of the order of 8-9%, and with the boron content of the BPSG preferably being of the order of 3% with a phosphorous content of the order of 4%. The diffusion barrier thus prevents doping of the substrate or carrier wafer by the phosphorous or boron of the meltable layers.The phosphorous content needs to be controlled so as to keep the hygroscopic characteristic of the circuit or circuit element within acceptable bounds.
The carrier wafer and the semiconductive part of the circuit or circuit element may be bonded using any conventional process such as one of the following:1. Vacuum furnace process.
2. Wet or dry oxygen or inert gas process under atmospheric or reduced pressure.
3. Rapid thermal processing.
4. Field-assisted bonding in conjunction with any of the bonding techniques 1 to 3 above.
The bonded element preferably has the substrate removed therefrom using a lapping machine, a thickness of substrate being left which is preferably of the order of 10-30 micrometres thick. The remaining substrate may then be masked and etched electrochemically to remove the remaining substrate, followed by the removal of the diffusion barrier, when provided, thus revealing the semiconductive material. If electrochemical etching is employed, this provides an automatic limiter of the etching process in as much as the latter will cease once the semiconductive material of predetermined resistivity is reached. However, other methods of removing the remainder of the substrate in a desired may be employed.
x method of manufacturing a dielectrically-isolated intergrated circuit or circuit element in accordance with the present invention will now be described in greater detail, by way of example, with reference to the accompanying drawings, in which;
Figures 1 to 5 illustrate diagrammatically various stages of manufacture.
Referring first to Figure 1, a silicon single crystal substrate 1 in the form of a heavily doped material and a layer 2 of a semiconductive material is provided thereon. This layer may be an epitaxially grown layer of silicon of a thickness of the order of 2 - 10 micrometres. Next, a diffusion barrier 3 is provided on the semiconductive layer 2, this layer conveniently being of silicon nitride and/or silicon oxide if silicon is used as the semiconductive material. The diffusion barrier 3 is of the order of 50 - 150 nanometres thick.
The diffusion barrier is illustrated in Figure 2 of the drawings, as is a layer 4 of a meltable material which is provided on the diffusion barrier 3. preferably, the meltable material is PSG with a phosphorous content of 8-9% or BPSG with a boron content of 3% and a phosphorous content of 4%. The layer of the BPSG or BPSG is conveniently of the order of 0.5 - 1 micrometres thick.
Next there is separately provided a further insulator of any inert material although preferably in the form of another substrate 5 identical to the substrate 1 and provided with a layer 6 of PSG or BPSG as before. The carrier thus formed by the substrate 5 and layers 6 is then placed with the PSG or BPSG layer in contact with the PSG or BPSG layer of the semiconductive element previously formed and the two components bonded together (Figure 3) using any conventional method such as a vacuum furnace, wet or dry oxygen bonding at atmospheric pressure, or rapid thermal processing. Xny of these methods may be augmented by the field-assisted bonding process which involves applying a voltage across the bonding plane between the two PSG or BPSG layers (or other selected meltable material).
The present invention lends itself to batch production at the bonding stage because a number of wafers and semiconductors elements to be bonded can be placed in a stack one on the other with the substrate of one in contact with the substrate of another because the bonding process will not result in bonding at a substrate-substrate interface but only at the meltable material-meltable material interface of each integrated circuit or circuit element to be formed. This is because there is no "adhesive" between adjacent substrates to affect bonding.
Once bonding has been achieved, the next step in the manufacturing process is to remove the majority of the substrate 1, such as by lapping or any other convenient technique, so as to leave a substrate thickness of the order of 10-30 micrometres (Figure 4). Finally, the remaining substrate 1 is then etched electrochemically to remove the remaining substrate 1 so as to reveal the semiconductive layer 2 which is then etched and/or oxidized to the desired pattern, thus forming isolated areas (Figure 5). Rs the substrate 5 is heavily doped, electrochemical etching will automatically stop on reaching the epitaxial layer of the semiconductive material. Once the desired pattern of semiconductive material has been provided, the integrated circuit or circuit element can then be processed to its final form in a conventional manner.The removal of the remaining substrate I may be accomplished by chemical, electrochemical, plasma, reactive ion beam etching, for example.
more detailed example of a method of manufacturing an integrated circuit or circuit element in accordance with the present invention is given below:
EXAMPLE
A < 111 > silicon substrate heavily doped with boron to resistivity of < .02 ohm-cm having an epitaxial layer of silicon 12 microns thick with a resistivity of 1 ohm-cm was oxidised t a thickness of about 100 angstroms followed by a LPCVD (low ressure chemical vapaour deposition) layer of silicon nitride 1000 xngstroms thick to provide a diffusion barrier. The substrate, as well as all the layers, were optically flat, mirror smooth and free trom any protrusions.Next a layer of PSG was deposited in an APCVD (atmospheric pressure chemical vapour deposition) reactor using silance, phosphine and oxygen in a nitrogen carrier ac 4300C, to a thickness of 1.5 microns. The phosphorous content was estimated to be about 9%.
t similar layer was also deposited on another silicon slice to serve as the carrier. After checking the layers for flatness interferometrically, they were cleaned in sulphuric-peroxide cleaning solution, washed and centrifuged dry, and baked in an oven for 1 hour at 1600C.
The two silicon slices or wafers were laid face to face and placed in a high vacuum furnace having a graphite flat plate heater, and loaded using a quartz plate and a molybdenum block. After an initial bakeout, a vacuum of better than 2 X 10e-6 was obtained. The temperature of the graphite plate was raised to ll000C by passing a current through it, the temperature rising in about 13 seconds and maintained for 5 minutes. After cooling, the wafers were found to be bonded such that they could not be separated without breakage and the bond examined in a SEM (scanning electron microscope) showed no voids of any appreciable size.
x similarly bonded wafer pair was then lapped down to leave about 30 microns of the substrate on the epitaxial side. The remainder of the substrate was electrochemically etched in hydrazine, the etch terminating at the epitaxial interface. A short chemical etch using HF-HN03 was used to remove about 1 micron from the exposed surface. x photoresist pattern corresponding to the desired isolation pattern was then formed on the epitaxial surfaced and the unwanted areas etched in
HF-HN03 till the nitride layer was exposed and terminated the etching. This resulted in the isolated regions being formed in the epitaxial layer and this was confirmed by testing the electrical leakage between the isolated areas.
The use of a meltable material to effect the bonding between the wafer component and the semiconductive component of the overall intergrated circuit or circuit element, especially the use of PSG or BPSG, means that the temperature limitation for subsequent integrated circuit processing is greatly reduced compared with known methods. Furthermore, the meltable material is preferably chosen so as to effect a gettering action and to act as an ion barrier dielectric, thus reducing leakage in the final integrated circuit or circuit element and increasing the lifespan of the minority carriers. k further advantage of the method according to the present invention is the feature, as already mentioned, of being able to bond a stack of devices simultaneously which significantly reduces manufacturing costs. Thus, the present invention affords a very significant advance in the art.
Claims (22)
1. x method of manufacturing a dielectrically isolated integrated circuit or circuit element comprising the steps of:
a) providing a layer of a semiconductive material of a predetermined resistivity and type on a substrate of a relatively low resistivity,
b) providing a layer of a meltable, electrically-insulating material on the semiconductive material, the meltable material having a softening temperature lower than the melting point of the semiconductive material.
c) providing a carrier for the dielectrically isolated circuit or circuit element,
d) bonding the carrier to the layer of meltable material,
e) removing a majority of the substrate on which the layer of semiconductive material is provided, and
f) removing a predetermined pattern of the semiconductive material to isolate different regions of the semiconductive layer.
2. A method according to claim 1, wherein a diffusion barrier is provided between the semiconductive material and the layer of meltable material.
3. A method according to claims 1 or 2, wherein the meltable material is phospho silicate glass.
4. A method according to claim 3, wherein the phospho silicate glass has a phosphorous content in the range of 8-9%.
5. A method according to claim 1 or 2, wherein the meltable material is boro phospho silicate glass.
6. A method according to claim 5, wherein the boro phospho silicate glass has a boron content of 3% and a phosphorous content of 4%.
7. A method according to any of claims 3 to 6, wherein the layer of glass has a thickness in the range of 0.5 -1 micrometres.
8. A method according to any of the preceding claims wherein the substrate is composed of silicon and wherein the layer of semiconductive material is composed of a heavily doped silicon.
9. A method according to claim 2 and any of claims 3 to 8 appended thereto, wherein the diffusion barrier is a nitride.
10. A method according to claim 2 and any of claims 3 to 8 appended thereto, wherein the diffusion barrier is an oxide.
11. A method according to any of the preceding claims, wherein removal of the semiconductive material to provide isolated regions thereof is by electrochemical etching.
12.. x method according to any of the claims 1 to 9, wherein the removal of the semiconductive material to provide isolated regions thereof is by chemical etching.
13. A method according to any of claims 1 to 9, wherein removal of the semiconductive material to provide isolated regions thereof is by plasma etching.
14. A method according to any of claims 1 to 9, wherein removal of the semiconductive material to provide isolated regions thereof is by reactive ion beam etching.
15. A method according to any of the preceding claims, wherein the bonding step is accomplished using a vacuum furnace process.
16. A method according to any of claims 1 to 13, wherein the bonding step is accomplished by a wet or dry oxygen or inert gas process under atmospheric or reduced pressure.
17. A method according to any of claims 1 to 13, wherein the bonding step is accomplished by rapid thermal processing.
18. A method according to any of the preceding claims, wherein the bonding step is accomplished by field-assisted bonding.
19. A method according to any of the preceding claims, wherein the carrier is of a composite nature and comprises an inert substrate provided with a layer of a meltable material.
20. A method according to claim 18, wherein the layer of meltable material on the caRrier substrate is the same as the layer of meltable material on the semiconductive layer.
21. A method of manufacturing a dielectrically isolated integrated circuit or circuit element substantially as herein particularly described with reference to the accompanying drawings.
22. An integrated circuit or circuit element manufactured in accordance with any of the preceding claims.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08715499A GB2206445A (en) | 1987-07-01 | 1987-07-01 | Method of manufacturing dielectrically isolated integrated circuits and circuit elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08715499A GB2206445A (en) | 1987-07-01 | 1987-07-01 | Method of manufacturing dielectrically isolated integrated circuits and circuit elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8715499D0 GB8715499D0 (en) | 1987-08-05 |
| GB2206445A true GB2206445A (en) | 1989-01-05 |
Family
ID=10619913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08715499A Withdrawn GB2206445A (en) | 1987-07-01 | 1987-07-01 | Method of manufacturing dielectrically isolated integrated circuits and circuit elements |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2206445A (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0317445A2 (en) * | 1987-11-20 | 1989-05-24 | Fujitsu Limited | Method for fabricating a silicon carbide substrate |
| EP0378906A1 (en) * | 1988-12-08 | 1990-07-25 | Fujitsu Limited | Method of producing semiconductor-on-insulator structure and semiconductor device having semiconductor-on-insulator structure |
| US5091330A (en) * | 1990-12-28 | 1992-02-25 | Motorola, Inc. | Method of fabricating a dielectric isolated area |
| US5110748A (en) * | 1991-03-28 | 1992-05-05 | Honeywell Inc. | Method for fabricating high mobility thin film transistors as integrated drivers for active matrix display |
| EP0486318A1 (en) * | 1990-11-15 | 1992-05-20 | Seiko Instruments Inc. | Semiconductor device for use in a light valve device, and process for manufacturing the same |
| US5227313A (en) * | 1992-07-24 | 1993-07-13 | Eastman Kodak Company | Process for making backside illuminated image sensors |
| US5231045A (en) * | 1988-12-08 | 1993-07-27 | Fujitsu Limited | Method of producing semiconductor-on-insulator structure by besol process with charged insulating layers |
| US5346848A (en) * | 1993-06-01 | 1994-09-13 | Motorola, Inc. | Method of bonding silicon and III-V semiconductor materials |
| US5407856A (en) * | 1991-05-08 | 1995-04-18 | Fraunhofer Gesellschaft Zur Forderung Der Angewandten Forschung | Direct substrate bonding |
| US5434433A (en) * | 1992-08-19 | 1995-07-18 | Seiko Instruments Inc. | Semiconductor device for a light wave |
| DE4423067A1 (en) * | 1994-07-01 | 1996-01-04 | Daimler Benz Ag | Insulated semiconductor substrate prodn. method |
| EP0697713A1 (en) * | 1994-07-21 | 1996-02-21 | Kabushiki Kaisha Toshiba | Silicon on insulator substrate and method of manufacturing the same |
| US5574292A (en) * | 1992-05-13 | 1996-11-12 | Seiko Instruments Inc. | Semiconductor device with monosilicon layer |
| US5618739A (en) * | 1990-11-15 | 1997-04-08 | Seiko Instruments Inc. | Method of making light valve device using semiconductive composite substrate |
| US5633176A (en) * | 1992-08-19 | 1997-05-27 | Seiko Instruments Inc. | Method of producing a semiconductor device for a light valve |
| EP1775762A3 (en) * | 2005-08-25 | 2007-12-05 | Sumco Corporation | Laminated substrate manufacturing method and laminated substrate manufactured by the method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4530001A (en) * | 1980-09-29 | 1985-07-16 | Oki Electric Industry Co., Ltd. | High voltage integrated semiconductor devices using a thermoplastic resin layer |
-
1987
- 1987-07-01 GB GB08715499A patent/GB2206445A/en not_active Withdrawn
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4530001A (en) * | 1980-09-29 | 1985-07-16 | Oki Electric Industry Co., Ltd. | High voltage integrated semiconductor devices using a thermoplastic resin layer |
Cited By (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0317445A3 (en) * | 1987-11-20 | 1990-01-10 | Fujitsu Limited | Method for fabricating a silicon carbide substrate |
| US4983538A (en) * | 1987-11-20 | 1991-01-08 | Fujitsu Limited | Method for fabricating a silicon carbide substrate |
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| EP1775762A3 (en) * | 2005-08-25 | 2007-12-05 | Sumco Corporation | Laminated substrate manufacturing method and laminated substrate manufactured by the method |
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Also Published As
| Publication number | Publication date |
|---|---|
| GB8715499D0 (en) | 1987-08-05 |
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| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |