GB2199988A - Multi-layer molded plastic ic package - Google Patents
Multi-layer molded plastic ic package Download PDFInfo
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- GB2199988A GB2199988A GB08800089A GB8800089A GB2199988A GB 2199988 A GB2199988 A GB 2199988A GB 08800089 A GB08800089 A GB 08800089A GB 8800089 A GB8800089 A GB 8800089A GB 2199988 A GB2199988 A GB 2199988A
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- plate
- integrated circuit
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- leads
- coupled
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49527—Additional leads the additional leads being a multilayer
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- H01L23/495—Lead-frames or other flat leads
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Abstract
A multi-layered molded plastic package for encapsulating an integrated circuit is described. The package includes a carrier (43) having two metal plates (30, 40) which are separated by an adhesive coated insulation tape. A second insulating tape layer (18) is used to bond externally extending leads (11) onto one of the metal plates. Power and ground connections from the terminals of the integrated circuit are made to respective ones of the plates and power (42) and ground (31) connection tabs of the two plates are connected to respective leads. The power and ground planes remove the requirement for direct physical connection between the power and ground terminals of the integrated circuit and their respective leads. <IMAGE>
Description
MULTI-LAYER MOLDED PLASTIC IC PACKAGE
BACKGROUND OF THE INVENTION
1. Field of the Invention.
The present invention relates to the field of plastic encapsulation of semiconductor devices and more specifically to the encapsulation of multi-lead integrated circuits within a plastic carrier.
2. Prior Art.
During the early development of encapsulating integrated circuits, the integrated circuits were typically packaged in a metal or a ceramic shell. Although ceramic encapsulation is effective, ceramic insulation is costly and reflect a sizable percentage of the total cost of manufacturing an integrated circuit chip. More recently, plastic encapsulation techniques have been devised which substantially lower the cost of packaging an integrated circuit devi'ce.
In a typical plastic packaging technique, an integrated circuit, usually in a form of a die, is placed proximate to a leadframe. The chip or the die is then wired such that~various terminals of the integrated circuit are physically connected to the leads of the leadframe by wires. Next, the integrated circuit chip is bonded and potted such that the chip is encapsulated within the plastic package and only the leads extend externally of the package.
The conventional single-layer molded plastic package using metal leads as known in the prior art typically require one-toone connection of the various integrated circuit terminals on the die to the leads. The number and position of power and ground leads of the package were directly dependent on the' number and position of-the power and ground bond pads on the die. Although multiple connections could be made to the various power and ground leads from the die pads, such practice places additional constraint in positioning the various pads. Also, in certain high current applications, additional pads and leads are needed to shunt the additional current. Increase in the number.
of power and ground pads on the die which result in the increase in the number of leads ultimately cause high electrical inductance and low capacitance to exist between the power and ground pads, such that these properties cause low speed response of the integrated circuit. Further, increase in the number of bond pads on a single layer package dictates an increase in the package lead count resulting in an increase in the size of the package and inhibiting any attempt at package shrink.
Also due to the fact that a single layer molded plastic package is basically flat and causes all I/O (input/output) to ground lead current loops to lie in one plane, cross talk on high lead count packages is appreciably significant to cause communication degradation.
Where prior art single-layer molded plastic packages are quite adequate for various low lead count or low speed integrated cirucuits, a high lead count, high speed integrated circuit implemented in a compact plastic package is difficult to achieve using prior art techniques. It is appreciated then that what is needed is a plastic package for encapsulating a high speed, high lead count integrated circuit, such as a 32-bit microprocessor chip, in a compact system.
SUMMARY OF THE INVENTION
The present invention discloses a multi-layered molded plastic package for encapsulating an integrated circuit. The plastic package includes a multi-layered carrier having a power plane and a ground plane, which are formed from flat metal plates. The power plane operates as a base and the ground plane is disposed to overlie the power plane. A center area of the ground plane is stamped out to provide an opening for the placement of the integrated circuit.
A tape having a polyimide adhesive is used to bond the two plates together and also to act as an insulator. Then a second insulation tape layer using the polyimide adhesive is used to bond leads to the second plate. After attaching the integrated circuit onto the power plane in the opening provided within the ground plane, wires are used to couple power pads on the integrated circuit to the power plane and ground pads to the ground plane.
The use of ground and power planes removes the requirement of directly connecting ground and power terminals to various ground and power leads. The use of the ground and power planes reduces package size, improves thermal performance and reduces lead and mutual inductance.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 shows a leadframe and an adhesive coated insulation tape which is bonded onto the leadframe.
Figure 2 shows a completed assembly of Figure 1.
Figure 3 shows the assembly of Figure 2 after stamping out a center area and removing an inner ring holding various lead tips in place.
Figure 4 shows a ground plane and a second adhesive coated insulation tape.
Figure 5 shows a completed assembly of Figure 4.
Figure 6 shows the completed assembly of Figure 5 with a center opening stamped out.
Figure 7 shows the assembly of Figure 6 being joined to a power plane.
Figure 8 shows the completed assembly of Figure 7.
Figure 9 shows the bonding of the leadframe of Figure 3 and the double-layered plate assembly of Figure 8.
Figure 10 shows the completed assembly of Figure 9.
Figure 11 shows a portion of.the assembly of Figure 10 and the bonding of an integrated circuit and some of its terminal connections.
Figure 12 shows a cross-sectional view of a completed package of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
A multi-layer molded plastic integrated circuit package which provides for a compact encapsulation is described. In the following description, numerous specific details are set forth such as specific shapes, material, etc., in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known techniques have not been described in detail in order not to unnecessarily obscure the present invention.
Referring to Figure 1, a leadframe is shown having a plurality of leads 11 held in place by an outer ring 14. Lead tips 12 are held in place by inner ring 13 to prevent damage to them. Leadframe 10 is constructed from a number of various metals which are well-known in the prior art for constructing leads. Leadframe 10 of the present invention is flat and is formed by stamping or etching it from a desired metal sheet.
Inner ring 13 functions as a boundary for opening 15 at the center of the leadframe 10. Inner ring 13, outer ring 14 and opening 15 of the preferred embodiment is square in shape to accommodate a square-shaped integrated circuit (IC), however, any such shape being arbitrary and determined by the shape of the integrated circuit which will reside within the opening 15.
As practiced with the present invention, the lead tips 12 are silver plated on upper surface 16 by a well-known prior art process for subsequent gold wire bonding.
An insulation tape 18, such as KaptonTM tape manufactured by E.I. du Pont de Nemours & Co., which is coated with a polyimide adhesive on both surfaces 19 and 20 is used.
Polyimide coated tape 18 is cut such that its dimensions are larger than opening 15 of leadframe 10. Surface 19 of tape 18 is placed against non-silver plated side of leadframe 10 such that tape 18 covers opening 15. Leadframe 10 and tape 18 are subjected to a hot tack operation well-known in the prior art to adhere tape 18 to lead frame 10. However, during this hot tack process, the adhesive coating on surfaces 19 and 20 are-not completely cured. Figure 2 shows the completion at the end of the hot tack process, wherein tape 18 and leadframe 10 are joined to enclose opening 15.Although a particular material and adhesive are used in the preferred embodiment, it is appreciated that ot:#icr insulators alld adllesives well-knowll ill the prior art will perform an equivalent function.
Referring to Figure 3, a center opening 23 is formed by stamping out a portion of tape 18 and inner ring 13. At this stage tape 18, having an opening 23, is attached to lead tips 12. The various leadtips 12 are separated from each other due to the removal of inner ring 13. The boundary dimensions of opening 23 must be of such size as to accommodate an IC chip or die within opening 23. At this stage of manufacture, assembly 24 is formed.
Referring to Figure 4, a metal plate 30 is stamped to have dimensions substantially similar to the dimensions of tape 18 of
Figure 1. Plate 30 of the preferred embodiment is formed from a copper material and is silver plated on one surface 32. Plate 30 includes tabs 31 which will mate with appropriate leads 11 of leadframe 10 of Figure 3. Tabs 31 are raised slightly from the plane of plate 30. Tabs' 31 surfaces are treated by a metallurgical process, such as gold or nickel plating, to help bond tabs 31 to leadframe 10. The preferred embodiment uses gold plating on tabs 31. Then, tape 35 having polyimide adhesive on both sides is cut to match the dimensions of plate 30 and then by the use of the polyimide adhesive as previously explained in reference to Figure 1 is mated to the non-plated side 33 of plate 30 by the hot tack process.The resulting attachment of plate 30 to tape 35 is shown in Figure 5 as unit 37.
Referring to Figure 6, opening 36 is stamped in plate unit 37. Opening 36 has dimensions to enable IC die to be placed within. However, opening 36 has dimensions which are smaller than opening 23 of Figure 3 such that portion of surface 32 of unit 37 will reside within opening 23 when properly mated.
Referring to Figure 7, a metal plate 40 constructed from a material equivalent to that of plate 30 of Figure 4, is stamped to have dimensions substantially equivalent to that of plate 30.
In the preferred embodiment opposing corners 41 are notched to have a slight angular cut. Tabs 42 are formed in an equivalent manner to that of tabs 31 of plate 30 of Figure 4 to mate with various corresponding leads 11 which will be coupled to plate 40. Tabs 42 are positioned at separate locations than tabs 31.
Plate unit 37 is mated to plate 40 such that polyimide coated tape 35 is sandwiched between plate 30 and 40. The completed combination of mated plate 30, tape 35 and plate 40 is shown in
Figure 8 as assembly 43.
Referring to Figure 9, assembly 24 is now mated to assembly 43 such that tape 18 is sandwiched between leadframe 10 and plate 30. The completed assembly 45, having a center area 46, is shown in Figure 10. The preferred embodiment is comprised of a substantially flat and square assembly 45, although such shape being arbitrarily dependent on the size and #shape of the integrated circuit being encapsulated. Then, assembly 45 is cured under thermo-compression to permanently join all elements 10, 18, 30, 35, 40. Assembly 24 is comprised of plate 40 which functions to provide a base for area 46. Tape 35 and plate 30 overlie plate 40. Next, tape 18 and leads 11 of leadframe 10 overlie plate 30, such that a portion of plate 30 is exposed.
In the preferred embodiment, plate 40 forms a power plane 52 and plate 30 forms a ground plane 53.
The tabs 31 and 42 when properly formed will extend past the outer boundary of tape 18. Due to the slight rise, the tabs 31 and 42 will extend from its respective plates 30 and 40 to mate with various corresponding leads 11 along their underside.
The tabs 31 and 42 are bonded to the leads 11 by using one of various prior art methods, such as parallel gap welding, ultrasonic bonding, compliant bonding, wobble bonding, or thermo-compression (pulsed solder reflow).
Referring to Figure 11, an IC in a form of a die 50 is placed within the center area 46 to lie upon power plane 52. A variety of prior art techniques, such as adhesive die attach, is utilized to bond die 50 onto power plane 52. Wires 55 are used to couple pad 57 on die 50 to power plane 52 and wires 54 are bonded to couple pads 58 to ground plane 53. Other wires, such as wire 56, are used to couple other pads 59 of die 50 to various leads at lead tip 12.
Referring also to Figure 12, the proper positioning of the various tabs 31 and 42 in the earlier formation of the ground and power planes is apparent in that tabs 31 and 42 mate with appropriate leads 11 to couple the ground plane 53 and the power plane 52. In the preferred embodiment, tabs 31 and 42 are bonded prior to the placement of wires 54-56 as earlier described. Although only one of the ground plane tabs 31 is shown in the Figures 11 and 12, the other ground tabs 31 and power tabs 42 are mated to their respective leads 11 in an equivalent manner. The various wire bondings are accomplished by bonding wires 54-56 to the silver spot-plated planes 52-53 and to the silver-plated lead tips 12.
It is appreciated that various bonding techniques or configurations may be utilized to practice the present invention. In an alternate embodiment, instead of using tabs 31 and 42 at the outer edge of the planes 52 and 53, heavy gage wires may be utilized to interconnect the ground and the power planes at lead tips 12. Further, decoupling capacitors can be surface mounted on the plane between the power and the ground plane. Finally, the complete unit is encapsulated in a plastic package 60 by a well-known stamping and forming process used in the manufacture of semiconductor devices, outer ring 14 of lead frame 10 is removed and various leads 11 are separated to form individual leads 11 of an IC package. Assembly 45 is worked by a well-known conventional plastic package assembly technique.
Various advantages are derived due to the performance improvement of the present invention. A critical improvement is that the inductance of power and ground paths of the IC will be drastically reduced, because major portions of the lead length is replaced by low inductance metal planes. Capacitance of the power and ground paths will also increase to a value typically near 100 pF thereby helping to reduce noise in the power supply.
As stated earlier, decoupling capacitors can be placed within the package connecting the ground and power planes to further reduce the lead inductance of the IC. The lead inductance is determined, not only by the leads 11, but also by the lead length in the external circuit. That is, the presence of the ground and power planes will reduce the inductance of various
I/O lines which will be coupled to the leads 11 of the IC and will aid in maintaining a more uniform value of inductance per unit length. Therefore, the present invention will result in a package which will not be highly geometry dependent as was the case in prior art devices without the use of ground and power planes.
Unlike in prior art plastic packages without the use of ground and power planes, the present invention does not require a one-to-one connection of the power and ground terminals on the die to the leads, thereby p#roviding independent control over the position and number of the ground and power terminals on the die and on the package leads. Also, because of the favorable gains in the package inductance and capacitors the number of ground and power leads required for equivalent performance is much less compared to prior art devices.
The overall contribution of the various advantages in performance will result in smaller package sizes for the device.
The use of metal plates as ground and power planes also contributes to the distribution of heat generated by the IC, thereby presenting a thermal performance improvement. For "hot devices" this will eliminate the need for internal "heatspreaders".
Other advantages which result from the practice of the present invention are as follows: During the manufacturing process, the lead tips in the leadframe are protected by adhesive coated tapes and by the metal ring, thereby preventing damage. When tabs are used, the ground and power lead tips need not be present for wire bonding such that the ground and power lead tips can be cut back with respect to other lead tips, freeing crucial real estate near the IC wire bonding areas.
Further,-die pads no longer need the support of tie bars, such that further real estate is available for additional I/O leads.
Also, mutual inductance between the leads, as well as between the I/O lines, will be reduced because current loops between power and ground potential occur perpendicular to the planes and not between the leads, as was the case in the prior art.
Thus a multi-layer plastic package for encapsulating an integrated circuit is described.
Claims (15)
1. A carrier for a semiconductor device, comprising:
a first conducting plate;
an insulator coupled to said first plate and overlying at least a portion of said first plate;
a second conducting plate coupled to overlie said first insulator such that said first insulator is disposed between said first and second plates;
said semiconductor device having its first terminal coupled to said first plate and having a second terminal coupled to said second plate;
a first lead coupled to said first plate;
a second lead coupled to said second plate;
an encapsulating shell surrounding said carrier such that said leads extending externally of said shell;
whereby said semiconductor device having its first and second terminals electrically coupled to said first and second leads, respectively, by said plates.
2. The carrier defined in Claim 1, wherein said insulation is comprised of an adhesive coated insulation tape.
3. The carrier defined in Claim 2, wherein said plates are comprised of copper.
4. A plastic package for an integrated circuit, comprising:
an opaque plastic encapsulating shell;
an integrated circuit carrier encapsulated within said shell;
a plurality of leads extending into said shell and coupled to said carrier;
said carrier comprising:
(a) a first conducting plate, wherein said integrated circuit is disposed on said first plate;
(b) a second conducting plate overlying said first plate and disposed about said integrated circuit;
(c) a first insulator disposed between and bonded to said first and second plates;
(d) a second insulator disposed between and bonded to said second plate and said plurality of leads;
(e) wherein power terminals of said integrated circuit' are electrically coupled to one of said plates; and
(f) wherein ground terminals of said integrated circuit are electrically coupled to other of said plates;
whereby said ground and power terminals are coupled to ground and power leads by each of 'said plates, respectively.
5. The plastic package defined in Claim 4, wherein said insulators are comprised of adhesive coated insulation tape.
6. The plastic package defined in. Claim 5, wherein said plates are comprised of copper.
7. The plastic package defined in Claim 6, wherein said power terminals of said integrated circuit are coupled to said first plate and said ground terminals are coupled to#said second plate.
8. The plastic package defined in Claim 7, wherein said first and second plates further including tabs disposed on its outer edge for coupling said plates to various predetermined power and ground leads.
9. The plastic package defined in Claim 8, wherein said adhesive is comprised of polyimide.
10. The plastic package defined in Claim 9, wherein other terminals of said integrated circuit are selectively coupled directly to lead tips of various predetermined corresponding leads.
11. The plastic package defined in Claim 10, wherein said carrier is substantially flat.
12. The plastic package defined in Claim 11, wherein said carrier is rectangular in shape to hold a substantially rectangular-shaped integrated circuit.
13. The plastic package defined in Claim 7, wherein a capacitor is coupled between said first plate and said second plate for decoupling purposes.
14. A method of encapsulating an integrated circuit in a plastic package;
comprising the steps of:
preparing a leadframe having a plurality of leads disposed therein, said leadframe having a central opening for placement of said integrated circuit;
cutting an adhesive coated insulation tape to fit over said opening;
bonding said insulation tape to said leadframe to form a leadframe assembly;
stamping a center opening in said tape;
cutting a first plate;
cutting a second adhesive coated insulation tape;
bonding said second insulation tape to said first plate;
stamping out a center opening in said second tape and said first plate;
cutting a second plate;
bonding said second plate to said second insulation tape such that said second tape is disposed between said first and second plates; ;
bonding said first plate to said first tape such that said first tape is disposed between said first plate and said leadframe;
bonding said integrated circuit to said second plate;
bonding wires to various terminal pads on said integrated circuit;
terminating other end of said wires to various leads of said leadframe and to said first and second plates;
encapsulating in a plastic shell;
whereby ground and power terminals of said integrated circuit are coupled to ground and power leads by said first and second plates.
15. A carrier for a semiconductor device, substantially as hereinbefore described with reference to the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US214487A | 1987-01-12 | 1987-01-12 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8800089D0 GB8800089D0 (en) | 1988-02-10 |
| GB2199988A true GB2199988A (en) | 1988-07-20 |
| GB2199988B GB2199988B (en) | 1990-04-25 |
Family
ID=21699416
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8800089A Expired - Lifetime GB2199988B (en) | 1987-01-12 | 1988-01-05 | Multi-layer molded plastic ic package |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2779620B2 (en) |
| GB (1) | GB2199988B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2665799A1 (en) * | 1990-08-08 | 1992-02-14 | Mitsubishi Electric Corp | Encapsulated semiconductor device with improved heat removal |
| EP0545007A1 (en) * | 1991-11-29 | 1993-06-09 | STMicroelectronics S.r.l. | A semiconductor device structure having a heat-sink and a plastics body, and highly reliable means of electrical connection to the heat-sink |
| EP0562629A2 (en) * | 1992-03-26 | 1993-09-29 | Sumitomo Electric Industries, Limited | Semiconductor device comprising a package |
| EP0645810A1 (en) * | 1993-04-06 | 1995-03-29 | Tokuyama Corporation | Package for semiconductor chip |
| GB2293918A (en) * | 1994-10-06 | 1996-04-10 | Ibm | Electronic circuit packaging |
| GB2324198A (en) * | 1997-04-09 | 1998-10-14 | Nec Corp | Tape-fixed leadframe |
| WO2002063684A2 (en) * | 2001-02-02 | 2002-08-15 | Stratedge Corporation | Single layer surface mount package |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2532039B2 (en) * | 1987-05-29 | 1996-09-11 | 新光電気工業株式会社 | High frequency semiconductor device |
| JPH0793406B2 (en) * | 1989-10-06 | 1995-10-09 | 株式会社三井ハイテック | Lead frame manufacturing method and semiconductor device using the same |
| JPH07112039B2 (en) * | 1991-03-14 | 1995-11-29 | 日立電線株式会社 | Multi-pin multi-layer wiring lead frame |
| JP2745887B2 (en) * | 1991-08-29 | 1998-04-28 | 日立電線株式会社 | Resin-sealed semiconductor device |
| JPH0563130A (en) * | 1991-08-30 | 1993-03-12 | Sumitomo Special Metals Co Ltd | Lead frame and manufacture thereof, and semiconductor package |
| JP2570584B2 (en) * | 1993-07-30 | 1997-01-08 | 日本電気株式会社 | Semiconductor device |
| JP2536459B2 (en) * | 1994-09-26 | 1996-09-18 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| JP2811170B2 (en) * | 1996-06-28 | 1998-10-15 | 株式会社後藤製作所 | Resin-sealed semiconductor device and method of manufacturing the same |
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| GB1245710A (en) * | 1968-12-25 | 1971-09-08 | Hitachi Ltd | Case for containing a semiconductor element |
| US3784883A (en) * | 1971-07-19 | 1974-01-08 | Communications Transistor Corp | Transistor package |
| GB1499889A (en) * | 1974-03-06 | 1978-02-01 | Rca Corp | High frequency semiconductor device |
| US4168507A (en) * | 1977-11-21 | 1979-09-18 | Motorola, Inc. | Structure and technique for achieving reduced inductive effect of undesired components of common lead inductance in a semiconductive RF power package |
| GB2107116A (en) * | 1981-09-24 | 1983-04-20 | Junkosha Co Ltd | Temperature sensing device with high resistance connecting leads |
| US4639760A (en) * | 1986-01-21 | 1987-01-27 | Motorola, Inc. | High power RF transistor assembly |
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- 1988-01-05 GB GB8800089A patent/GB2199988B/en not_active Expired - Lifetime
- 1988-01-12 JP JP63003264A patent/JP2779620B2/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1245710A (en) * | 1968-12-25 | 1971-09-08 | Hitachi Ltd | Case for containing a semiconductor element |
| US3784883A (en) * | 1971-07-19 | 1974-01-08 | Communications Transistor Corp | Transistor package |
| GB1499889A (en) * | 1974-03-06 | 1978-02-01 | Rca Corp | High frequency semiconductor device |
| US4168507A (en) * | 1977-11-21 | 1979-09-18 | Motorola, Inc. | Structure and technique for achieving reduced inductive effect of undesired components of common lead inductance in a semiconductive RF power package |
| GB2107116A (en) * | 1981-09-24 | 1983-04-20 | Junkosha Co Ltd | Temperature sensing device with high resistance connecting leads |
| US4639760A (en) * | 1986-01-21 | 1987-01-27 | Motorola, Inc. | High power RF transistor assembly |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2665799A1 (en) * | 1990-08-08 | 1992-02-14 | Mitsubishi Electric Corp | Encapsulated semiconductor device with improved heat removal |
| US5763296A (en) * | 1991-11-21 | 1998-06-09 | Sgs-Thomson Microelectronics S.R.L. | Method for fabricating an electronic device structure with studs locating lead frame on backing plate |
| EP0545007A1 (en) * | 1991-11-29 | 1993-06-09 | STMicroelectronics S.r.l. | A semiconductor device structure having a heat-sink and a plastics body, and highly reliable means of electrical connection to the heat-sink |
| US5338971A (en) * | 1991-11-29 | 1994-08-16 | Sgs-Thomson Microelectronics, S.R.L. | Electronic device structure with studs locating lead frame on backing plate |
| EP0562629A2 (en) * | 1992-03-26 | 1993-09-29 | Sumitomo Electric Industries, Limited | Semiconductor device comprising a package |
| EP0562629A3 (en) * | 1992-03-26 | 1994-03-09 | Sumitomo Electric Industries | |
| EP0645810A1 (en) * | 1993-04-06 | 1995-03-29 | Tokuyama Corporation | Package for semiconductor chip |
| EP0645810A4 (en) * | 1993-04-06 | 1997-04-16 | Tokuyama Corp | PACKAGE FOR SEMICONDUCTOR CHIP. |
| GB2293918A (en) * | 1994-10-06 | 1996-04-10 | Ibm | Electronic circuit packaging |
| GB2324198A (en) * | 1997-04-09 | 1998-10-14 | Nec Corp | Tape-fixed leadframe |
| US5969412A (en) * | 1997-04-09 | 1999-10-19 | Nec Corporation | Tape-fixed leadframe |
| GB2324198B (en) * | 1997-04-09 | 2001-10-17 | Nec Corp | Tape-fixed leadframe and fabrication method thereof |
| WO2002063684A2 (en) * | 2001-02-02 | 2002-08-15 | Stratedge Corporation | Single layer surface mount package |
| WO2002063684A3 (en) * | 2001-02-02 | 2003-09-18 | Stratedge Corp | Single layer surface mount package |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8800089D0 (en) | 1988-02-10 |
| JPS63246851A (en) | 1988-10-13 |
| GB2199988B (en) | 1990-04-25 |
| JP2779620B2 (en) | 1998-07-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PE20 | Patent expired after termination of 20 years |
Effective date: 20080104 |