GB2196787A

GB2196787A - Semiconductor chip manufacture

Info

Publication number: GB2196787A
Application number: GB08626134A
Authority: GB
Inventors: Roger Leslie Baker; George Hedley Storm Rokos; Trevor Kenneth Monk; David William Mcneill
Original assignee: STC PLC
Current assignee: STC PLC
Priority date: 1986-10-31
Filing date: 1986-10-31
Publication date: 1988-05-05
Also published as: GB8626134D0

Abstract

The need often arises to have on the same chip a number of bipolar transistors of different sizes. To do this, each "large" transistor is made up of two or more "small" transistors connected in parallel. The process involves doing most of the chip manufacture with a set of common masks, which can be regarded as semi-customisation, whereafter a single mask is used to apply metallisation to the chip to parallel-connect the transistors to give the required transistor sizes. This is described in its application to merged technology. <IMAGE>

Description

SPECIFICATION Semiconductor chip manufacture This invention relates to the manufacture of bipolar transistors on an integrated circuit chip, especially when using polysilicon doping techniques.

According to the invention, there is provided a a method of manufacturing bipolar transistors in an integrated circuit chip, in which a common mask set is used to define a number of transistors in the same chip, in which subsequent to the doping using the respective masks of said set a metallisation step is undertaken using a further mask to produce transistors of the required sizes by connecting adjacent transistors in parallel to produce transistors of the sizes required, such that transistors of different sizes can be produced, and in which the further mask is a customised mask for a combination of transistors needed for a specific chip.

Embodiments of the invention will now be described with reference to the accompanying drawings, in which Fig. 1 illustrates schematically the doping techniques usable in an embodiment of the invention, while Fig. 2 shows how several, in this case four, separately-deposited transistors can be joined together in parallel to produce a single large transistor.

Polysilicon doping techniques have been much used in the production of integrated circuit chips, especially where the same chip has to incorporate both bipolar and MOS transistors. Such chips are said to use merged technology. However, the present invention is applicable to other techniques for chip manufacture. It will be seen that by the use of this technique we can produce on a chip a range of bipolar transistors which cover many lowvoltage applications. Thus we use a common mask set for producing a range of what may be termed "semi-customised" chips. Then a single metallisation layer is applied to a chip which is specific to the desired chip. Thus this single layer, which is applied via a mask intends specifically for it, provides the customised part of the process.Such a common mask set, plus individual metallisation masks, covers a great many discrete devices for each chip or die size.

Merged technology, as referred to above and using polysilicon sources, makes available high emitter doping levels. Hence it is possible to produce devices which combine high cut-off frequencies with reasonable current gains, or very high gain with a good cut-off frequency, the "trade-off" being assisted by the fine geometry structure used. The devices also have low reverse current gain, with the result that saturation times should be quite short, in spite of the high forward gains recorded. Even individual devices could therefore cover a wide range of gerenic specifications.

To achieve a high range of capability from a given mask set, multiple transistor structures can be built onto a standard sized die, which structures are connected individually or in parallel to get the device area and collector series resistances needed. Thus in such a die one would produce groups of individual transistor structures, all of a standard size, and then as a separate step connect some of those structures in parallel to produce transistors of different sizes. If it is convenient, the original production using the common mask set could produce transistors of two or more sizes, which could be parallelled as required.

Thus the main mask set is used to produce all of the dies of a particular size and particular characteristics, in a "semi-customised" manner whereafter each die is further treated via a "dedicated: metallisation mask to set up the desired inter-transistor connections. This gives the required device areas and collector series resistances. Hence the mask used for this metallisation provides the full customisation.

The above operation is in addition to the doping techniques already established for adjusting the frequency/noise resistance/gain performance of the basic transistors involved.

Discrete transistors are normally implanted on an epitaxial substrate, but the range of such devices may be extended to those with higher breakdown voltages than those now proposed. This involves doping of N-epitaxial layer uniformly with a deep but low-level 0 diffusion before creating the local emitter-base structures. These can also be diffused through the standard base masks if a top collector contact is needed. Oxide layers are then thicker than those produced by standard CMOS processors to minimise the parasitic capacitances of the bond pads and metallic interconnections.

We now discuss Fig. 1, which indicates schematically the various processing steps which have to be done to implement the techniques discussed above.

Initially, Fig. 1(a), a substrate 1 is doped N+, and has an epitaxial layer 2 of N- silicon grown on its upper surface. Then, Fig. 1(b), a first mask is used to produce P base implants such as 3 in the epitaxial layer. These base implants are produced via a mask indicated at 4. The epitaxial layer is now coated with an oxide layer 5.

Windows are now cut in the oxide layer, and polysilicon is applied, as shown at 6. This is implanted with arsenic and etched via a mask, indicated at 7, Fig. 1(c). Then we have the emitter drive in and activation, and diffusion of dopant. Next implants are made in the N- layer, Fig. 1(d), where p+ and n+ regions (if needed) are produced. These are near the surface of the epitaxial layer 2, and are the p+ and n+ contact implants for the base and collector electrodes. Metallisations are now produced, Fig. 1(e), to give the pattern of interconnected transistors needed.

Fig. 2 shows the arrangement of two metallised regions on a chip, produced as described above by the final, or "custom" mask One of these metallisations, 10 interconnects four base regions, while the other, 11, interconnects four emitter regions. With the substrate acting as the collector contact, this effectively gives four transistors connected in parallel to give a large area transistor.

Claims

1. A method of manufacturing bipolar transistors in an integrated circuit chip, in which a common mask set is used to define a number of transistors in the same chip, in which subsequent to the doping using the respective masks of said set a metallisation step is undertaken using a further mask to produce transistors of the required sizes by connecting adjacent transistors in parallel to produce transistors of the sizes required, such that transistors of different sizes can be produced, and in which the further mask is a customised mask for a combination of transistors needed for a specific chip.

2. A method as claimed in claim 1, and in which the transistors are made using polysilicon doping techniques.

3. A method of manufacturing bipolar transistors in an integrated circuit chip, substantially as described with reference to the accompanying drawings.

4. An integrated circuit chip in the manufacture of which the method of claim 1, 2 or 3 is used.

CLAIMS Amendments to the claims have been filed, and have the following effect: New or textually amended claims have been filed as follows:

5. A method of manufacturing bipolar transistors in an integrated circuit chip, in which a common mask set is used to define a number of transistors in the same chip, in which each said transistor has first, second and third electrodes, in which subsequent to the doping using the respective masks of said set a metallisation step is undertaken using a further mask to produce transistors of the required sizes by connecting adjacent transistors in parallel to produce transistors of the sizes required, in which each said transistor is produced by connecting in parallel a plurality of adjacent first electrode regions and by connecting in parallel a plurality of adjacent second electrode regions, the chip's substrate acting as a third electrode contact, such that transistors of different sizes can be produced, and in which the further mask is a customised mask for the combination of transistors needed for a specific chip.

6. A method as claimed in claim 5, in which the first electrodes are emitters, the second electrodes are bases and the third electrodes are collectors.