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GB2195048A - Semiconductor packages and connection techniques for use therewith - Google Patents

Semiconductor packages and connection techniques for use therewith Download PDF

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Publication number
GB2195048A
GB2195048A GB08621183A GB8621183A GB2195048A GB 2195048 A GB2195048 A GB 2195048A GB 08621183 A GB08621183 A GB 08621183A GB 8621183 A GB8621183 A GB 8621183A GB 2195048 A GB2195048 A GB 2195048A
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United Kingdom
Prior art keywords
housing
lead
package
semiconductor device
electrical connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB08621183A
Other versions
GB8621183D0 (en
Inventor
Simon Mansey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
INT RECTIFIER CO Ltd
Infineon Technologies Americas Corp
Original Assignee
INT RECTIFIER CO Ltd
International Rectifier Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by INT RECTIFIER CO Ltd, International Rectifier Corp USA filed Critical INT RECTIFIER CO Ltd
Priority to GB08621183A priority Critical patent/GB2195048A/en
Publication of GB8621183D0 publication Critical patent/GB8621183D0/en
Publication of GB2195048A publication Critical patent/GB2195048A/en
Withdrawn legal-status Critical Current

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    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
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    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

A lead 10 extends through the wall 11 of a housing for a semiconductor device 21, and an aluminium wire is bonded ultrasonically to the end of the lead while that end is supported by support 15 against the lateral bonding load. The wire is then bonded to the device 21. <IMAGE>

Description

SPECIFICATION Semiconductor packages and connection techniques for use therewith The present invention relates to semiconductor packages, methods of manufacturing the same, semiconductor packages produced by the method, methods of ultrasonic bonding, and methods of supporting a lead in a semiconductor package.
It is conventional in the semiconductor industry to supply semiconductor devices in the form of semiconductor wafers in which the semiconductor device itself is incorporated, the wafer providing one or more bonding pads for connection of electrical leads to the semiconductor device. Before such a wafer may be commercially used, or sold, it is necessary to package the wafer, often referred to as a die, within some form of housing. Such a housing containing the semiconductor device is often referred to as a "package". Such a package may be hermetically sealed and in order to allow the semiconductor device to communicate with the outside world it is necessary to provide connection pins which extend through a wall of the outer housing and are internally connected to the bonding pads of the die.
For purposes of good heat extraction from the semiconductor device, it is conventional to construct the housing of a good heat conducting metal. Since it is of course essential that the electrical conductors communicating with the semiconductor device are electrically insulated from the housing, it is conventional to provide an electrical insulator surrounding a pin at the point where it passes through the wall of the housing. Such an electrical insulator may be a glass compound which is genera#lly satisfactory and provides excellent insulation but which is however subject to cracking if the pins are subjected to a lateral load.
A very convenient method of connecting the bonding pads of the die to the inner ends of the pins within the package is the technique known as ultrasonic bonding. However, in order for this technique to succeed it is necessary for a certain minimum contact pressure to be developed between the two surfaces which are to be bonded. When used for the internal connection wires of a semiconductor package constructed as described above, this may lead to cracking of the above mentioned glass insulation or breaking of the glass to metal seal. Breaking of the seal is itself a problem if the package is intended to be hermetically sealed as required for some applications.
An object of the invention is to provide a semiconductor package having connection leads more resistant to lateral loading.
A further object of the invention is to provide a semiconductor package whose internal connections can be reliably effected by ultrasonic bonding.
Another object of the invention is to provide a method of ultrasonic bonding which avoids the cracking problems described above.
Another object of the invention is to provide a method of laterally supporting a lead in a semiconductor package.
According to one aspect of the present invention, there is provided a semiconductor package comprising: an electrically conductive housing; a semiconductor device mounted within said housing; a connection zone on said device; a lead passing through and electrically insulated from a wall of said housing; a support member disposed adjacent a portion of said lead within the housing to resist lateral forces applied to said portion; and an electrical connection extending from said lead to said connection zone.
The connection zone may be a bonding pad and the electrical connection may be electrically connected to said lead and said bonding pad by means of an ultrasonically effected bond.
According to another aspect of the invention, there is provided a method of supporting a lead in a semiconductor package comprising an electrically conductive housing, a semiconductor device mounted within the housing and a lead extending through a wall of said housing and electrically insulated therefrom, in which method a support member is disposed adjacent a portion of said lead within the housing to resist lateral forces applied to said portion.
According to another aspect of the invention, there is provided a method of manufacturing a semiconductor package comprising: providing an electrically conductive housing; mounting a semiconductor device having a connection zone within said housing; passing a lead through a wall of said housing; electrically insulating said lead from said wall; disposing a support member adjacent a portion of said lead within the housing to resist lateral forces applied to said portion; and forming an electrical connection from said portion to said connection zone by means of ultrasonic bonding.
Another aspect of the invention provides a semiconductor package manufactured by said method.
According to a further aspect of the invention, there is provided a method of ultrasonic bonding in which an electrically conductive connection member is pressed against an electrical connection lead by means of an ultrasonic bonding tool whilst said lead is supported by means of a support member and said ultrasonic bonding tool is energised to effect an ultrasonic bond.
In any of the above aspects of the invention, the support member may be an electrically insulating insert or it may be an extension of a substrate on which the semiconduc tor device is mounted.
Said substrate may be a layer of electrically insulating material provided with at least one copper layer on at least one major surface thereof. Preferably, said substrate has a copper layer on which major surface thereof which is divided into a plurality of portions, on one of which the semiconductor device is mounted and to another of which said lead is bonded.
Bonding of the substrate to the copper layer may be by means of the technique referred to as direct bonding copper. Bonding of the lead to the copper layer may be by means of the technique referred to as brazing.
The substrate may be of beryllia, aluminium nitride, or aluminium oxide.
The semiconductor device may be a power MOSFET, such as the device manufactured by the international Rectifier Corporation and known as a "Hexfet".
The electrical connection extending from the lead to the connection zone of the semiconductor device may have a thickness of 0.020in (0.5 mm). A force of one kilogram is required to bond such a wire to the lead. The electrical connection is preferably of aluminium to effect a satisfactory ultrasonic bond.
The invention is applicable inter alia to packages of the type referred to as hermetic flatpacks.
For a better understanding of the invention, and to show #how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings, in which: FIGURE 1a illustrates a plan view of a known semiconductor package; FIGURE 1 b shows a cross-sectional view of the package of Figure la; FIGURE 2 shows a method of ultrasonic bonding according to a first embodiment of the present invention; FIGURES 3a and 3b show further details of the embodiment according to Figure 2; FIGURE 4 shows a lateral view partially in section of a semiconductor package illustrating a connection technique according to a second embodiment of the present invention; FIGURE 5 shows a plan view of the semiconductor package illustrated in Figure 4;; FIGURE 6 shows a side view partially in section of a semiconductor package illustrating a connection technique according to a third embodiment of the present invention; and FIGURE 7 shows a plan view of the semiconductor package according to Figure 6.
Reference will first of all be made to Figures 1a and 1 b which illustrate respectively a plan view and a cross-sectional view of a hermetic semiconductor package of the T0220 type.
The package comprises a metal can 1 having a securing flange 2 which is effective as a heat sink, and three terminal pins 3,4 and 5 which extend through one wall of the housing 1 and are insulated therefrom by means of glass to metal seals 6,7 and 8. It will be noted that each pin has a portion internal of the can to which an electrical connection wire may be connected.
Such a housing assembly may be used for packaging a semiconductor die, such as a field effect transistor. By forming the base of the housing 1 of material having high thermal conductivity, it is possible to utilise such a housing assembly for high power applications.
When the die is mounted within the housing, it is conventional to connect the internal ends of the pins 3,4 and 5 to the semiconductor device comprised in the die by means of electrical connection wires and one method of effecting such connection is ultrasonic bonding. In this technique, a bonding tool presses an aluminium wire into contact with a surface to which it is to be bonded and is caused to vibrate at ultrasonic frequencies whilst contact pressure between the wire and the surface for bonding is maintained above a predetermined value. For a wire of 0.5mm diameter, a contact force of about 1 kilogram is required to form an effective bond.
If such a force is applied to the inner end of the pins 3,4 and 5 illustrated in Figures la and 1b, there is severe danger of cracking the glass to metal seals 6,7 and 8. Whilst this might not necessarily destroy the electrical insulation properties, it would certainly prevent the package from achieving its desired hermetic properties.
Reference will now be made to Figure 2 which illustrates an ultrasonic bonding technique which may be employed according to one embodiment of the invention. An electrical connection pin 10 extends through a wall 11 of an electrically conductive housing and is insulated therefrom by means of a glass to metal seal 12. On its interior end 13, the pin 10 is provided with a flattened region 14 which is supported by an electrically insulating support member 15 which itself is supported partially by a base wall 16 of the housing and partially by an electrically insulating substrate 17 which will support the die. An aluminium connection wire 18 is supplied from a wire discharge nozzle 19 to the desired point of connection on the pin 13 and is pressed into contact therewith by means of an ultrasonic bonding tool 20. Owing to the presence of the support member 15, the large contact force which is required between the wire 18 and the pin 13 does not lead to cracking or other damage to the glass to metal seal 12 since the contact force is absorbed by the support member 15 and partially by the substrate 17.
It will be recalled from Figure la that three connection pins 3,4 and 5 are provided in the conventional package illustrated. In the embodiment illustrated partially in Figure 2, it is also envisaged that three pins will be pro vided. In this embodiment, -the two outer pins will be connected as illustrated in Figure 2, but the central pin will be connected somewhat differently since it is intended that the central pin will be braded to an electrical conduction path on the ceramic substrate 17.
This is illustrated in Figure 3a, whilst Figure 3b illustrates a corresponding view of the construction adopted for the outer pins and corresponds to Figure 2.
In Figures 3a and 3b, a die 21 is also illustrated in position on the substrate 17.
The central pin 10a is in Figure 3a supported by a support member 15a and the internal end 13a of the pin 10a is provided with a flattened surface 14a. During bonding, the ultrasonic bonding tool 20 will be applied to the flattened face 14a to effect bonding between the end 13a and a copper layer provided on the substrate 17.
in the embodiment illustrated in Figure 3b, it will be appreciated that each of the outer pins 10 will be connected to a respective corresponding bonding pad on the die 21 by means of a connection wire such as wire 18 of Figure 2.
Figure 4 illustrates semiconductor package construction in which the separate support member 15 or 15a of Figures 3a and 3b is unnecessary and support is provided instead by means of an extension of the substrate.
Referring to Figure 4 in more detail, a connection pin 40 passes through a wall 41 of a housing 42 and is insulated therefrom by means of a glass to metal seal which is not illustrated in Figure 4. An internal end 43 of the pin 40 is provided with a flattened region 44 and is supported by means of a copper layer 45 on a substrate 46 which in turn is supported by a lower copper layer 47 abutting a lower wall 48 of the housing 42.
On the upper surface of the substrate 46, a further copper layer 49 supports a die 50.
Connection between} the end 43 and the copper layer 45 as well as between the layer 47 and the wall 48 is by means of brazing. A soft solder joint connects the die 50 to the layer 49. It will be appreciated that copper layers 45 and 49 are formed by etching from a single copper layer originally applied to the substrate 46. Extending from the end 43 to a bonding pad on the die 50 is an aluminium wire 51 of 0.5mm diameter. The wire 51 is connected to the die 50 by means of a first ultrasonic bond 53 and is connected to the pin 40 by means of a second ultrasonic bond 52. The ultrasonic bonds are formed by means of an ultrasonic bonding tool such as tool 20 illustrated in Figure 2.
Figure 5 illustrates a plan view of the semiconductor package 42 illustrated in Figure 4.
In Figure 5, the two outer pins and the components electrically associated therewith are provided with the same reference numerals as provided in Figure 4. Figure 5 illustrates more clearly that the wires 51 are connected to bonding pads 54 on the die 50. A central pin 60 is bonded directly to a copper layer 61 which forms part of the layer 49 illustrated in Figure 4. Thus, by means of this connection, the pin 60 is connected to a terminal on the lower side of the die 50 via the copper layer 49. Pin 60 is connected to the central copper bonding pad 61 by means of brazing. Thus, since no ultrasonic bond is required for pin 60, the presence of the supporting region of the substrate having copper layer 61 is not strictly necessary. However, its presence gives rise to a more robust construction.
As an alternative to providing a support member beneath the internal end of the connection pins, cracking of the glass to metal seals may also be prevented simply by avoiding the need to apply lateral forces to the pin.
An embodiment which achieves this effect is illustrated in Figure 6. A connection pin 70 passes through a wall 71 of a housing 72 and has an internal end 73. Within the housing, an electrically insulating substrate 74 is mounted on a lower wall 75 of the housing 72 with the inter-position of a copper layer 76. On the upper surface of the substrate 74, several copper layers are provided, two of which have reference numerals 77 and 78 and appear in Figure 6. All the copper layers on the upper surface of the substrate 74 are formed by etching from a single copper layer originally covering the majority of the upper face of the substrate 74. Copper region 78 supports the internal end 73 of the pin 70 and also one end of an aluminium connection wire 79 of 0.5mm diameter.The other end of the wire 79 is connected to a bonding pad of a die 80 which is supported by the copper region 77.
The die 80 is connected to region 77 by means of soft solder whereas the end 73 of the pin 70 is connected to the copper region 78 by means of brazing. A brazed joint also connects the lower copper layer 76 to the wall 75. As in the embodiment illustrated in Figures 4 and 5, the aluminium wire 79 is connected at each end by means of an ultrasonic bond. In this case however whilst one end is bonded to a bonding pad on the die as in the preceding embodiment, the other end is bonded directly to the copper layer 78 and not to the end 73 of the pin 70. Thus, during loading by the ultrasonic bonding tool, no lateral forces are applied to the pin 70 so that there is no danger of cracking the glass to metal seal. A robust construction is provided by supporting both the end 73 and the aluminium connection wire 79 by means of the copper layer 78 on an extension of the substrate 74.
Figure 7 shows a plan view of the embodiment of Figure 6 and corresponding components are provided with the same reference numerals, the components illustrated in Figure 6 corresponding to the two outer pins of the assembly.
Figure 7 also illustrates the central pin 80 connected to a copper region 81 which is part of the copper region 77 illustrated in Figure 6.
It will be appreciated that in the embodiment of Figure 6 and 7, the internal ends of the pins are all formed substantially identically and all are brazed to respective copper regions 78 or 81. The internal ends of the pins are thus well supported and protected against any lateral loading which may inadvertently be applied to the internal ends. The outer pins 70 are electrically connected via the copper regions 78 and the aluminium wires 79 to respective bonding pads 82 and 83 on the upper surface of the die 80.
Thus, by means of the present invention, cracking of glass to metal seals provided between connection pins and walls of the semiconductor package is avoided either by absorbing lateral loading by a support member or by avoiding the need to apply such lateral loading.
In all the illustrated embodiments, the insulating substrate on which the die is mounted may be of beryllia, aluminium nitride or aluminium oxide. Although not illustrated in the figures, it will be appreciated that when completed each semiconductor package will be en -closed by an upper wall and thus hermetically sealed.
The die m#ay comprise a power MOSFET such as the device sold under the name "Hexfet" by the International Rectifier Corporation.
The invention is not however limited to such uses and may find application in any situation where a robust construction providing effective support for internal ends of connection pins is required.

Claims (18)

1. A semiconductor package comprising: a housing; a semiconductor device mounted within said housing; a connection zone on said device; a lead passing through and electrically insulated from a wall of said housing; and an electrical connection electrically connected to said lead and extending to said connection zone.
2. A package as claimed in claim 1 in which the electrical connection is electrically connected to said lead by means of an ultrasonically effected bond.
3. A package as claimed in claim 2, in which a support member is disposed adjacent a portion of the lead within the housing to resist lateral forces applied to the portion.
4. A package as claimed in claim 1 or claim 2 or claim 3 in which the electrical connection is connected to the connection zone by means of an ultrasonically effected bond.
5. A package as claimed in claim 1 or claim 4 in which the lead is electrically connected to a conducting surface of a substrate, and the electrical connection is connected to that conducting surface by means of an ultrasonically effected bond.
6. A package as claimed in any of the preceding claims in which the electrical connection is an aluminium or other wire.
7. A semiconductor package constructed and arranged substantially as herein specifically described with reference to any of Figures 3, 4 and 6 of the accompanying drawings.
8. A method of supporting a lead in a semiconductor package comprising an electrically conductive housing, a semiconductor device mounted within the housing and a lead extending through a wall of said housing and electrically insulated therefrom, in which method a support member is disposed adjacent a portion of said lead within the housing to resist lateral forces applied to said portion.
9. A method as claimed in Claim 8 in which an electrical connection from said portion to a connection zone on the semiconductor device is formed by means of ultrasonic bonding.
10. A semiconductor package manufactured by a method as claimed in either of claims 8 and 9.
11. A method of ultrasonic bonding in which an electrically conductive connection member is pressed against an electrical connection lead by means of an ultrasonic bonding tool whilst said lead is supported by means of a support member and said ultrasonic bonding tool is energised to effect an ultrasonic bond.
12. A package as claimed in any of claims 1 to 6, or a method as claimed in any of claims 8 to 11, in which the support member is an electrically insulating insert.
13. A package as claimed in any of claims 1 to 6 or a method as claimed in any of claims 8 to 11 in which the support member is an extension of a substrate on which the semiconductor device is mounted.
14. A package or method as claimed in claim 13 in which the substrate is a layer of electrically insulating material provided with at least one copper layer on at least one major surface thereof
15. A package or method as claimed in claim 13 in which the substrate has a copper layer which is divided into a plurality of portions, on one of which the semiconductor device is mounted and to another of which said lead is bonded.
16. A method of connecting a lead passing through and insulated from a wall of a housing to a semiconductor device mounted within the housing in which an electrical connection is ultrasonically bonded to a portion of the lead within the housing while the portion is supported to resist the lateral forces for effecting the bond.
17. A method of connecting a lead passing through and insulated from a wall of a housing to a semiconductor device mounted within the housing, in which an electrical connection is ultrasonically bonded to a conducting surface of a substrate within the housing, and a portion of the lead within the housing is connected to that conducting surface.
18. A method of connecting a lead passing through and insulated from a wall of a housing to a semiconductor device mounted within the housing performed substantially as herein specifically described with reference to any of Figures 3, 4 and 6 of the accompanying drawings.
GB08621183A 1986-09-02 1986-09-02 Semiconductor packages and connection techniques for use therewith Withdrawn GB2195048A (en)

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Application Number Priority Date Filing Date Title
GB08621183A GB2195048A (en) 1986-09-02 1986-09-02 Semiconductor packages and connection techniques for use therewith

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GB2195048A true GB2195048A (en) 1988-03-23

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4262165A (en) * 1976-03-26 1981-04-14 Hitachi, Ltd. Packaging structure for semiconductor IC chip
EP0084866A2 (en) * 1982-01-21 1983-08-03 Olin Corporation Semiconductor casing
EP0114917A2 (en) * 1982-12-29 1984-08-08 Olin Corporation Semiconductor packages
US4572924A (en) * 1983-05-18 1986-02-25 Spectrum Ceramics, Inc. Electronic enclosures having metal parts
US4649415A (en) * 1985-01-15 1987-03-10 National Semiconductor Corporation Semiconductor package with tape mounted die

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4262165A (en) * 1976-03-26 1981-04-14 Hitachi, Ltd. Packaging structure for semiconductor IC chip
EP0084866A2 (en) * 1982-01-21 1983-08-03 Olin Corporation Semiconductor casing
EP0114917A2 (en) * 1982-12-29 1984-08-08 Olin Corporation Semiconductor packages
US4572924A (en) * 1983-05-18 1986-02-25 Spectrum Ceramics, Inc. Electronic enclosures having metal parts
US4649415A (en) * 1985-01-15 1987-03-10 National Semiconductor Corporation Semiconductor package with tape mounted die

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