GB2191352A

GB2191352A - Frequency synthesiser

Info

Publication number: GB2191352A
Application number: GB08613784A
Authority: GB
Inventors: Christopher Jacques Beale; Nicholas Paul Cowley
Original assignee: Plessey Co Ltd
Current assignee: Plessey Co Ltd
Priority date: 1986-06-06
Filing date: 1986-06-06
Publication date: 1987-12-09
Also published as: GB8613784D0

Abstract

A locked-loop frequency synthesiser for use in a TV tuning system, comprising a local oscillator 2 for producing an output signal which is fed to a programmable element and signal comparator 42, which may be a divider or a counter. Synchronisation means 40 is provided for ensuring that the transfer of control data to the programmable element only takes place during a period when the programmable element is in its quiescent state in relation to a comparison cycle of the reference oscillator 14. During one cycle of the reference oscillator 14 signal, switch 40 is closed and the number of cycles of the local oscillator 2 signal occurring is counted by 42 to produce an error signal via charge pump 19 for controlling oscillator 2. During the next cycle switch 40 is open and data may be fed to 42 to change the division ratio. <IMAGE>

Description

SPECIFICATION Frequency Synthesisers The present invention relates to frequency synthesisers.

Known types of frequency synthesisers, when used as part of a TV tuning system may give rise to a detrimental picture ripple during programming of the programmable dividers or counters, etc. The picture ripple may be particularly bad during a 'fine tune' stage, when the frequency synthesiser is being optimally aligned to the incoming signal. The ripple occurs during a data load sequence because the information presented to the programmable dividers, etc., during that data load sequence is incorrect. Consequently, erroneous division occurs and hence the synthesised frequency becomes incorrect. The synthesis loop then has to correct for this error, which gives rise to a 'glitch' in the demodulated video.

Presently known methods of overcoming this fault involve either disabling the divider chains in the frequency synthesiser during the data load sequence or arranging for the divider chains to accept new data only when all bits have been updated.

Both of the above known methods provide an improvement to the TV tuning system, though the system is still not optimised since in both cases when division is reenabled the programmable dividers may start dividing in the wrong part of their cycle and hence lead to a tuning 'glitch' (see Figure 2).

An object of the present invention is to provide a frequency synthesiser which overcomes these inadequacies.

According to the present invention there is provided a frequency synthesiser comprising a local oscillator for producing an output signal which is afforded to a signal comparator via a programmable element, the signal comparator providing a control signal for the local oscillator, synchronisation means being provided for controlling the transfer of data to the programmable element whereby the data is acquired by the programmable element in a predetermined time dependent relationship to the cycle of a reference signal.

In a preferred embodiment the synchronisation means controls the transfer of data in a manner such that the data is acquired by the programmable element during a period when the programmable element is in its quiescent state in relation to the reference cycle.

In one embodiment the programmable element is a divider programmable by means of a shift register to which the divider is coupled, the shift register being adapted to receive programming data in the form of bit binary codes. The signal comparator may be in the form of a phase/frequency comparator, the phase/frequency comparator providing the control signal for the local oscillator in the presence at the phase/frequency comparator of a phase difference between the reference signal and the signal afforded to the phase/frequency comparator from the programmable divider.

In a further embodiment the programmable element is in the form of a counter programmable by means of a shift register to which the counter is coupled, the shift register being adapted to receive programming data in the form of bit binary codes.

In said further embodiment the signal comparator may be in a form enabling comparison between a reference number stored within the programmable counter and a counted number of cycles of the signal received by the programmable counter originating from the local oscillator over a period dependent on the cycle of the reference signal, the control signal provided by the signal comparator being dependent on the difference between the reference number and the counted number of cycles.

The present invention will be described further, by way of examples, with reference to the accompanying drawings in which: Figure 1 is a schematic block diagram of a known frequency synthesiser; Figure 2 is a pulse train diagram illustrating how a phase error between signals fed to a phase comparator may arise in the frequency synthesiser of Figure 1; and Figure 3 is a pulse train diagram illustrating the phase between the signals fed to the phase comparator in the circuit of Figure 1 utilising the present invention; and Figure 4 is a schematic block diagram of a further embodiment of the present invention.

Referring to Figure 1 the frequency synthesiser is provided with a phase locked loop circuit which in this specific example is provided on an integrated circuit chip the edge of which is illustrated by the dashed line 1. A voltage controlled local oscillator 2 is located off chip and provides an output signal which is fed as an input signal to the chip via an input terminal 3. The local oscillator signal presented at the terminal 3 is fed via a preamplifier 4 and a prescaler 5 to a programmable divider 6. The programmable divider 6 provides an output signal along a line 10 to an input of a phase/frequency comparator 12.

The programmable divider 6 is coupled to a shift register 8 which receives programming data in the form of binary codes fed along a line 9, the shift register 8 acting as a program store for the programmable divider 6. Clock pulses are fed along a line 11 to the shift register 8.

A reference source in the form of a reference oscillator 14 and a reference divider 16 serve to provide a reference signal along a line 15 to a second input of the phase/frequency comparator 12.

A control signal for the local oscillator 2 is provided along a feedback line 18, via a charge pump 19 and an amplifier 28, when there is a phase difference between the reference signal Fref and the signal Fpd afforded to the phase/frequency comparator 12 along the line 10. A loop filter 29 is arranged in parallel with the amplifier 28 and the feedback line 18 is coupled to a line 20 external to the chip and connecting the local oscillator 2 with a varactor diode 22.

As can be seen by comparing the pulse trains in Figure 2 a phase error E may be introduced through data being loaded into the programmable divider 6 by the data shift register 8. The phase error E occurs when the programmable divider 6 restarts transmitting its output signal at the wrong instant in relation to the reference cycle.

In a preferred embodiment of the present invention the data acquisition to the programmable divider 6 occurs between the end of one reference cycle and the start of the next reference cycle without disabling any element within the feedback loop. This is accomplished by providing a synchronisation means controlling the transfer of data during a data load window period when the programmable element is in its quiescent state in relation to the reference cycle.

By synchronising in this manner the programmable dividers are only updated immediately before the start of each reference cycle and so will never enter into an erroneous division sequence after data load. Also as the data acquisition is synchronised to the start of the reference cycle, then minimum phase disturbance is introduced between the two inputs to the phase/ frequency comparator 12 and hence minimum ripple on the demodulated video.

A further embodiment of the present invention will now be described with reference to Figure 4, common features of Figures 1 and 4 being identified by the same reference numerals.

Referring to Figure 4 the frequency synthesiser is provided with a frequency locked loop circuit which is provided on an integrated circuit chip. As in Figure 1 the voltage controlled local oscillator 2 is located off chip and provides an output signal which is fed as an input signal to the chip via the input terminal 3. In this embodiment however the input signal is afforded to a switch 40 via the preamplifier 4 and the prescaler 5, the output signal from the reference divider 16 closing the switch 40 for a sequence of gated periods. The output signal from the prescaler 5 is therefore afforded to a programmable counter and signal comparator 42 under the control of the output signal from the reference divider 16.The number of signals transmitted through the switch 40 during one of the gating periods are counted and compared with a reference number within the counter and signal comparator 42. A digital representation of the comparator output is used to control the charge pump 19. The output of the charge pump 19 is fed back to control the frequency of the local oscillator 2, the feedback being via the amplifier 28 and the filter 29 in the same manner as in Figure 1.

In operation the counter is preset to a known data word before the start of each signal gate period. The known data word may be a predetermined word, for example all O's, or a word loaded from the data shift register 8. The counter then counts cycles of the received signal within the gated period. The number of cycles counted is then compared with a reference data word. The reference data word would in the instance of an all O's load be the number in the data shift register, or for the instance of the data shift register load would be all O's. The frequency error is therefore expressed as the difference between the reference number and the counted number of cycles, and this difference word is used to control the magnitude of the charge pump current into the amplifier 28 and the filter 29. An important feature of this embodiment is the provision of means for synchronising the presetting of the counter to the known data word before the start of each signal gate period.

Although the present invention has been described above with respect to two particular embodiments, it should be understood that modifications may be effected within the scope of the invention. For example, the invention may be applied to all frequency synthesisers in which frequency reference is used as part of the synthesiser circuit, and regardless of type, application, or method of data transmission.

Claims

1. A frequency synthesiser comprising a local oscillator for producing an output signal which is afforded to a signal comparator via a programmable element, the signal comparator providing a control signal for the local oscillator, synchronisation means being provided for controlling the transfer of data to the programmable element whereby the data is acquired by the programmable element in a predetermined time dependant relationship to the cycle of a reference signal.

2. A frequency synthesiser as claimed in Claim 1 wherein the synchronisation means controls the transfer of data in a manner such that the data is acquired by the programmable element during a period when the programmable element is in its quiescent state in relation to the reference cycle.

3. A frequency synthesiser as claimed in Claim 1 or Claim 2 wherein the programmable element is a divider programmable by means of a shift register to which the divider is coupled, the shift register being adapted to receive programming data in the form of bit binary codes.

4. A frequency synthesiser as claimed in Claim 3 wherein the signal comparator is a phase/frequency comparator, the phase/frequency comparator providing the control signal for the local oscillator in the presence at the phase/frequency comparator of a phase difference between the reference signal and the signal afforded to the phase/frequency comparator from the programmable divider.

5. A frequency synthesiser as claimed in Claim 1 or Claim 2 wherein the programmable element is in the form of a counter programmable by means of a shift register to which the counter is coupled, the shift register being adapted to receive programming data in the form of bit binary codes.

6. A frequency synthesiser as claimed in Claim 5 wherein the signal comparator is in a form enabling comparison between a reference number stored within the programmable counter and a counted number of cycles of the signal received by the programmable counter originating from the local oscillator over a period dependent on the cycle of the reference signal, the control signal provided by the signal comparator being dependent on the difference between the reference number and the counted number of cycles.

7. A frequency synthesiser substantially as hereinbefore described with reference to Figures 1 and 3 or 3 and 4 of the accompanying drawings.

8. ATVtuning system incorporating a frequency synthesiser as claimed in any one of Claims 1 to 7.