GB2178627A - Power line carrier communications system - Google Patents

Abstract

A system for formatting an input byte-wide data stream into an output message bit stream for transmission over a power line for and for extracting an output byte-wide data stream from an input message stream received over a power line. The system includes format means responsive to consecutive, parallel data bytes occurring in an input byte-wide data stream for generating a preamble portion of a serial output message bit stream, converting the input byte-wide data stream into a data portion of the output message bit stream and generating a checksum portion of the output message bit stream. The system further includes extraction means responsive to a serial input message bit stream having a preamble portion, a data portion and a checksum portion for extracting from the input message bit stream data portion an output byte-wide data stream including consecutive, parallel data bytes.

Description

SPECIFICATION Power line carrier communications system BACKGROUND OF THE INVENTION I. Field of the Invention The present invention relates to power line carrier communications systems. More particularly, the present invention relates to a novel method and apparatus for formatting messages and extracting data from messages so as to achieve enhanced noise immunity in a power line carrier communications system.

II. Background Art Power line communications systems have recently become a viable alternative as a communications link in many applications. Although various other data links such as optical, RF, ultrasonic and hardwire links have advantages in certain areas each one has limitations upon its applicability. For example, optical links operate only by line of sight, RF links are restricted by numerous regulations, ultrasonic links are interrupted by walls, and hardwired links require costly installation of signal carrying lines. With the power line carrier communication system as an alternative, pre-existing AC power lines may be utilized in the communications link.

In many applications such as building energy management schemes, power line communications systems enable the retrofitting of existing buildings to become a fairly simple task. By using the AC power line, no aftermarket installation is required for installation of remote control models which control energy consuming devices such as compressors, motors, heating and air-conditioning and lighting.

These remote control units and additional sensor units may communicate over the power line.

Utilization of the AC power line as a communications medium permits data to be transferred directly over the AC power line along with the normal AC current. The AC power line not only contains the typically 117 volt RMS of unwanted signal but also kilo-volt spikes which presents fundamental design challenges for carrier current transceiver circuits. In industrial environments unwanted noise from motors, compressors and other industrial equipment generate even greater amounts of noise which may cause errors in the data transmitted over the power lines.

At low data rates such as 1200 baud, power line carriers, current transceivers and data processors are currently able to handle noise immunity. However, as the baud rates increase, such as to 2300 baud, noise on the power line becomes an increased factor in causing erroneous data.

It is therefore an object of the present invention to provide a novel and improved power line communication system capable of operating at increased baud rates with enhanced immunity to noise related data errors.

It is yet another object of the present invention to provide a highly reliable power line communications message format standard for transmission and receiving of data.

SUMMARY OF THE INVENTION The present invention relates to a power line carrier communications data formatter that permits the formatting of parallel data for serial transmission over a power line. In addition, the formatter extracts from serial data received over the power line parallel data which may then be processed. A microcontroller is used for formatting an input bytewide data stream into an output message bit stream for serial transmission over a power line. The microcontroller extracts an output byte-wide data stream from a serial input message bit stream received over the power line.The microcontroller under program control comprises format means responsive to consecutive, parallel data bytes occurring in the input byte-wide data stream for generating a preamble portion of a serial output message bit stream, converting the input byte-wide data stream into a data portion of the serial output message bit stream and generating a checksum portion of the output message bit stream. Extraction means are included that is responsive to a serial input message bit stream having a preamble portion, a data portion and a checksum portion for extracting from the input message bit data portion an output byte-wide data stream including consecutive, parallel data bytes. The format means computes the output message checksum frgm the data bytes occurring in the input byte-wide data stream.The extraction means synchronizes with the input message bit stream and computes a checksum value corresponding to the bits and the received data portion of the input message bit stream and compares the computed checksum value with the bits in the checksum portion of the input message bit stream, and provides byte-wide output data upon verification of the checksum.

The system further comprises transceiver means for converting the output bit stream into a frequency-shift keyed output message bit stream and also converting an input frequency-shift keyed message bit stream to a corresponding serial binary bit stream. Coupling means are included for coupling the signals from the transceiver onto the power line and coupling signals from the power line into the transceiver. Sampling means are included for conditioning an input message bit stream from the transceiver to the extraction means.

Carrier detect means are included for enabling the extraction means to process an input data bit stream in response to detecting the input message data bit stream.

Utilization of the microcontroller of the pre sent invention in the power line communications systems permit data transfer over a power line at increased baud rates with less susceptibility to noise.

BRIEF DESCRIPTION OF THE DRAWINGS The objects, advantages, and features of the present invention will be more fully apparent from the detailed description set forth below, taken in conjunction with the accompanying drawings in which like reference characters correspond throughout and wherein: Figure 1 is a schematical block diagram of a typical power line carrier communications system; Figure 2 is a schematical block diagram of an exemplary pair of control modules utilizing the power line carrier communications system of the present invention and associated waveforms; Figure 3 is a schematical diagram of the power line carrier transceiver circuitry and carrier detect circuitry; Figure 4 is a schematical diagram of the data sampling circuitry and microcontroller circuitry; Figure 5 is a graphical representation of the message format utilized in the present invention;; Figure 6 is a graphical representation of the bit period sample timing.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1 illustrates in block diagram form a store energy management system. Store input power, for example 480 volts thr ee phase power, is provided on power lines 10 and 12 to provide power to store equipment such as heating, ventilation, air-conditioning equipment (HVAC) and refrigeration equipment. The store input power is coupled by line 12 into transformer 14 which steps down the voltage of the input power and in this example would typically be 208 volts three phase power. The 208 volt power may be used for lighting and various other store equipment. Respectfully coupled to power line 10 by line 18 and 20 are binary control modules 22 and 24. Binary control modules 22 and 24 use the power line 10 and 16 as a communications network for communicating with other modules.Binary control modules 22 and 29 control the equipment drawing power from power line 10. Similarly, Binary control modules 26 and 28 are respectively coupled by lines 30 and 32 to power line 16. Binary control modules 26 and 28 communicate with each other on power line 16 and with other modules on power lines 16 and 10. Binary control modules 26 and 28 control the equipment drawing power f rom power line 16.

To provide communication coupling between different power voltage levels, i.e. around transformer 14, and differently phased lines bridge 34 is provided. Bridge 34 provides on lines 36 and 38 the data messages provided by the modules around transformer 14.

A store computer interface module 40 is coupled by line 42 to line 16. Store computer interface module 40 permits communication access by store computer 44 which is coupled to store computer interface module 40 by line 46. Store computer 44 may be utilized to download control parameters and provide data accessing for report generation of the energy management status. Operator interface to the store computer is provided by CRT terminal 48 which is coupled by line 50 to store computer 44. In addition, printer 52 is coupled to store computer 44 by line 54 so as to provide hard copy reports on system status.

Analog input modules (AIM) 56 and 58 are respectively coupled to line 16 by line 60 and 62. Analog input modules 56 and 58 are coupled to analog sensors such as temperature and pressure sensors (not shown). The analog input modules provide data to the binary control modules for computation of equipment control commands.

Figure 2 illustrates in block diagram form the communications portion of an exemplary pair of binary control modules (BCM) 100 and 102. Module 100 includes a microprocessor 102 which transmits and receives data via line 104 to microcontroller 106. Data is formatted by microcontroller 106 for transmission on line 108 to transceiver 110. Transceiver 110 modulates the digital data into an analog signal for coupling over power line 112.

When receiving a message from module 102 the transceiver 100 converts the analog signal into digital form which is coupled over lines 114 to sampler 116. Sampler 116 provides a data signal on 118 to microcontroller 106. Carrier detector 120 is utilized in combination with transceiver 110 to detect the presence of a valid carrier on the power line.

The carrier detector is utilized in the system because of contention which is an inherent possibility in a multiple modular system. Upon detection of a valid carrier signal, carrier detector 120 provides an enabling signal on line 122 to microcontroller 106 for enabling the microcontroller to process the data received through the transceiver 110 via sampler 116.

Module 102 is similar to module 100 in that a transceiver 126 and carrier detector 128 are coupled to the power line. The output of the transceiver 126 is coupled by line 130 to sampler 132. The output of sampler 132 is coupled by line 134 to microcontroller 136.

Microcontroller 136 is also respectively coupled to transceiver 126 and carrier detector 128 by lines 138 and 140. Data is coupled between microcontroller 136 and microprocessor 144 via line 142.

In Figure 2 an exemplary transmitted message segment is illustrated as being coupled on line 108 from microcontroller 106 to tran sceiver 110. In the transmitted message segment on line 108, bits i and i+2 are illustrated as being logic level "0" while bits i+l and i+3 are logic level "1". When the transmitted message segment is coupled onto the power line 112, spurious noise induced on the power line by motors, compressors and other electrical equipment, may occur simultaneously with message transmission. This noise may cause errors in the data or rejection of the message as being invalid.

With module 100 transmitting a message, module 102 along with all other modules on the network will receive the message. A received message segment on line 130 of module 102 corresponds to the transmitted message segment on line 108 of module 100.

The received message segment is characterized by spurious noise pulses during the bit periods. For example during the period of bit noise pulse 150 occurs. Similarly, during bit i+1, noise pulses 152 and 154 are evident while during bit i+2 noise pulses 156 and 158 occur. The received message segment is conditioned by sampler 132, whose operation is described later, so as to provide a substantially noise-free message segment corresponding to the transmitted message segment. With the conditioned message segment input to microcontroller 136 from sampler 132, via line 134, the chances of microcontroller 136 interpreting the bit incorrectly are substantially reduced. Without sampler 132 being utilized, microcontroller 136 may erroneously interpret a noise pulse, such as noise pulse 154 during bit i+1, as a valid logic state in the message.

Utilizing the sampler 132, received messages are conditioned so as to remove any such noise pulses from the bits, thereby eliminating an erroneous reading of data.

Figure 3 illustrates the transceiver circuitry and carrier detect circuitry. In Figure 3, data is transmitted through lines A, B and C of the input AC power line where it is coupled through capacitors 200a-200c into winding 202 of transformer 204 to the neutral line N.

Each capacitor 200a-200c isolates the input AC power line phases, A-C, from one another while permitting data transfer onto each phased line. A second winding 206 of transformer 204 is inductively coupled to winding 202. One end of winding 206 is coupled to a positive 18 volt potential and through capacitor 208 to ground. Capacitor 210 is coupled between the ends of winding 206. Capacitor 210 and winding 206 form a tank circuit which attenuates noise in the message. The other end of winding 206 is coupled through resistor 212 to point 214. The transformer coupling circuitry described respectively couples the transmitted and received power line carrier signals to/from the power lines and module. It is envisioned that the module may be coupled to a single line phase.

Point 214 is coupled to the cathode of zener diode 216 having its anode coupled to ground. Point 214 is also coupled to the carrier input/output terminal (CARI/O) of power line carrier transceiver 218. Transceiver 218 is typically a carrier current transceiver manufactured by National Semiconductor Corporation of Santa Clara, Calif ornia being part number LM1893. The operation of transceiver 218 is described in the publications "A New Carrier Current Transceiver l.C." by Mitchell Lee, IEEE Transactions on Consumer Electronics, Part 1, Volume CE-28, No.3, August 1982; and "A Carrier Current Transceiver I.C.

f or Data Transmission over the AC Power Lines" by Dennis M.

Miticelli and Michael E. Wright, IEEE Journal of Solid State Circuits, Volume SC-17, No. 6, December 1982.

Transceiver 218 converts a digital bit stream signal received at a transmit data input (TXD) into a frequency-shift keyed modulated analog signal output when a logic high or "1" signal is input to a transmit/receive select input (Tx/Rx). The Tx/Rx input is coupled to a positive 5 volt potential through resistor 226.

The transmitted signal is output from transceiver 218 and coupled through a boost stage external to transceiver 218.

The boost stage includes resistor 220 which is coupled across the base and emitter of transistor 222 which has a base coupled to the transceiver boost base terminal (BB) and an emitter coupled to the transceiver boost emitter terminal (BE). The collector of transistor 222 is coupled to point 214. The emitter of transistor 222 is coupled through resistor 224 to ground.

When in the receiving mode, the Tx/Rx input is driven by a logic low or "0" signal. A carrier signal input from point 214 at the CARPI/0 input is provided as a serial frequency-shift keyed (FSK) bit stream. The transceiver converts the FSK data into digital form such that at a receive output (RXD) a corresponding serial digital bit stream is present.

A display circuit associated with transceiver 218 is used to indicate when the transceiver is in the transmit or receive mode. The display circuit is comprised of inverter 228 having an input coupled to the Tx/Rx input with its output coupled to the cathode of LED 230. The anode of LED 230 is coupled through pull-up resistor 232 to a positive 5 volt potential.

When the Tx/Rx signal is high, transmit mode, LED 230 conducts providing illumination indicative of the transmit mode. The receive data (RXD) output is similarly coupled through pull-up resistor 238 to a positive 5 volt potential.

The Tx/Rx input is also connected to the anode of zener diode 234. The cathode of diode 234 is connected to capacitor 236 to ground and to resistor 237 to the input (ALC) of transceiver 218. This portion of the transceiver circuitry is used to control the auto matic level control circuit of transceiver 218.

Power supplied to transceiver 218 is typically positive 18 volts and is provided to a V+ input. The V+ input is also coupled to ground through parallel connected capacitors 240 and 242. Transceiver 218 includes an internal 5.6 volt reference zener diode at a Z input which is connected to a positive 18 volt potential through resistor 244. Capacitor 246 is coupled across CAP 1 and CAP 2 inputs along with the FREQ input coupled to ground through series connected resistor 248 and potentiometer 250 which establish the carrier center frequency. A limiter filter input (LF) is coupled through capacitor 252 to ground.

Similarly, an off set hold capacitor input (OHCAP) and the noise integrator input (NI) are respectively coupled to ground through capacitors 254 and 256. A transceiver phase lock loop filter input (PLLF1) is coupled to a second phase lock loop filter (PLLF2) through series connected resistor 258 and capacitor 260.

Carrier detect means are connected to point 214 through switch or jumper 262. A series connected capacitor 264 and resistor 266 couple through jumper 262 point 214 to the noninverting input of amplifier 268. The noninverting input of amplifier 268 is also coupled through resistor 270 to ground. Back to back diodes, diodes 272 and 274, are coupled between the non-inverting input of amplifier 268 and ground so as to limit the signal amplitude into the carrier detect circuit when the transceiver is transmitting onto the power line.

Series capacitor 264 and resistor 266 are included in the carrier detect circuit to prevent shorting of the transceiver output when the transceiver is transmitting on the power line.

The inverting input of amplifier 268 is coupled to the centertap of potentiometer 276. Potentiometer 276 is coupled between ground and one end of resistor 278. The other end of resistor 278 is coupled to a positive 5 volt potential. Capacitor 280 is coupled between the inverting input of amplifier 268 and ground. The input power to amplifier 268 is provided by a voltage input connected to a 5 volt potential with the voltage input also coupled through to capacitor 282 to ground. Amplifier 268 is typically one half of a LM383 dual amplifier chip.

The output of amplifier 268 is coupled to the anode of diode 284 with the cathode of diode 284 coupled through capacitor 286 to ground. The output of amplifier 268 is also coupled through pull-up resistor 288 to a positive 5 volt potential. Coupled across the anode and cathode of diode 284 is resistor 290.

The junction of the cathode of diode 284, resistor 290 and capacitor 286 is coupled to the inverting input of amplifier 292. Amplifier 292 is typically the other half of the LM383 dual amplifier chip. The output of amplifier 292 is coupled through a feedback network comprised of resistors 294, 296, 298 and 300 to the non-inverting input of amplifier 292. A positive 5 volt potential is coupled to the feedback network. The positive 5 volt potential is coupled through current limiting resistor 302 to the anode of LED304 with the cathode of LED304 coupled to the output of amplifier 292. LED304 will illuminate when a carrier has been detected.

The basic operation of the carrier detector circuit is such that the signal received at the non-inverting input of amplifier 268 is amplified, output to the rectifier network (diode 284, resistor 290) which then charges capacitor 286. A filtered DC voltage exists on capacitor 286 which is a function of the carrier amplitude at the input of amplifier 268. The output stage (amplifier 292 and f eedback network) of the carrier detect circuit is basically a comparator circuit. When the voltage on capacitor 286 reaches the ref erence voltage established at the non-inverting input of amplif ier 292, the output voltage of amplifier 292 changes state. Therefore a logical "I" or "0" exists at the output of amplifier 292 as the signal CARDET depending upon whether a carrier signal exists at the input of the amplifier 268.Potentiometer 276 permits adjustment of the threshold of the comparator 268 so as to set the sensitivity of the output stage in detecting a carrier signal.

Figure 4 illustrates a sampling means for sampling data received by the transceiver from the power line. Also illustrated in Figure 4 is microcontroller means for formatting data for transmission over the power line and for extracting data from a received formatted message.

The sampling means comprises shift registers 400 and 402, counter 404 and logic gates 406 and 408. Shift registers 400 and 402 are 8-bit serial-in/parallel-out shift registers typically bearing part numbers 74HC164.

Shift register 400 has a pair of signal inputs (A and B) coupled to the RxD output of transceiver 218 and a clock input (CLK) connected to a 40 KHz oscillator (not shown). The clear input (CLR) of shift register 400 is coupled to an output (D2) of microcontroller 410. An output (OA) of shift register 400 is coupled to an input of exclusive-or gate 406. Another output (QH) of shift register 400 is coupled to a pair of the signal inputs (A and B) of shift register 402.

The clock input (CLK) of shift register 402 is coupled to the 40 KHz oscillator. The clear input (CLR) of shift register 402 is coupled to the (D1) output of microcontroller 410. A switch or jumper 412 permits the selective coupling of the output of shift register 402 (OF output or QH output) to another input of gate 406. The output of gate 406 is coupled through inverter 408 to a count enable input (CTEN) of counter 404.

Counter 404 is a 4-bit binary up/down counter typically bearing part number 74HC191. The selected output of shift register 402 (QF or OH) is coupled to the down/up input (DN/UP) of counter 404. The clock input (CLK) of counter 404 is also coupled to the 40 KHz oscillator while the load data input (LD) is coupled to the D1 output of the microcontroller 410. The data inputs of counter 404 (A,B,C and D) are held low by coupling to the output of inverter 414 which has an input tied through pull-up resistor 416 to a positive 5 volt potential. Switch or jumper 418 selectively couples counter data input (A) to either the output of inverter 414 or the 5 volt potential through resistor 416.The output (QD) of counter 404 is coupled to input A4 of buffer 420 which has a corresponding output Y4 to the input G3 of microcontroller 410.

Microcontroller 410 is a single-chip microcontroller, for example a microcontroller chip bearing part number COP440 manufactured by National Semiconductor Corporation. Microcontroller 410 has an internal arithmetic logic unit, program memory, input and output buffers, instruction decode/control logic along with an internal data bus. Microcontroller 410 is programmed to function as an "intelligent UART" so as to format data 8-bit bytes, received from a microprocessor (not shown) on a data bus (D-BUS, D0-D7) at ports LO-L7 of microcontroller 410 which is coupled to an internal buffer register. The input data is coupled on an internal data bus to a RAM memory for processing. Ports R0-R7 of microcontroller 410 are coupled to the eight bit address bus (A-BUS, AO-A7) of the microprocessor.

A 4 MHz signal is provided from the oscillator (not shown) to the clock input (CLK1) of microcontroller 410 for processor timing. The microcontroller 410 may be reset from the microprocessor by setting the signal PLC RST+ to a logic "1" or by the hardware during a power-up condition which sets the signal MR+ to a logic "I". Both of these signals are coupled through gate 402 to the reset input (RESET) of microcontroller 410. The microprocessor provides the signal (PLC SEL-) through buffer 420 to the Gl input of the microcontroller 410. This signal (when set to a logic "0") is used to initiate a data transfer between buffer 420, through switch or jumper 428 to the H2 input of the microcontroller 410. This signal is used in conjunction with G1 to indicate a write transf er (logic "O") or a read transfer (logic "I").The microcontroller 410 provides the signal (PLC RDYI-) f rom the GO output to the microprocessor. This signal is used to indicate when the data transfer has been completed. The carrier detect signal (CARDET-) provided from the carrier detect circuit is provided to an input (IN2) of microcontroller 410. The carrier detect signal enables the microprocessor to begin processing a data stream received at the G3 input from the sampling circuit.

Microcontroller 410 has a series of general purpose outputs D0-D3 with the DO output coupled to the TXD input of transceiver 218 so as to provide the formatted data i.e., a serial bit stream, for transmission over the power line. The outputs are an output from an internal buffer register of the microcontroller 110. The D1 output is coupled to the reset logic converter 424 coupled to buffer 420 counter 404, and shift registers 400 and 402 for respectively resetting their operation after the transmission of a formatted bit stream.

The resetting of these components is to clear out any extraneous signals which may effect the validity for future data. The D2 output is coupled to the Tx/Rx input of transceiver 218 with the state of the signal on this line enabling the transmitting circuitry or the receiving circuitry of transceiver 218. When configured as a binary control module, the D3 output is not used. The signal IO/M is coupled through switch or jumper 426 to the signal 10 ENBL-. The signal IO/M originates from the microprocessor and is used to indicate the start of an I/O (logic "0") or memory (logic "I") bus cycle. When configured as a binary output module, the D3 output is coupled through switch or jumper 426 to provide the signal 10 ENBL-. In this configuration, the microcontroller 410 can initiate an IJO bus cycle by setting this signal to a logic "0".

Microprocessor 410 also contains four additional general purpose output ports (HO-H3).

The HO output is coupled to the microprocessor as a signal (PLC INTR-) provides an interrupt to the microprocessor which indicates that a signal has been received and data extracted therefrom within the microcontroller.

The output H1 provides a signal (PLC BUSY-) to the microprocessor as a status flag that the microcontroller is either formatting a message or deformatting a message and is unable to respond to commands from the microprocessor. When configured as a binary control module, the H2 input is used by microcontroller 410 to determine the direction of the data transf er. A logic "0" indicates that data is being transferred from the microprocessor to the microcontroller 410. A logic "1" indicates that data is being transferred from the microcontroller 410 to the microprocessor. When configured as a binary output module, H2 out put is used as an output in conjunction with the D3 output. The output from D3 indicates the start of the I/O bus cycle and H2 is used to determine the direction of the data transfer.

The output from H2 is coupled through inverter 430 to switch or jumper 432 to the signal RD-. The output from H2 is also coupled through switch or jumper 428 to the signal WR-. A logic "0" on H2 is used to indicate a write transfer, while a logic "1" indicates a read transfer to the microcontroller 410.

The microcontroller has four general purpose inputs (lN0-lN3) with the INO input always being tied to a logic low level via the output of inverter 414. The IN1--IN3 inputs are held high through pull-up resistor 434 to a 5 volt potential. As discussed previously the input IN2 is coupled to the carrier detect signal (CARDET-).

When configured as a binary control module, the serial input (SI) of microcontroller 410 is coupled through switch or jumper 436 through pull-up resistor 438 to a 5-volt potential. This is used by the microcontroller to identify the type of configuration that is present. When configured as a binary output module, the serial input (SI) is coupled through switch 436 to the inverter 414 which is connected through pull-up resistor 416 to a 5-volt potential. Thus a logic "I" at the (SI) input indicates that the configuration is a binary control module, while a logic "0" indicates that the configuration is a binary output module. The binary output module merely provides output control functions in response to commands issued over the network without independent processing.

When the microcontroller is not busy processing received information the microprocessor asserts the PLC SEL-signal to initiate in the formatting of sequentially applied bytes of 8 bit parallel data presented from the microprocessor on the data bus (D-BUS). The microcontroller 410 formats the data into a serial message bitstream for transmission by the transceiver over the power line. The preferred message format is illustrated in Figure 5.

The formatted bit stream of Figure 5 includes a three part preamble for synchronizing the receiving transceiver and for initial message error detection. The preamble consists of the PLC initialization period followed by the transmit/receive synchronization period which is then followed by a unique code word which was analytically selected to minimize chances detecting a synchronization error.

The first part of the preamble is the PLC initialization which consists of four cycles of alternating "1" s and "O"'s. The PLC initialization sequence is utilized by a receiving transceiver. The automatic adjust function of the receiving transceiver requires one high and low transition to be received in order for the phase lock loop to lock onto the incoming carrier. Thus the PLC circuit can not guarantee it will output valid receive data on the first one and zero transition. However, during this time, the receiving unit is attempting to determine the start of a bit time. It does this by initiaiizing its receive clocks when a transition occurs. Since the first transition is not guaranteed to be valid, there are three additional high-to-low transitions for the receiver to synchronize its clocks.Three transitions, instead of one, are provided to permit the receiver as many opportunities to synchronize on the incoming signal without causing a significant delay in transmission.

The second part of the preamble consists of a transmit/receive synchronization period. The transmitter sends two zeroes, followed by a one, followed by two zeroes, followed by two ones. This is used by the receiver to indicate that the PLC initialization sequence has completed. Since it is possible for the receiver to synchronize on more than one point within the initialization sequence, this portion of the preamble is designed such that the receiver can easily identify the end of'initialization and prepare itself to check the succeeding code word. It does this by waiting for the first occurrence of two zeroes in the received bitstream. This can be easily differentiated from the alternating zero and one pattern in the first portion of the preamble. Just in case the first series of two zeroes are incorrectly received, the transmitter sends a second series of two zeroes.This provides two chances for the receiver to correctly identify the end of the initialization sequence.

The third part of the preamble consists of a code word unique to the power line communications message format that is used to verify that the receiving microcontroller has synchronized correctly with the incoming message.

The code word consists of two "0"'s followed by three s which are then followed by a "0", a "1" and a "O". The receiving microcontroller upon verification of this sequence by the microcontrollers internal firmware determines that a valid message is to follow. Once the code word has been verified by the receiving microcontroller, the microcontroller will not re-synchronize the data portion of the message.

The microcontroller chip is made up of many functional blocks, these include the central processor unit (CPU), arithmetic logic unit (ALU), read only memory (ROM), random access memory (RAM), counter/timer unit and input and output circuits. All of those functional blocks are used during both the transmit and receive operations.

During a transmit, the entire message is first transf erred from the microprocessor to the microcontroller's internal RAM, the message is stored as a series of sequential bits. Once the transfer has been completed, the microcontroller sets the Tx/Rx output (D2) to a logic one.

This places the PLC transceiver into the transmit state. The microcontroller then sets the TxD output (DO) to the state of the first bit in the transmit message. The counter/timer is then set to interrupt the CPU once every bit time (1/2300 seconds). Whenever a counter/timer interrupt occurs, the microcontroller then transmits the next bit within the message.

During a receive, the microcontroller uses the RXD (G3) and CARDET- (IN2) inputs.

When CARDET- makes a transition from a logic "1" to a logic "0", the microcontroller uses this as an indication that a message is being transmitted. It then checks the incoming data from the RxD input and waits for a highto-low transition. This transition marks the start of a bit time. The microcontroller then delays for 1/2 bit time and then initializes the counter/timer to interrupt once every bit time (1/2300 seconds) from the center of the received bit. Then whenever, a counter/timer interrupt occurs, the microcontroller reads the state of the RXD input and saves the state of this bit in its RAM. By saving the bits sequentially the microcontroller builds the entire receive message in RAM. Once completed, a checksum is calculated and verified on the received message.

The code word is followed by message start bit which is comprised of a "1". Following the start bit is the message data. The message data is transmitted from the most significant byte to the least significant byte and within each byte from the most significant bit to the least significant bit.

A frame control byte directly follows the start bits and is an 8-bit field used to identify the message type such as a system broadcast message, module command, initial system data, module request or input/output command.

Following the frame control byte is a source control byte which is an 8-bit field that has the address of the module that initiated the message. This address is determined by hex switches set to a predetermined unique identifying address for each module. The source address byte identifies the module which originated the transmission. Following the source address byte is a message data stop/start bit which are a "1" followed by a "O".

Following the source address byte, message data stop/start bits are placed into the transmitted message data by the formatting microcontroller. The message data stop/start bits are used to verify synchronization on the incoming data by the receiving microcontroller.

The message data stop/start bits are placed into the transmitted message at intervals of 16-bits.

The first occurrence of message data stop/start bits are followed by an 8-bit field designated as the destination address byte which contains the address of the module that is to receive the message. Following the destination address bit is an 8-bit field used when message data is sent through a bridge module.

This address information is used by the bridge module to determine the ultimate destination when the message is re-transmitted by the bridge. The destination address may be the bridge module address when messages are transmitted through the bridge for retransmission to a final module.

Following the address extension byte are message data stop/start bits which are typically a "1" followed by a "0". As before, the message data stop/start bits are used by the receiving microcontroller to verify the synchronization of the incoming data.

The second group of message data stop/start bits is followed by the data field. The data field may be either a single byte (8-bits) data field, as illustrated in Figure 5, or a nine byte (72-bits) data field. When the data field is comprised of nine bytes, at 16-bit intervals message data stop/start bit are interposed as was previously described.

As illustrated in Figure 5, the data field is a single data field byte which is followed by a checksum byte. The checksum byte is an 8bit field containing two 4-bit check values.

The first check value is a 4-bit exclusive-OR of the message data contents, exclusive of the message data stop/start bits, e.g., frame control byte, source address byte, destination address byte, address extension byte and data field byte. The second 4-bit check value is a 4-bit sum of the number of bits in the message data, exclusive of the message data stop/start bits, set to "1". A checksum byte is used to indicate that message data bits received are accurate with respect to the transmitted message data bits. The checksum bits are followed by stop bits which indicate the end of the message transmission. The stop bits are transmitted as two "0" 's When the receiving module carrier detect circuit detects a carrier signal it provides a signal CAR DET- to the receiving microcontroller.This signal enables the microcontroller to interrupt other concurrent processing and receive the message. Synchronization of the transceiver occurs during the PLC initialization period of the message as discussed previously. Synchronization of the receiving microcontroller is accomplished when a first high to low transition occurs during the transmit/receive synchronization period at this point the microcontroller initializes its receiving clock. After the occurrence of the high to low transition, the receiving microcontroller makes three additional readings on the state of the incoming data during the same bit time. If two out of three readings indicate that the data was still in the low state, then synchronization is confirmed.Should at least two of the three readings indicate that the data was not in the low state, for example the first high to low transition was caused by a noise spike, the receiving microcontroller does not synchronize its receive clock at this time. The receiving microcontroller will then wait again until the second high to low transition in the transmi receive synchronization period.

By utilizing. the multiple reading scheme, the effect of noise spikes on the validity of incoming data can be minimized. During the receipt of an incoming message, the receiving microcontroller may find it necessary to resynchron ize on the incoming data. When this occurs, the microcontroller attempts to predict the po sition of the next rising edge.

The receiving microcontroller looks for the code word to verify that synchronization is correct with the incoming message. The microcontroller compares the received code word with a programmed sequence of corresponding bits. Upon verification, the receiving microcontroller knows that a valid message is to follow. The microcontroller resynchronizes its internal receiver logic on the first high to low transition of the code word. Once the code word has been verified, the receiving microcontroller will not resynchronize during the data portion of the message. Should the received code word contain an error that is detected by the microcontroller, the microcontroller is programmed to restart the receive sequence to detect the transmit/receive synchronization data.

Upon validation of the code word and correct synchronization, the microcontroller looks for start bits which immediately follow the code word and indicate the beginning of message data.

The sampling circuit samples the received message bits and provides an output signal of a state corresponding to the predominant state of the bit during the bit period. The sampling circuit continuously samples the data bit with fifteen samples taken over a 375 microsecond period occuring during a central portion of the 435 microsecond bit time (2300 baud) being used to determine the bit state. Figure 6 illustrates the sampling scheme which occurs during an exemplary bit period.

The sampling hardware is illustrated in Figure 4 such that data is received on the RXD line is sampled at a 40KHz clock rate and shifted at the same rate into shift registers 400 and 402. The 40 KHz oscillator may be synchronized with the 4 MHz oscillator although this is not a requirement. As data is passed through shift register 402 it is counted by the 4-bit counter 404. Counter 404 counts up during the sampling of a high bit, and as the bits are shifted through registers 400 and 402 during a following low bit, the counter counts down. With the jumpers 412 and 418 in the position illustrated in Figure 4, counter 404 provides an output indication at the counter QD output (the most significant bit output of the 4-bit binary counter) of the state which appears most often in 8 out of 15 samples occuring during the bit period.Should eight or more samples during the bit period be high, then the OD output provides a high output as being the state of the bit. The QD output is sampled by the Microcontroller during the bit period after the last 15 samples have been counted. Although illustrated as three samples being taken by the microcontroller during the bit period after the 16 samples are taken, one sample by the microcontroller is sufficient. By changing jumpers 412 and 418 to the opposite position f rom that illustrated in Figure 4, the counter is preset to begin counting from 1 with a OD output high when 7 of 13 bit samples are high.

By utilizing the described sampling scheme the received data can be isolated from line noise that lasts up to 150 microseconds and which typically occurs every 8.3 milliseconds.

By utilizing this sampling scheme to eliminate noise from an incoming signal, the microcontroller is able to spend less time decoding data so as to achieve an increased baud rates in data reception.

During the reception of the incoming message data portion of the message, no other processing is performed by the receiving microcontroller until the entire message has been received, except for the verification of the stop/start bits.

After the entire message has been received the microcontroller recalculates the checksum on the entire message and compares this calculation against the checksum data attached to the message. If the calculated checksum data matches the received checksum data then a valid message is assumed to have been received. The message data is then ready to be processed by the microcontroller and/or forwarded to the module microprocessor.

The formatting of messages as disclosed herein permit the accurate transmission and reception of data over a communications medium which is inherently noisy. By utilizing the message format and receiving sampling scheme, the received data may be accurately processed by the module in performing the assigned tasks. The described elements permit baud rates which may be substantially greater than the exemplary 2300 baud rate. It is envisioned that even greater baud rates may be implemented with the system disclosed herein.

Claims (12)

1. A system for formatting an input bytewide data stream into an output message bit stream for transmission over a power line and for extracting an output byte-wide data stream from an input message bit stream received over a power line, comprising: format means responsive to consecutive, parallel data bytes occuring in an input byte-wide data stream for generating a preamble portion of a serial output message bit stream, converting said input byte-wide data stream into a data portion of said output message bit stream, and generating a checksum portion of said output message bit stream; and extraction means responsive to a serial input message bit stream having a preamble portion, a data portion and a checksum portion for extracting from said input message bit stream data portion an output byte-wide data stream including consecutive, parallel data bytes.

2. A system according to claim 1 wherein said format means computes said output message checksum portion from said data bytes occuring in said input byte-wide stream.

3. A system according to claim 1 or claim 2 wherein said extraction means further comprises: buffer means responsive to said input message bit stream for storing said input message bit stream; synchronizing means for synchronizing said buffer means with said input message bit stream; arithmetic means for computing a receiver checksum value corresponding to the bits in data portion of said input message bit stream, comparing said receiver checksum valve with the bits in said checksum portion of said input message bit stream, and providing a verification signal when said receiver checksum valve matches the bits in said checksum portion of said input message bit stream; and output means responsive to said verification signal for outputting said consecutive, parallel data bytes in said output byte-wide bit stream.

4. A system according to any foregoing claim wherein the said preamble portions of said input and output message bit streams are of a substantially identical format.

5. A system according to any foregoing claim further comprising transceiver means coupled to said format means and said extraction means for receiving said output message bit stream and for converting said output message bit stream from a serial binary bit stream to a frequency-shift keyed bit stream and responsive to said input message bit stream in the form of a frequency-shift keyed bit stream for providing a corresponding serial binary bit stream.

6. A system according to claim 5 further comprising coupling means coupled to said transceiver means for coupling said frequencyshift keyed output message bit stream from said transceiver means onto a power line, and for coupling said frequency-shift keyed input message bit stream on a power line to said transceiver means.

7. A system according to claim 6 further comprising carrier detect means coupled to said coupling means and said extraction means, said carrier detect means responsive to said frequency-shift keyed input message bit stream for providing a carrier detect signal wherein said carrier detect signal enables said extraction means for extracting from said input message bit stream data portion said output byte-wide data stream.

8. A system according to any of claims 5 to 7 further comprising sampling means coupled between said transceiver means and said extraction means for multiple sampling of the state of each bit in said input message bit stream and providing a conditioned input message bit stream wherein each bit corresponds to the predominant sample state of each bit in said input message bit stream, said conditioned input message bit stream provided to said extraction means for extracting said output byte-wide data stream.

9. An apparatus for formatting a sequence of groups of parallel input data bits into a serial output bit string for transmission over a power line, comprising: input buffer means for receiving and storing a sequence of groups of parallel input data bits; arithmetic means coupled to said buffer means for receiving said stored data bits, computing checksum bits corresponding to said stored data bits, and generating preamble bits, said arithmetic means providing sequentially said preamble bits, said stored data bits and said checksum bits; and output buffer means responsive to said sequenced preamble bits, stored data bits and checksum bits and providing a corresponding serial output bit string at a predetermined bit rate.

10. An apparatus for extracting a sequence of groups of parallel output data from a formatted serial input bit string received over a power line, comprising: input buffer means for receiving and storing a serial input bit string having preamble bits, data bits, and checksum bits; arithmetic means coupled to said input buffer means for receiving said stored input bit string, computing checksum bits corresponding to said stored data bits, comparing said computed checksum bits with said input bit string checksum bits, and providing said stored data bits at an output in response to a match in computed checksum bits and stored checksum bits; and output buffer means coupled to said output for receiving said stored data bits and for outputting said stored data bits as a sequence of groups of parallel output data.

11. A method of formatting parallel bits of an input byte-wide data stream into a serial output message bit stream for transmission over a power line, comprising: generating a series of preamble bits each having a predetermined bit state; generating a series of message data bits corresponding to parallel bits of an input byte-wide data stream; and generating a series of checksum bits wherein the respective sequence of said preamble bits, message data bits, and checksum bits form a serial output message bit stream.

12. A method according to claim 11 further comprising: generating a series of start bits between said preamble bits and said message data bits; generating a series of stop bits following said checksum bits; and generating groups of stop/start bits in said series of message data bits, said stop/start bits being generated after a predetermined number of message data bits.