GB2176942A - Making printed circuit boards - Google Patents
Making printed circuit boards Download PDFInfo
- Publication number
- GB2176942A GB2176942A GB08515409A GB8515409A GB2176942A GB 2176942 A GB2176942 A GB 2176942A GB 08515409 A GB08515409 A GB 08515409A GB 8515409 A GB8515409 A GB 8515409A GB 2176942 A GB2176942 A GB 2176942A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- indentation
- conductor
- areas
- solder mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/16—Coating processes; Apparatus therefor
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0073—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
- H05K3/0082—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the exposure method of radiation-sensitive masks
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
- H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/428—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61K—PREPARATIONS FOR MEDICAL, DENTAL OR TOILETRY PURPOSES
- A61K38/00—Medicinal preparations containing peptides
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
- H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09036—Recesses or grooves in insulating substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09845—Stepped hole, via, edge, bump or conductor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09927—Machine readable code, e.g. bar code
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09936—Marks, inscriptions, etc. for information
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09981—Metallised walls
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/025—Abrading, e.g. grinding or sand blasting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/054—Continuous temporary metal layer over resist, e.g. for selective electroplating
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0548—Masks
- H05K2203/056—Using an artwork, i.e. a photomask for exposing photosensitive layers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0571—Dual purpose resist, e.g. etch resist used as solder resist, solder resist used as plating resist
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0577—Double layer of resist having the same pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/066—Transfer laminating of insulating material, e.g. resist as a whole layer, not as a pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0756—Uses of liquids, e.g. rinsing, coating, dissolving
- H05K2203/0759—Forming a polymer layer by liquid coating, e.g. a non-metallic protective coating or an organic bonding layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
- H05K3/045—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by making a conductive layer having a relief pattern, followed by abrading of the raised portions
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
An insulating substrate (10) coated with a thin copper layer is drilled to form through holes (16) and etched to define a circuit pattern (15). A liquid photopolymer solder mask layer ( 1) having a smooth planar outer surface is applied over the circuit pattern and processed to expose land areas (14) surrounding the through holes (16), the walls (18) of the solder mask surrounding the lands (14) being substantially cylindrical and roughened. A thin copper layer (20) is then applied by electroless deposition overall the exposed surfaces and an insulating resist layer (13) is applied over the copper on the planar surface of the mask (11). A thick copper layer is electroplated onto the copper coating in the through hole (16) and the resist (13), together with the underlying copper layer (20), is mechanically removed. The land (14) then forms the bottom surface of an indentation having copper coated sidewalls. <IMAGE>
Description
SPECIFICATION
Printed wiring boards with solder mask over bare copper wires having large area thickened circuit pad connections
This invention relates to printed wiring boards of the type having a solder mask layer over bare copper wiring etched on a substrate, and more particularly it relates to the preparation of connection sites at circu it pad and through hole positions which have thicker copper conductors and solder overlays.
To reduce the cost of printed wiring board manufacture, a solder mask layer has been placed directly over bare copper wire traces etched on a copper clad substrate. Connections are made to the wire traces, at circuit pad connector positions commonly called lands, by exposing the copper, that is by leaving voids inthesoldermasksothattheconnection areas or circuit pads including those atthrough hole positions are not covered. The circuit pads are then covered with solder.
The copper cladding on the substrate is about .0014 in. (0035 cm) thick to facilitate etching ofthe circuit traces. Before etching the copper traces are electroplated to full thickness of about .002 in. (.05 cm) before applying the solder mask. Also it is conventional to selectively plate the circuit pad positions with tinlead or other protective layers before applying the solder mask layer and before etching. This requires a step of stripping the tin-lead layer in a chemical process which is difficult to protect against pollution.
The prior art process also limits the wiring density, since the land areas need to be in the order of .050 in.
(.13cm) in diameter in orderto make a reliable connection. Thus a closertogetherspacing of circuit traces is not feasible.
It is therefore an object ofthis invention to correct the foregoing deficiencies of the prior art. Further objectives are to reduce pollution in the manufacturing process, to increase wiring density, to reducethe amount of copper on the circuit boards, and to decrease the number of manufacturing steps and therefore the cost of production of printed circuit boards.
Awiring board clad with a thin copper coating is etched to provide a wiring trace pattern complete with circuit pad connection positions and through holes. The wiring density may be increased by making the circuit pad areas smaller than heretofore required. A liquid photopolymer solder mask layer is then placed over the wiring pattern to have a flat planar (flush) outer surface with a glossy surface to whichacopperlayerwill notadherewell.Thislayeris then photo exposed and developed to uncoverthe land areasto which connections should be made. An electroless chemical deposit of a very thin copper layer is then deposited over the entire surface area.It will not adhere well to the glossyflatsurface but does adhere well to the circuit copper wiring and the photo developed areas about the pad position and in particularon the sidewalls ofthe solder mask layer.
Then an insulating resist layer is laid over the depo sited copper layer on the flat planar surface leaving exposed the cicuit pad positions and the surrounding wiring board substrate area as well as the sidewalls of the solder mask coating, all covered with the deposited copper layer. A thicker coating of copper is then electroplated over only the exposed areas, and if desired a tin-lead coating. The resist layer together with the poorly adhering deposited copper layer is then mechanically stripped from the flat planarsurface, such as by stripping, air or water abrasion.
Brief description of the drawings
In the drawing:
Figure 1 is an elevation section view of a portion of a printed wiring board illustrating a step in theformation of a circuit connecting terminal at athrough hole position;
Figure2 is a similar elevation section view ofthe printed wiring board portion after completion of the process; and Figure 3 is planviewofaportionoftheprinted wiring board of Figure 2 looking down at a through hole position.
The preferred embodiments
The printed wiring board configuration shown in the drawings depicts a solder mask layer 11 over bare copper wiring traces 15 etched in a very thin copper cladding layer on the surface of the insulating substrate board 10. It is critical in connection land areas or circuit pads 14 such as shown aboutthe through hole 16 that a minimum surface area be covered with a thick copper conductor, which may be soldered. In
Figure 3 it may be seen that the diameter ofthe eyelet 19 will dictate the spacing between circuit traces 15. It is thus inconsistent to expect higherwiring packing densities with wiring traces located closelytogether when circuit pads are reliably prepared with adequate conductor surface area.
Also it may be noted from Figure 2 that the lands 14 are covered with a thickening layer 17 of copper, but thatcircuittraces l5donothavethethickening layer 17. Heretofore the processes of wiring board construction have included a thickening layer of copper on all the circuit wiring traces on the substrate 10 before the solder mask layer 1 1 is applied.
Now in accordance with this invention an improved wiring board is provided with more dense wiring, less copper and high quality large area circuit pad connections, surprisingly requiring fewer manufacturing steps. It is possible with the process of this invention to eliminate some critical chemical manufacturing steps before required to the effect that expensive pollution control procedures are no longer necessary.
Those steps taken in sequence to make this improved wiring board are outlined asfollows: 1. drill the through holes 16 in the substrate lamin- ate 10, which is clad with a very thin layer of copperto facilitate the etching of the circuit traces therein;
2. laying down an etch resist layer on the copper cladding to define the desired circuit trace pattern, etching away unwanted copper and stripping the etch resist layer;;
3. laying down a liquid photopolymer solder mask layer with a smooth flat planar outer surface overthe etched circuit traces, photoexposing to provide a pattern for leaving exposed land areas 14, etc. to be prepared as circuit connection pads, and developing to remove the photopolymer aboutthe circuit lands 14, etc. in such a way to leave substantially cylindrical shaped solder mask walls with a somewhat roughenedtextureto which a layer ofcopperwill adhere well;
4. chemically depositing by the electroless process a thin layer of copper, typically .00005 in (.00013 cm) thick, overthe solder mask surface and into the exposed land positions and on thesubstratethere- around and through the holes in the laminate;;
5. rolling or screening overthe electroless copper layer resident on the flat planar glossy solder mask outer surface an insulating resist layer 13;
6. electroplating a thick layer, typically .001 inch (.025cm), of copper 17; and
7. mechanically removing the resist layer 13 with the underlying thin copper layer 20 from the glossy surface of the solder mask layer 11 by stripping, air or water jet, etc.
The preferred liquid photopolymerforthe solder mask coating is type 311 LV manufactured by M &
Chemicals of Rahway, N. J. The coating thickness is at least .002 inch (.005 cm) overtraces and .004 inch (.01 cm) overthe base laminate. A preferred method of processing the solder mask layer is to deposit it in two separate coatings. The first coating can be screen printed with an appropriate gauge mesh polyester screen to a thickness of .002 inch (.005 cm) directly overthe substrate 10 with the wire traces 15 thereon.
Afurtherlayerofthesamethickness is coated on a flat photoimage plate of glass or plastic carrying an appropriate imageforthesoldermaskpattern over the circuit traces. The two liquid photopolymer coatings are then broughttogether in airfree contact so thattheflat plate will further enhance the glossy outer surface to make a pooradherancesurfaceforthe electroless thin copper layer to be deposited thereon.
This can be done by placing the layers in a vacuum chamber at decreased pressure of 25 inches (62.5 cm) of mercury therebyto purge all airfrom between the two coated surfaces before they are joined. Alternatively, where a thin layer of photopolymer can be used, as would be the case with thin copper conductors, then the liquid photopolymer can be applied to eitherthe substrate 10 orthe flat photoimage plate, but not necessarily both. The photo exposure step may take place either within or outside the vacuum chamber. The exposed photopolymer is developed by washing out unhardened areas with a solventmix- ture of 85 parts trichloroethane and 15 parts isopropyl alcohol.
Metallization layer 20 is applied over the photopolymer surface after development using the M &
HD high speed autocatalytic copper plating process of M & Chemicals. The deposition thickness is just enough to provide a conductive path forthe electroplating step.
Plating resist layer may be roller coated because the solder mask surface is flat and free of any projections or irregularities. A preferable resist is type CN F 1 1 10 from M & Chemicals.
Copper is conventionally electroplated on the exposed land areas to a thickness of the order of .001 inch (.0025cm). Note that this invention now provides for the plating ofthe substantially cylindrical side walls of the solder mask layer 11 thereby to substantially increase the available conductor area to which contact can be made. This permits the diameter of the eyelet 19 (Figure 3) to be made smaller without reducing the reliability of the circuit pad connection.
Tin-lead is then electroplated overthethickened copper coating, afterwhich the plating resist layer 13 is removed along with the underlying electroless deposited thin copper layer. Because ofthe glossy polymersurfacethe resist may be removed mechanically to avoid chemical processes and their corresponding pollutant atmospheres which must be confined or eliminated. Preferably this is done by air abrasion or by light sanding. It may also be done by an air or water stream. The electroless deposit about the land areas and through holes however makes a strong bond because the solder mask and substrate surfaces are textu red by the earlier process steps.
Thus the desired metallized areas are not removed by this mechanical removal step.
The typical increase in land surface area as illustrated in Figure 3 has a typical .050 inch (.125 cm) diameter eyelet 19 surface area increased at least 20 percent by metallizing the surrounding annular ring 23. In addition the metallization oftheverticalwall surfaces of the solder mask layer, the land surface area is increased by 130 percent.
This process afforded by this invention thus eliminates several steps and reduces the expenditure of materials, while retaining the significant advantages of the solder mask over the bare wire type of printed wiring board. Accordingly, the conventional practice of plating tin-lead over all conductor traces before applying the solder mask coating is eliminated,togetaherwith the requisite chemical etching and stripping and it polluting side effects. Furthermore immersion in molten solder with corresponding expensive equipment and hot air knives for blowing away excess solder are eliminated.
Additional advantages are provided by saving of materials where copper and tin-lead coatings are only required on the desired circuit pad locations. Fusing of the tin-lead layer is simply achieved with inexpensive equipment.
The ability to resolve fine lines and spaces is of great importance. One of the limitations to achieving fine lines and spaces of the order of .005 inch (.0127 cm) is the primary imaging step, which is the photopatterning of either a plating or etch resist. An etch resist photopolymer is typically one fourth ofthe thickness of a plating resist photopolymer, and since the resolution decreases with the photopolymer thickness, greater resolution can be achieved with an etch resist pattern. The disclosed process defines conductor patterns by etching prior to electroplating and thereby achieves improved resolution. This departs from the prior art practice for soldermask on bare copper printed wiring boards where resolution is sacrificed by employment of a plating resist for the primary imaging.
For the higher resolution advantage afforded by this invention, the primary imaging of the conductor patterns is achieved by the steps now described. A flat (preferably glass) plate phototool with clear areas defining the conductor locations has a photopolymer release coating on the image plane over which a layer of the CNF 1110 photoresist is applied by screen print- ing over the entire plate surface.
The photopolymer layer is partially hardened in light struck areas by passing lightthroug h the glass plate into the photoresist layer. This step hardens the photopolymer layer enough so that its viscosity precludes extrusion of photopolymer from between the phototool and the printed wiring board. Nextthe glass plate is placed with the photopolymer layer near to and out of contact with the copper clad and previously drilled printed wiring board substrate, in a vacuum chamberforcontactto be made in the presence of a pressure of about 30 inches (75 cm) of mercury.
Then the photopolymer is fully hardened by expo- sure to light passing through the glass plate and thereby clings to the printed wiring board. The release layer of the glass plate permits its removal for recoating and reuse with screening directly over the unhardened photoresistthereon.
Mentioned heretofore was the achievementofin- creased land surface area. One additional desirable feature of the lands is the increase in copper thickness on land areas, while the traces require no additional electroplated copper. Thus a heavy copper interconnection layer is provided without waste of copper.
New functions are achieved by this invention in addition to the traditional functions. The flush solder mask provides for restricting solder to land areas for wave soldering with life long insulation and environment protection. Furthermore the flush solder mask characteristic permits temporary metallization (from which used copper is reclaimable) mechanically removable with improved cost and environmental advantages.
Prior art solder mask coatings produce a surface which roughly follows the contours of the conductor patterns and is therefore notflush nor flat so that mechanical removal of a layercould not be achieved.
If a solder mask is screen printed, mesh marks result and any metallization thereoverwould need be etched for removal. Smooth surfaced layers cannot be achieved by simply roller coating over a contoured surface, and the substitute photo imaging step would be more costly and time consuming.
A distinctive and novel feature of the printed wiring board afforded by this invention is the flat flush solder mask outer surface, which permits the electroless deposition step and corresponding simplification of the manufacturing process. Plating of the sidewalls of the solder mask layer is also a distinctive feature of this invention.
The disclosed method for solder masking of printed wiring boards is not restricted to solder mask over bare copper boards but can be used independentlyto achieve a solder mask coating over circuit traces covered with tin-lead or other metal.
This invention also providesforthe inexpensive repair of faulty printed wiring boards having voids in the holes. These are conventionally scrapped.
However the solder may now be stripped from the landsandthrough holestoexposetheunderlying copper. Next an etch resist is photoimaged to coat copper external surfaces, leaving through holes free of photoresist. The copper is removed from the holes by etching, so that a uniform coating of copper can be metallized therein. After etching, the plating resist is removed and the board is processed as previously described. Thus an expensive multilayer board can be restored at lower cost than remaking.
Having thus advanced the state of the art, those novel features believed descriptive of the nature and spirit of the invention are defined with particularity in
Claims (11)
1. The method of preparing solder mask coatings over circuit conductors on printed circuit wi ring boards characterized bythe step of:
laying down overthe circuit conductors a mask layer treated to obtain a smooth flat planar outer surface which permits a superimposed metallic layer to be easily removed.
2. The method of Claim 1 further characterized in that the outer surface is obtained by disposing a liquid photopolymer layer as said solder mask layer with a flat plate phototransparency in air free contact with the liquid photopolymer layer, photoexposing the liquid polymerthrough the phototransparencyto provide a pattern of hardened polymer and producing unhardeded areas to be washed outto establish exposed circuit conductor areas for receiving solder, and
removing the phototransparencyto produce a flat glossy outersurface of hardened polymer.
3. The method defined in Claim 2 including the further step of metallizing both the sidewalls of the polymer about the exposed conductor areas and polymer about the exposed conductor areas and the exposed circuit conductors to increase the amount of conductor surface available in the exposed areas for receiving solder.
4. The method defined in Claim 3 further characterized in that the solder mask layer has a thickness of at least 0.002 in.
5. The method defined in Claim 2 including the further steps of establishing a metallizing layer over the solder mask surface and exposed conductor areas for electroplating a thick coating in the exposed conductor areas and removing the metallized layer over the flat glossy surface after electroplating.
6. The method defined in Claim 2further char- acterized bythe steps of coating the entire surface of the printed wiring board with a layer of liquid photopolymer, coating a flat plate phototransparencywith a alayer of liquid photopolymer, registering the photo transparency with the printed wiring board with the two liquid layers in airfree contact, exposing the photopolymerto radiation through the photo transparencyto harden those areas to be covered by the insulation layer, and washing out the unhardened photopolymerto establish said exposed land areas.
7. The method defined in Claim 6 further char- acterized by the step of placing the two liquid layers together in a vacuum of approximately 25 inches of mercuryto exclude air.
8. The method of Claim 6 wherein a thin conductor layer is deposited overthe insulation layer, an insulating layer is rolled overthe insulation layer, the thin conductive layer is used as an electrode to electroplate a thicker layer of conductive metal into the washed out areas, and the thin conductive layer with its insulation layer covering are mechanically removed to expose only the thickened conductive layer as a conductor accessible from the outer surface.
9. The method defined in Claim 2 further char- acterized bythe steps of forming a temporary metallic layer on said flat surface of said board with the solder mask coating with a protective insulation layer and removing both the protective layer and the metallic coating thereunder.
10. The product obtained bythe method of any one of Claims 1 to 9.
11. A method of preparing solder mask coatings over circuit conductors on printed circuit wi ring boards, substantially as herein described with reference to the accompanying drawing.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/550,379 US4528259A (en) | 1983-11-10 | 1983-11-10 | Printed wiring boards with solder mask over bare copper wires having large area thickened circuit pad connections |
Publications (2)
Publication Number | Publication Date |
---|---|
GB8515409D0 GB8515409D0 (en) | 1985-07-17 |
GB2176942A true GB2176942A (en) | 1987-01-07 |
Family
ID=24196932
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB08515409A Withdrawn GB2176942A (en) | 1983-11-10 | 1985-06-18 | Making printed circuit boards |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2176942A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2246243A (en) * | 1990-05-18 | 1992-01-22 | Nippon Cmk Kk | Printed wiring boards |
GB2305299A (en) * | 1995-09-12 | 1997-04-02 | Irish Circuits Ltd | Printed circuit board production process |
WO2004077901A2 (en) * | 2003-02-27 | 2004-09-10 | Endress+Hauser Gmbh+Co. Kg | Printed circuit board and method for fixing wired parts thereto |
CN101066003B (en) * | 2004-12-02 | 2010-12-08 | 松下电器产业株式会社 | Printed circuit board and its design method, IC package terminal design method and its connection method |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114521072B (en) * | 2022-02-11 | 2023-03-10 | 北京华镁钛科技有限公司 | Counter bore thin copper surface process circuit board pressing device and process |
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GB1015827A (en) * | 1963-12-23 | 1966-01-05 | Ibm | Improvements in and relating to electrical connections in printed circuit boards |
GB1487800A (en) * | 1974-12-31 | 1977-10-05 | Ibm | Plated through-holes for printed circuits |
GB1488301A (en) * | 1974-09-27 | 1977-10-12 | Ibm | Methods of forming electrical conductors |
GB2123616A (en) * | 1982-07-12 | 1984-02-01 | Rogers Corp | Circuit boards and method of manufacture thereof |
GB2126428A (en) * | 1982-09-03 | 1984-03-21 | Fluke Mfg Co Inc | Molded circuit board and manufacturing method therefor |
-
1985
- 1985-06-18 GB GB08515409A patent/GB2176942A/en not_active Withdrawn
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1015827A (en) * | 1963-12-23 | 1966-01-05 | Ibm | Improvements in and relating to electrical connections in printed circuit boards |
GB1488301A (en) * | 1974-09-27 | 1977-10-12 | Ibm | Methods of forming electrical conductors |
GB1487800A (en) * | 1974-12-31 | 1977-10-05 | Ibm | Plated through-holes for printed circuits |
GB2123616A (en) * | 1982-07-12 | 1984-02-01 | Rogers Corp | Circuit boards and method of manufacture thereof |
GB2126428A (en) * | 1982-09-03 | 1984-03-21 | Fluke Mfg Co Inc | Molded circuit board and manufacturing method therefor |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2246243A (en) * | 1990-05-18 | 1992-01-22 | Nippon Cmk Kk | Printed wiring boards |
GB2246243B (en) * | 1990-05-18 | 1994-06-29 | Nippon Cmk Kk | Printed wiring board and method of manufacturing same |
GB2305299A (en) * | 1995-09-12 | 1997-04-02 | Irish Circuits Ltd | Printed circuit board production process |
WO2004077901A2 (en) * | 2003-02-27 | 2004-09-10 | Endress+Hauser Gmbh+Co. Kg | Printed circuit board and method for fixing wired parts thereto |
WO2004077901A3 (en) * | 2003-02-27 | 2004-10-28 | Endress & Hauser Gmbh & Co Kg | Printed circuit board and method for fixing wired parts thereto |
CN101066003B (en) * | 2004-12-02 | 2010-12-08 | 松下电器产业株式会社 | Printed circuit board and its design method, IC package terminal design method and its connection method |
US8097815B2 (en) | 2004-12-02 | 2012-01-17 | Panasonic Corporation | Printed circuit board and its designing method, and designing method of IC package terminal and its connecting method |
Also Published As
Publication number | Publication date |
---|---|
GB8515409D0 (en) | 1985-07-17 |
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WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |