GB2168843A - Manufacture of semiconductor devices - Google Patents

Abstract

A plurality of semiconductor devices (25) are formed on a common wafer (20). The devices are metallized with a plurality of metallizing layers (71-73), the lowest of which (71) forms an ohmic contact with the silicon surface, the uppermost (73) being solderable and resistant to a caustic etch. After metallizing, the individual devices are separated by eg. laser scribing and are subsequently ground to produce a conical surface shape (90), mounted on an expansion plate (80) and caustic etched to remove damage to the silicon surface caused by the grinding operation. <IMAGE>

Description

GB 2 168 843 A 1

SPECIFICATION

Improvements in or relating to methods of manu facture of semiconductor devices This invention relates to semiconductor devices, and more specifically to a method of manufactur ing a plurality of semiconductor devices from a common wafer.

10 The initial step in the manufacture of power 75 semiconductor devices such as controlled rectifiers or the like normally take place in a wafer fabrica tion facility in which a very large diameter wafer has junctions formed therein for a plurality of iden- 15 tical devices. After the formation of the junctions in 80 the larger wafer, the individual devices are sepa rated from the wafer and are then further proc essed separately, usually in an assembly facility. In the further processing, an expansion plate contact 20 is first alloyed to the bottom of the individual water elements. Thereafter contact metals are applied to the upper surface of the individual wafer elements. This contact metallizing process normally requires masking and oxide-etching for each 25 individual wafer element.

The above sequence of first alloying the expansion contact and later applying contact metals has been necessary because the contact metals used in power devices are commonly aluminium. The alu- 30 minium contact metal would diffuse into the wafer surface at the alloying temperatures used for applying the expansion contact to the bottom of the wafer and would interfere with the diffused junction pattern.

After metallizing, the outer periphery of the individual wafer elements is tapered to increase the breakdown voltage of the device. This process employs either an acid etch process or a grinding process followed by an acid etch to remove the 40 damage caused by the grinding. However, the aluminium contact can be attacked by the acid etch used in the beveling operation. Therefore, it was necessary to protect the metallizing by coating it, for example, by gold plating and by wax, prior to 45 the acid etch operation.

All of the above steps were carried out in an assembly area on individual wafer elements which must be separately handled. Thus, the added steps and separate handling substantially increase the 50 expense of the device and reduce process yield.

According to one aspect of the invention, there is provided a method of metallizing a surface portion of a monocrystalline silicon wafer comprising an initial step of removing at least one micron thick- 55 ness from said surface portion to ensure removal of unintended oxygen contamination in said surface portion, thereafter depositing a thin layer of nickel onto the surface portion and converting at least a portion of the thickness of the nickel layer to nickel silicide, and depositing at least a layer of a contact metal atop the layer of nickel, the contact metal layer being tenaciously fixed to the surface portion.

According to another aspect of the invention, 65 there is provided a method of metallizing a plural- 130 ity of exposed surface portions of a silicon wafer, which surface portions are for respective identical wafer elements which are subsequently to be separated from one another, wherein the metallizing 70 surface is capable of surviving process temperatures of greater than about 650'C and makes ohmic contact with N or P type silicon and is resistant to a large variety of chemical etches and is easily so[derable; the method comprising the steps of: applying an insulation coating to a surface of the silicon wafer; photolithographically masking and etching through said mask to expose at least one predetermined surface portion of the surface through the insulation coating; thereafter removing at least a one micron thickness from the surface portion while leaving the insulation coating intact to ensure removal of unintended oxygen contamination in the surface portion; depositing a thin continuous layer of silicide-forming metal atop the 85 surface portion and atop adjacent surfaces of the insulation coating and converting at least a portion of the thickness of the silicide- forming metla to a metal silicide; depositing at least a layer of contact metal atop the layer of said silicide-forming metal; 90 applying a delaminating stress to the metal layers to remove the silicide-forming layer and the contact metal layer from atop the insulation coating, with the silicide-forming layer and the contact layer strongly adhering to the surface portion of the sili- 95 con wafer; cutting apart the silicon wafer into a plurality of wafer elements which all contain at least one of the plurality of exposed surface portions; and thereafter further processing each of the plurality of wafer elements to complete respective 100 semiconductor devices.

A metallizing system may thus be applied to the wafer in the wafer fabrication facility before the wafer is cut into its individual devices. The metallizing system may employ nickel and silver. This 105 metallizing system makes ohmic contact to underlying bare silicon surfaces, and is capable of surviving subsequent alloying temperatures employed in alloying an expansion contact to an individual wafer element. After the metallizing is applied to 110 the wafer, the wafer is cut into individual wafeT elements. These are then alloyed to respective bottom expansion contacts in a vacuum alloying process which might employ temperatures as high as 650'C for 30 minutes. Since the metallizing system 115 may have an outer silver layer, a hot caustic etch can be applied to the outer periphery of the wafer elements after the beveling operation without protecting the metallizing from the caustic etch. Preferably, potassium hydroxide is used for the etching 120 operation and citric acid is used for a final rinse. Sodium hydroxide can also be used as the etchant. Since no protection is necessary for the metallizing system during the etch of the periphery of the device, several process steps are saved as compared 125 to the prior beveling operation employing an acid and a nickel plated aluminium contact.

The process may be used for manufacture of high power semiconductor devices which can, for example, be silicon controlled recitifiers having reverse voltages up to 5,000 volts and forward cur- 2 GB 2 168 843 A rents greater than about 50 amperes. However, the process can be applied to any high power device which employs an expansion plate contact and/or a beveled outer periphery.

When polished silicon is to receive a contact, an etching process may be used for removal of from 1 to 3 microns of the silicon surface before applying the first nickel coating. When the etch is less than one micron, delamination at the nickel-silver layers 10 is observed. At greater than 3 microns, the gate voltage and current characteristics of a controlled rectifier device are adversely affected. One manner in which the silicon surface can be treated is through the use of an etchant employing two parts 15 of hydrofluoric acid, nine parts of nitric acid and four parts of acetic acid. The etching solution is applied to the silicon surface-for approximately 15 seconds. This will remove approximately 2 microns of a polished silicon surface.

Immediately following the etching step, a layer of nickel is evaporated onto the treated silicon surface to a thickness from 125 Angstroms to 1, 000 Angstroms. The nickel layer will form a silicide in the vacuuM chamber if there is a moderate degree 25 of substrate heating (100'C is more than sufficient) and if there is a very clean silicon surface. During the nickel layer evaporation, the heat radiating from the boiling nickel surface will supply considerable energy to the wafer surfaces. Also, the 30 evaporating nickel atoms themselves impact with considerable kinetic energy. Excellent results have been obtained at evaporation temperatures as low as 60'C. At 120', the four-layer metallization adheres strongly to the underlying oxide and it be- 35 gins to be difficult to shake it loose from the oxide. The nickel thickness is critical. If too thick, above about 300 Angstroms, peeling will occur. If too thin, below about 100 Angstroms, the metallization will not release from the oxide. It has been found that if the metallizing layers overlap an oxide layer atop the silicon surface, the metallizing will easily lift off the oxide layer but will adhere very well to the treated bare silicon surface.

In addition to being unexpectedly adherent to the underlying silicon, but not to oxidized silicon, 110 the above metallizing system also has the follow ing characteristics:

(1) The system will survive alloying temperatures in subsequent processing steps-for the manufaG- 50 ture of a semiconductor device, such as temperatures of 6500C which are encountered in a vacuumalloying operation.

(2) The metallizing system makes good ohmic contact to silicon, whether of P type or N type and 55 of various resistivities.

(3) The metallizing system has a low lateral impedance (4) The metallizing system is covered by a silver layer and is thus resistant to chemicals employed 60 in many subsequent processing steps for the man- 125 ufacture of a semiconductor device..

(5) The metallizing system is resistant to thermal fatigue which might be encountered during the operation of the semiconductor device to which it is 65 attached.

(6) The metallizing system is solderable and does not require the use of additional soldering coatings for connecting leads to the metallizing.

The invention will be further described, by way 70 of example, with reference to the accompanying drawings, in which:

Figure 1 is a plan view of a semiconductor wafer which contains a large amount of individual devices which are simultaneously processed in a 75 wafer fabrication facility; Figure 2 is a cross-sectional view of Figure 1 taken across the section line 2-2 in Figure 1; Figure 3 shows one of the wafer elements of Figures 1 and 2 after it has been laser scribed from 80 the wafer in a prior art process;

Figure 4 shows the wafer element of Figure 3 after it has been alloyed to a molybdenum contact in a prior art technique;

Figure 5 shows the wafer of Figure 4 after a 85 masking and oxide etch step preparatory to the formation of a prior art contact system;

Figure 6 shows the wafer of Figure 5 after the evaporation of an aluminium contact onto the up per surface of the device in a prior art process;

Figure 7 shows the wafer of Figure 6 after the al uminium contact has been nickel plated and gold plated and lifted off the oxide, with the edges of the device ground and the upper surface of the de vice sprayed with a wax; Figure 8 shows the device of Figure 7 after the prior art steps of beveling, etching, wax stripping and application of a varnish to the outer periphery of the devicel Figure 9 shows the wafer of Figure 2 after a pho100 tolithographic masking and oxide etching of the unscribed wafer and after the novel silicon etch process to prepare the surface for metallization; Figure 10 is a greatly enlarged view of a portion of the full wafer of Figure 9 after metallization by 105 four sequential metal layers which strongly adhere to the treated silicon surface-, Figure 11 shows the structure of Figure 10 after a sinter and lift-off process in which the metallizing lifts off the oxide coating on the silicon wafer; Figure 12 shows one wafer element separated from the wafer of Figures 2, 9, 10 and 11 by a laser-scribing operation and shows a molybdenum contact which is subsequently alloyed to the wafer element; and 115 Figure 13 shows the device of Figure 12 after be- veling and treatment with a hot caustic etch and the application of a passivation coating to the outer periphery of the device.

Referring first to Figures 1 and 2, there is shown 120 a conventional silicon wafer 20, which can have any desired configuration, and which is shown in greatly exaggerated thickness for purposes of clarity. Typically, wafer 20 may have a diameter of 4 inches and a thickness from 10 to 40 mils, typically, 15 mils. The wafer is treated in a suitable wafer fabrication facility which provides extremely clean conditions for the processing of the wafer in any desired manner. By way of example, the wafer of Figures 1. and 2 was processed to form junction 130 patterns for a plurality of controlled recitifiers or GB 2 168 843 A 3 thyristors. Thus, the overall wafer 20 has a P-type layer 21 followed by an N-type layer 22, followed by a P-type layer 23. The plurality of controlled rectifiers to be formed have a centre gate configura- tion and are all provided with an N-type annular cathode region 24. The underlying P-type layer 21, which is the gate region for each device, is exposed at the centre of each annular region 24.

The final step in the wafer fabrication in the prior 10 art process for the overall wafer 20 is the formation of the cathode regions 24. During this step, which commonly is a diffusion operation, an oxide layer 26 grows on the surface of the wafer 20. This oxide layer 26 may have a thickness, typically, of 15.05 mils and is used in the subsequent processing of the device.

It would be desirable to continue with processing steps for completing the devices to be formed in the wafer of Figures 1 and 2 in the wafer fabrication facility which is best adapted for carrying out steps such as masking, oxide etching and the like. Moreover, it would have been desirable to metallize the various P and N regions at the surface of the wafer of Figure 2 which are to receive contacts or electrodes while the wafer is in the wafer fabrication facility. However, this could not be done with previously existing contact systems such as aluminium which would diffuse into the silicon during subsequent alloying steps necessary to fas- ten expansion plate type contacts to the bottom surface of the wafer elements. Consequently, in the prior art process, wafers 20 at the stage of manufacture shown in Figures 1 and 2 were removed from the wafer fabrication facility.

Wafer elements, such as elements 25 of Figure 3, were suitably separated from the wafer 20 as by a laser scribing operation. Seven individual circular wafer elements 25, each of which has a diameter, for example, of 0.75' are scribed from wafer 20 in the example of Figures 1, 2 and 3. Wafer elements 25, after their processing is complete, are to be used in controlled rectifiers which might have reverse voltage ratings of up to 5,000 volts and forward current ratings of greater than 50 amperes.

45 Different numbers of wafer elements can be cut from wafer 20, depending on the rating of the device to be formed. It will also be noted that the description of a preferred embodiment of the invention to follow hereinafter employs the exam-

50 ple of a controlled rectifier. However, the invention can apply to any device formed in the silicon wafer regardless of the number of junctions or junction pattern and would also apply to the manufacture of a single device in a single wafer.

All steps following the laser scribing steps of Figure 3 are usually carried out in an assembly area which is not as clean or well controlled as a wafer fabrication facility. However, the conditions in the assembly area are normally of sufficient 60 quality to permit carrying out of the subsequent steps to be described in Figures 4-8 for the prior art system.

In the first step carried out, and as shown in Figure 4 for the single wafer element 25, a plurality of 65 individual elements 25 are alloyed to expansion plate contacts such as contact 30 which can be of molybdenum or tungsten or the like. Typically, contact 30 will be a molybdenum contact having the same diameter as the wafer 25 and having a 70 thickness from 30 to 120 mils, typically 60 mils.

Note that the relative dimensions of the wafer and the contact are distorted in Figures 4-8 for pur poses of clarity. The alloying of the contact 30 to the wafer 25 takes place at a relatively high temperature. Therefore, the prior art alloying operation was carried out prior to the application of aluminium contacts to regions 23 and 24 of wafer 25 since an aluminium contact would diffuse into these regions at alloying temperatures and would

80 form a P-type region within the N-type region 24.

Thereafter, and as shown in Figure 5,, the upper surface of the individual wafer elements 25 is photolithograpically masked and the oxide layer 26 is etched to open an annular window 31 over the N- 85 type annular region 24 and to open a central win- dow 32 in the centre of each wafer element 25. The window 31 will subsequently receive a cathode contact for the controlled rectifier, while the central window 32 will receive a gate contact.

90 As shown in Figure 6, an aluminium contact layer 33 is next evaporated or otherwise applied onto the upper surface of each wafer element 25 with the photoresist on the oxide remaining in place. Layer 33 enters windows 31 and 32 to make 95 contact with the cathode and the gate regions of wafer elements 25. Aluminium layer 33 typically has a thickness of 5 mils.

The wafer element 25 of Figure 6 is then placed in an oven and exposed to an elevated tempera- 100 ture in neutral or reducing atmosphere in order to sinter the aluminium layer into the silicon surface and decompose the photoresist. The aluminium will not adhere to the underlying oxide layer 33 but adheres to the underlying decomposed photores- 105 ist. Therefore, after the sintering operation, the aluminium which overlies the oxide 33 is easily lifted off and aluminium remains only within the windows 31 and 32, adhered to the silicon surface of wafer element 25.

110 Thereafter, and as shown in Figure 7, the upper surface of the wafer is nickel plated with the nickel plating adhering to the upper surface of the alu minium contact 33. The nickel plate has a thickness of about.03 mils, and is solderable to subse- 115 quently applied leads. After the nickel plating step of Figure 7, gold is plated over the nickel to a thickness of 3,000 Angstroms. The nickel and gold layers are shown collectively by numeral 35. The gold plating is used to protect the underlying 120 nickel and aluminium from a subsequent acid etch. The upper surface of wafer element 25 is thereafter coated with a suitable wax coating 36 such as an apezion wax which protects the coated surfaces from attached by an acid etch to be subsequently 125 used.

Thereafter, and as shown in Figure 8, the outer periphery of the wafer 25 is beveled as by grinding. The bevel shown in Figure 8 has a first conical surface 40 which creates a first angle of intercep- 130 tion of the wafer boundary by the reverse junction 4 GB 2 168 843 A between regions 21 and 22 of about 3Y. A second conical surface 41 is also ground which has a sec ond interception angle between the outer periph ery of the wafer element and forward junction 5 between regions 22 and 23 from 2' to 10', typically 4'. Note that these angles are not shown to scale since the device dimensions have been greatly ex aggerated for purposes of clarity.

The device is next subject to an acid etch which 10 etches the outer periphery of the device. This acid etch cannot attack the remaining nickel-plated aluminium contact since it is protected by the overlying gold layer and wax layer. As shown in Figure 8, the wax coating 36 is then stripped away and the device is subjected to a light polish etch. A varnish layer 50 is then applied to the outer periphery of wafer element 25 to passivate the etched junction edges. A suitable silastic can also be applied to the wafer element.

20 The overall device of Figure 8 may then be suita- bly mounted in a device housing. Electrical con tacts can be made to the cathode and gate contact layers which are exposed through windows 31 and 32.

25 A process constituting a preferred embodiment 90 of the invention which replaces the process dis closed in Figures 3 to 8 is shown in connection with Figures 9 to 13. As shown in Figure 9 which is on the sheet of drawings containing Figures 1 and 30 2, the wafer of Figure 2, prior to the laser-scribing 95 operation, is subjected to a single photolitho graphic masking and etching step which opens windows in oxide layer 26 to expose the cathode and gate regions of each of the individual wafer 35 elements 25 before they are scribed from the wafer 100 20. Thus, as shown in Figure 9, windows 60 and 61 which are annular and central windows, respec tively, fie over respective annular cathode regions - 24 and central gate regions of each of water eie- ments 25 defined in the wafer 20. By way of exam- 105 -ple, the oxide etch process to open windows 60 and 61 can employ a conventional buffered oxide etch. This process is carried out in the wafer fabri cation facility which is designed for carrying out 45 such a process. Note that the equivalent mask and 110 etch process was carried out in the prior art in the step of Figure 5 for each of the individually-scribed elements 25 and in a wafer assembly facility.

Following the opening of the windows 60 and 50 61, the exposed surface of the silicon wafer 20 is 115 treated in a novel manner which enables desirable contact metals to adhere tenaciously to the tfeated silicon but not to the surrounding oxide. Thus, it would be desirable to employ a nickel, chromium, 55 nickel, silver contact metallization system for high 120 power silicon devices (those having a rated for Ward current greater than about 50 amperes) if the contact metals would reliably adhere to the under ly ng silicon surface after subsequent high temper 60 ature process operations, such as those employed 125 for alloying expansion plates to individual devices.

In the past, however, the adherence of the metals in such a system was not reliable since the upper silver layer frequently delaminated from the nickel 65 underlying the silver in an uncontrolled and appar- 130 ently arbitrary manner. Moreover, the bottom nickel layer sometimes bubbled away from the underlying silicon surface.

To ensure that the metallizing system will adhere 70 reliably to the underlying silicon, the following pretreatment of the silicon surface exposed through the windows 60 and 61 is used. After windows 60 and 61 have been opened by removal of the oxide in Figure 9, it was presumed that the exposed sur- 75 face of the silicon is oxide-free. In fact, there was an oxygen saturated layer of silicon below the silicon-silicon dioxide interface. Thus, there is sufficient oxygen released from the uppermost surface layers of the silicon substrate to cause nonadher- 80 ence and delamination of the metallizing layers during a subsequent sintering step. In the present process, a novel etch is employed to remove a sufficient thickness from the exposed silicon surface to ensure that the exposed surface is completely 85 oxygen-free. It has been found sufficient to remove from about 1 to 3 microns of the polished surface exposed through windows 60 and 61. Preferably about 2 microns should be removed.

It has been found that delamination problems exist if one micron or less of the surface is removed. If more than about 3 microns are removed, gate voltage and gate current characteristics are unacceptably affected.

The silicon etch preferably employs an etching solution consisting of 2 parts of hydrofluoric acid, 9 parts of nitric acid and 4 parts of acetic acid which are applied through the windows 60 and 61 to the exposed silicon surface of wafer 20 for about 15 seconds. Thereafter, the wafer 20 is placed in a tub rinse for about 5 minutes to flush away the acid.

Following the tub rinse, the wafer 20 is exposed to a light etch consisting of 50 parts of deionized water to 1 part of hydrofluoric acid for about 30 seconds. This step strips any chemical oxide which remains after the initial etch which employed nitric acid as one component. The wafer 20 is then rinsed in a tub rinse for about 5 minutes and is spun dry in the usual manner.

The metal layers 70 to 73 of Figure 10 are thereafter applied to the treated surface, by evaporation techniques in vacuum. For example, after pumping a vacuum for about 15 minutes, the substrate is heated to about 125'C. When the pressure has dropped to about 5 X 10-6 torr, a first nickel layer 70 is evaporated onto the surface to a thickness from 125 to 1,000 Angstroms, preferably 200 Angstroms. Nickel layer 70 should have a thickness sufficient to allow its conversion to nickel silicide during the deposition operation. The substrate should be at a temperature of 100'C or greater during the deposition of nickel to encourage its conversion to a silicide.

The purpose of the silicon etch step is to remove any source of oxygen in the treated surface. It is believed there is normally an oxygen saturated layer of silicon immediately below the SiO,/Si interface. If allowed to remain undisturbed, during silicide formation, it is believe that oxygen atoms in the involved region become highly mobile, and GB 2 168 843 A 5 diffuse upward to become trapped at the niGkel-sil ver interface to be formed. The final result is an oxidized film which destroys the nickel-silver inter face and delamination results.

In addition, the nickel layer 60 will bubble off the substrate if any oxygen is present in the substrate underlying the nickel after the metallizing system is completed. The etching of the silicon, however, re moves all traces of oxygen from the exposed mon 10 ocrystalline silicon wafer surface and solves delamination of the nickel-silver interface problem and the problem of release of nickel from the sili con.

Chromium, nickel and silver layers 71, 72 and 73, 15 respectively, are then separately evaporated onto layer 70, as shown in Figure 10. The wafer is there after allowed to cool to room temperature.

Chromium layer 71 has a thickness sufficient to act as a diffusion barrier, and can, for example, be from 500 to 3,000 Angstroms, preferably 1,500 Angstroms. Nickel layer 72 has a thickness suffi cient to prevent leaching of silver from layer 73 into layer 71 and can, for example, be 1,000 to 6,000 Angstroms, preferably 4,000 Angstroms.

Silver layer 73 is thick enough to receive solder connections and should be greater than about 1 micron, and may be 6 microns. Following the metal deposition operation, a lift-off process takes place in which the nickel layer 70, and the metal 30 layers 71, 72 and 73 disposed atop the underlying oxide layer 26 are lifted off the oxide, as shown in Figure 11.

To carry out the lift-off process, the wafer 20 is immersed in cleionized water containing a deter 35 gent and is exposed to ultrasonic energy for about minutes to loosen the metal on the insulation layer 26. The wafers are then exposed to a spray of cleionized water which flushes away all of the loose metal which overlies the silicon dioxide layer 40 26. The wafer is then tub rinsed and spun dry and inspected for residual metal. Any residual metal can be blown off with a jet of nitrogen gas.

The wafer 20 now has the general appearance shown in Figure 11, wherein layers 70, 71, 72 and 45 73 are firmly adhered to the areas exposed in win dows 60 and 61. The metallizing will survive tem peratures which are subsequently applied to the device during alloying or other processing steps.

Furthermore, the metallizing will be resistant to 50 certain chemical etches which are subsequently applied to the wafer elements 25. Further, the me tallizing makes low resistance connection to either P-type or N-type silicon and the contacts are sol derable, have low lateral impedance and are resist 55 ant to thermal fatigue. The metallization system also makes possible a novel improved process for completing the structure of the wafer 25, as shown in Figures 12 and 13. More specifically, the new metallization system permits vacuum alloying of 60 individual wafer elements to expansion plates after 125 metallizing. This is because there will be no ad verse contact metal diffusion or damage during al loying, and because the edge of the junction can be etched by a caustic etch which will not attack the overlying silver of the metallizing system. 130 Thus, for the next step of the overall process, individual metallized wafter elements 25 of Figure 1 are cut, as by laser scribing,from the wafer 20 of Figures 9, 10 and 11. Each individual wafer element 25 is then alloyed to an expansion plate such as plate 80 shown in Figure 12. The expansion plate 80 can, for example, be a molybdenum disc having a thickness of 60 mils. The vacuum-alloying process takes place in nitrogen at a pressure of 75 about 4 x 10-5 torr, at a temperature of about 650'C for about 30 minutes. A large number of wafer elements 25 are simultaneously processed. Since the vacuum alloying process of Figure 12 takes place after the contact metals have been ap- 80 plied, the plural steps of the prior art process of

Figures 5, 6 and 7 are eliminated.

Following the alloying step, the outer peripheral surface of individual wafer elements 25 are ground on a diamond wheel, for example, to form a first 85 ground conical surface 90 shown in Figure 13. Surface 90 can form an angle of about 35' relative to the junction between regions 21 and 22. Thereafter, a second conical surface 91 is ground, which has an angle to the junction between regions 22 90 and 23 of about 4'. These angles are not shown to scale in Figure 13. The wafer elements 25 are then rinsed with cleionized water and cleaned in an ultrasonic cleaning bath.

Thereafter, the outer ground periphery of the 95 wafer 25 is subjected to a novel caustic etch which removes the damage caused at the outer periphery by the grinding operation. The novel caustic etch step can be carried out without the need for a protective gold plating or wax or the like on the metal- 100 lizing layer since the silver layer 73 is resistant to the caustic etch. The caustic etch fluid is preferably potassium hydroxide.

More specifically, about 80 grams of potassium hydroxide in about 1 litre of deionized water is 105 heated to about 95'C to 100'C. A solution of 80 grams of citric acid in about 1 litre of cleionized water at room temperature is also prepared. The wafer elements 25 are first placed in hot running cleionized water for about 1 minute. They are 110 thereafter placed in the potassium hydroxide solution for approximately 3 minutes with the support fixture containing the wafer elements 25 being constantly agitated. The wafer elements are then removed from the potassium hydroxide solution 115 and placed in hot running deionized water for about 3 minutes.

Thereafter, the wafer elements are placed in the citric acid solution for approximately 30 seconds while being constantly agitated. The wafer ele120 ments are then immersed in hot running deionized water for about 2 minutes and are then appropriately dried as by irradiation under an infrared lamp.

The wafer elements 25 are then loaded into a coating tray and their surfaces are coated with a suitable pacification coating 100 as shown in Figure 13. The coating 100 may be of any desired type. Preferably the coating is a silastic such as Q 1-4935 manufactured by Dow-Corning Company. After coating with the silastic medium, the wafer 6 GB 2 168 843 A elements 25 are placed in a vacuum chamber for about 10 minutes and are thereafter heated to about 3250C for about 20 minutes. The completed wafer elements can then be mounted in a suitable 5 housing or otherwise further processed.

Claims (14)

1. A method of making a plurality of identical 10 semiconductor devices which are simultaneously processed and metallized with plural metallizing layers while they are parts of a common thin, flat silicon wafer having substantially parallel first and second surfaces, the metallizing being intimately 15 secured in ohmic contact with a plurality of spaced portions of the first surface and being capable of withstanding temperatures which are encountered in subsequent processing steps, the metallizing including a non-junction-forming metal in contact 20 with the first surface of the wafer and an outer so[derable metal layer which is non-reactive to a caustic etch, the method comprising the steps of: separating a plurality of wafer elements from the wafer with each of the wafer elements having at 25 least one respective metallizing area on at least a portion of the first surface thereof; -secu ring a respective expansion plate contact to the second surface of each of the wafer elements; and etching the outer periphery of each of the wafer elements 30 with a caustic etch.

2. A method as claimed in claim 1, including the step of flushing away the caustic etch with a weak acid.

3. A method as claimed in claim 1 or 2, in which the caustic etch consists of potassium hydroxide and the method includes the further step of flushing with citric acid after the potassium hydroxide is in contact with the outer periphery of each of the wafer elements for a given time.

4. A method as claimed in any one of claims 1 to 3, in which each of the expansion plates is secured to respective ones of the wafer elements by vacuum alloying at temperatures of about 650'C.

5. A method of making a plurality of identical 45 semiconductor devices, substantially as hereinbefore described with reference to and as illustrated in Figures 1, 2, and 9 to 13 of the accompanying drawings.

6. A silicon wafer or semiconductor device made by a method as claimed in any one of the 115 preceding claims.

7. A method of metallizing a surface portion of a monocrystalline silicon wafer comprising an initial step of removing at least one micron thickness from said surface portion to ensure removal of unintended oxygen contamination in said surface portion, and thereafter depositing a thin layer of nickel onto the surface portion and converting at least a portion of the thickness of the nickel layer to nickel silicide, and depositing at least a layer of a contact metal atop the layer of nickeIr the contact metal layer being tenaciously fixed to the surface portion.

8. A method of metallizing a plurality-of ex- posed surface portions of a silicon wafer, which surface portions are for respective identical wafer elements which are subsequently to be separated from one another, wherein the metallizing surface is capable of surviving process temperatures of 70 greater than about 650'C and makes ohmic contact with N or P type silicon and is resistant to a large variety of chemical etches and is easily solderable; the method comprising the steps of: applying an insulation coating to a surface of the silicon wafer; 75 photolithographically masking and etching through said mask to expose at least one predetermined surface portion of the surface through the insulation coating; thereafter removing at least a one micron thickness from the surface portion while 80 leaving the insulation coating intact to ensure removal of unintended oxygen contamination in the surface portion; depositing a thin continuous layer of silicide-forming metal atop the surface portion and atop adjacent surfaces of the insulation coat- 85 ing and converting at least a portion of the thickness of the silicide- forming metal to a metal silicide; depositing at least a layer of contact metal atop the layer of said silicide-forming metal; applying a delaminating stress to the metal layers to re- 90 move the silicide-forming layer and the contact metal layer from atop the insulation coating, with the silicide-forming layer and the contact layer strongly adhering to the surface portion of the silicon wafer; cutting apart the silicon wafer into a 95 plurality of wafer elements which all contain at least one of the plurality of exposed surface por tions; and thereafter further processing each of the plurality of wafer elements to complete respective semiconductor devices.

9 A method as claimed in claim 7 or 8, in which at least one micron thickness is removed from the surface portion by an acid etch.

10. Amethod asclaimed in claim 7 or8, in which the thickness of material removed from the surface portion is from one to three microns.

11. Amethod asclaimed in claim 9 or 10,in which the acid etch consists of a mixture of hydro fluoric acid, nitric acid and acetic acid which is ap plied to the surface portion for about 15 seconds.

110

12. A method as claimed in any one of claims 7 to 11, in which the nickel or silicide-forming layer has a thickness in the range of from 125 Angs troms to about 1,000 Angstroms.

13. A method as claimed in any one of claims 7 to 12, in which the contact metal layer is of a ma terial which is resistant to caustic etch.

14. A method as claimed in claim 13, in which the contact metal layer is of silver.

120 Amendments to the claims have been filed, and have the following effect:

(a) Claims 7 to 14 above have been deleted.

Printed in the UK for HMSO, D8818935, 5186, 7102.

Published by The Patent Office, 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained.