GB2160073A - Circuit arrangement for the peripheral controller of stored program controlled telephone exchanges - Google Patents

Abstract

The peripheral control unit of a stored program controlled telephone exchange is connected to the controlled telephone exchange peripheral by means of an operating data bus OPB, a scanning data bus SB, a peripheral address bus PAB, by peripheral selecting signals PSB and a peripheral strobe signal STR, through a multicircuit input-output unit I/O. The circuit arrangement comprises a central processing unit CPU, a bus cycle time extending unit RY, a means selecting unit SEL, a memory unit M and an optional communication unit COM. Between the unit RY and the unit I/O a peripheral sequence controller PSC is inserted, which is connected to all circuits of the unit I/O through timing outputs, and which is suitable for controlling the peripheral write and read operations independently of the internal bus cycle of the peripheral control unit and in compliance with the requirements of the telephone peripherals by means of special sequences. Assignment of the unit I/O takes place in the memory address range, and the internal bus operation is suspended by the unit RY for the periods of peripheral operation, permitting the operating program to perform the handling of peripherals by means of normal memory based instructions. <IMAGE>

Description

SPECIFICATION Circuit arrangement for the peripheral controller of stored program controlled telephone exchanges Subject of the invention is a circuit arrangement proposed for the peripheral controller for the peripheral controllerforstored program controlled telephone exchanges, where said controller is connected to the telephone peripheral by means of an operating data bus, a scanning data bus, a peripheral address bus, peripheral selecting signals and peripheral strobe signals, and where special write and read sequences are generated by said control unit for the peripherals.

In stored program controlled telephone exchanges the control functions required for their operation are accomplished by one or several control units. The telephone exchange and parts thereof are treated by the control units as peripherals. This implies that a control unit acquires information of the momentary state through peripheral read operations, whereas the control functions are performed by peripheral write operations.

In small-size telephone exchanges the control functions and the handling of peripherals are accomplished within a single control unit. In larger exchanges the usual arrangement is to separate physically the functions of peripheral handling from the control unit and to accomplish these functions in one or several peripheral control units. Thereby, a single control unit becomes capable of handling a number of peripherals /such as larger exchanges or parts thereof/, which may be located some distance apart.

In such cases, the task of a peripheral control device is to match the interface linked up with the control unit generally having a computer-like character, to the special interface of the peripheral belonging to the telephone part. A drawback of this arrangement lies, on the one hand, in the requirement of highspeed parallel links to cope with the large quanitity of transmitted data and, on the other hand, in the limitations imposed on the lengths of these links.

In another usual arrangement, also the peripheral controlling unit itself is provided with a programmable logic. This offers the advantage of lending itself, in addition to interface matching, to execute certain control functions as well. Preferably, some preprocessing functions closely associated with the telephone peripheral are performed in close vicinity of said peripheral. This method has the advantage of offering the possibility of decentralizing some tasks of frequent occurrence but of limited processing demands relieving thereby the control unit, permitting the latter to provide service for a greater part of the exchange with an increased number of facilities.

At the same time, the required volume of data transfer decreases as well, permitting adoption of less expensiVe and longer-distance series connections.

In a further arrangement, all control functions belonging to a given part of the exchange can be accomplished in the vicinity of the peripheral. In such cases, the control unit is realized as one composed of autonomous peripheral controllers and of parallel processors with communications links between them.

A common feature of all arrangements mentioned is the required of having a special interface toward the telephone peripherals. This interface is unified and well specified for each equipment or group of equipment. From the character of the telephone peripherals follows that the peripheral control unit is required to read or operate a large number of peripherals. Usually, the state of peripheral circuits is read by means of scanners, and operation is performed with the help of distributors. Multiplexing and demultiplexing of such large number of scanners and distributors can be accomplished partly at the peripheral itself. In one commonly adopted arrangement, the distributor demultiplexers and scanner multiplexers are incorporated in the peripheral control unit. This simplifies the circuitry of the peripheral, but requires a large-size peripheral control unit.With another usual arrangement, the peripheral control unit is coupled to the peripheral through scanning and distributing buses. The peripheral control unit contains scanner and operating peripheral registers that can be assigned to form groups, and the state of which can be read from or written to the peripheral, e.g. by means of a parallel 110 port. With both arrangements mentioned above, a problem is imposed by the peripheral circuits requiring, in certain cases, for accomplishing the function of scanning and distributing, special read and operate sequencing considerably differing from the internal functioning of control.Although various approaches are known for handling low-speed circuits leg. the WAIT-READY method, additional units ispecial I/O PC boards, etc. have to be provided for satisfying such special sequencing requirements.

Programmed sequence control is through possible, this renders the run of the peripheral handling program slow and cumbersome, the resolution of the realizable control sequences along the time axis will become coarse and insufficiently manageable and, in certain time ranges, it will become absolutely unsuitable for being used.

For applications in the telephone techniques, the ITT 0802 microprocessor system is known, among other uses, as peripheral control unit. The group of PC boards contains, among others, a central processing unit board CPU 0802i which can be used as a single-board microcontroller, and incorporates a parallel input board /PIB 0802 for periphery scanning suitable for scanning a 56+6 bit peripheral, and a parallel operating board POB 0802/ suitable for operating a 56+6 bit peripheral. The different variants of the system are suitable for single-board control of small-size telephone exchanges, in a larger system as pre-processing data processor, or in systems provided with distributed control as control units of subsets.

The CPU 0802 is equipped with two interfaces.

One is the 0802 system bus designed according to computer techniques and to establish connection with the other units /boards/ of the system. The other is 3x8 bit programmable input-output circuit para- llel 110 portl. In single-board applications, this peripheral is preferably used as interface. By this unit, special periphery write and read sequences can be operated by means of program control. For handling low-speed peripherals, it applies the WAIT/ READY method commonly used in computation techniques Ikeeping the central processing unit waiting for a given period in order to extend the bus cycle time/. The handling of several peripherals may also require one or more PIB and POB units.To increase the number of scanned circuits and to produce the required special scanning sequence, autonomous scanning subsystem SCC 0802 is used, which is suitable for scanning 1024 circuits. This subsystem consists of several modules /boards/ and it is connected to a 0802 system bus.

The ITT 0802 control unit, matched to the other units of the exchange, is linked up with other co-operating units through series communication board SIO connected to the 0802 system.

The main advantage of the control system described above, when used in the telephone technique, is its universal modular design. But, also its drawbacks arise from this feature, since in practical applications as peripheral control units, as singleboard control circuits, or as subunft for controlling parallel processors, it is difficult to adapt them to a given task, just because of their universal setup. As a single-board processors, they are capable of solving but very limited tasks, due to the small number of available peripheral connection points and owing to the programmed sequence control.For the purpose of controlling larger subunits, and for the programindependent realization of special peripheral sequences, as well as in applications as pre-processors and parallel data processors, large systems require the use of several P.C. boardsforthe accomplishment of communisations tasks.

The object of realizing our invention has been, by eliminating the deficiencies outlined above, to create in the field of telephone technique a single-board programmable peripheral controller which is capable of ensuring, through a properly selected interface, the special read and write sequences required by the peripherals of telephone systems.

Accomplishment of our set aim has been rendered possible by the recognition that by combining certain details of circuitry known from computer and telephone techniques, as well as by introducing an expedient new subunit, the peripheral sequence controller suitable for realizing any kind of peripheral write and peripheral read sequences functioning independently of the internal operation of the peripheral control unit, an economical, small-size circuit arrangement satisfying the above requirements can be created.

In realizing our invention we have set out from a circuit arrangement commonly used for control purposes in telephone technology. This arrangement contains a central processing unit, a memory and an l/O urTtt communicating with one another through an internal bus. Task of the central processor unit is to carry out the control programs, that of the memory is to store system programs and data, while the l!O unit serves to read the scanned data of the controlled peripheral and to write out the operating data. Optionally, a communication unit can also be included having the task in a multiprocessor system to ensure communication among processors. This arrangement has permitted to create a small-size programmable peripheral controlling circuit.To permit handling of slow peripherals, the usual method of inserting between the central processor and I/O unit a circuit for extending the duration of bus cycle time has been adopted, whereby, when a peripheral is addressed, the duration of the peripheral write and read operations is lengthened as required by the slow circuit concerned.

Because of the large number of controlled peripherals of the telephone circuitry, a parallel I/O unit is employed, which is connected to the peripheral through a unidirectional scanning bus, a unidirectional controlling data bus, a peripheral address bus, with peripheral selecting signals and a peripheral strobe signal. This arrangement has the advantage of offering the possibility of optimal sharing the address decoding and data multiplexing process between the peripheral and the liO unit, whereby the IIO unit is rendered capable of accessing a large number of peripherals by means of few circuit elements, permitting at the same time, simplification of the peripheral.

As usual practice,the IIO unit is assigned so as to permit the central processor unit to access the 110 unit in the memory address range. The main advantage of this feature manifests itself in the field of programming.

The circuit arrangement outlined above may represent an expedient and economical embodiment of the single-board peripheral controlling unit complying with our objective described. its application, however, is hindered by the problem that the I/O unit is required to co-operate with the telephone peripheral according to a write and read sequence specific to the circuits used in telephone technique, and differing from the operation of the internal bus.

This is eliminated by extending the duration of the bus cyde time only so far that it renders possible the use of peripherals of longer recovery times, but the peripheral controller will still remain unsuitable for accomplishing special addressing, allocation and data write-read sequences. The arrangements known so far have been able to solve this problem at the expense of serious drawbacks.

The essence of our invention is the implementation of peripheral write-read sequences specific to the circuits of the telephone technique by means of inserting between bus-cycle time extending circuit and I/O unit a new unit, termed periphered sequence controller, coupled with its one or several outputs to all subunits of the IIO unit.

Advantage of this arrangement is the controllability of all signal groups of the peripheral interface, independently of each other and of the course of the internal bus cycle in the function of time and, thereby, it is rendered capable of accomplishing any desired peripheral write/read sequence.

A further advantage of the circuit arrangement complying with the invention consists of providing the possibility of applying a very effective peripheral interface by means of which the peripheral controller becomes capable of handling more peripherals of the telephone circuitry than the single-board variants used hitherto.

A still further advantage of the arrangement proposed by the invention is that, by realizing peripheral interfacing effectively and by means of a small number of circuits, it permits to complete the peripheral controller, within the board, with an optional serial communication unit to fulfil the tasks of a computer-like interface towards possible cooperating units, whereby the periphery controller can be rendered equally suitable for solving the tasks of an independent controller, a pre-processor or a parallel processor.

In the following, the subject of the invention is described with reference to the attached drawings representing an exemplary embodiment of the invention, wherein Figure 1 shows the invented a circuit arrangement devised for the circuitry of a stored program controlled telephone exchange peripheral controller on hand of a block diagram; Figure 2 shows the block diagram of the 110 unit, as applied in the embodiment of the invention, is shown, where its connections to the peripheral sequence controller are also indicated in some detail.

With the circuit arrangement according to the invention, the peripheral controller incorporates a CPU central processor unit, a memory unit M, an I/O unit consisting of several circuits, a cycle time extending unit RY, a means selecting unit SEL, an optional communication unit COM, an internal bus IB providing connection between units, a peripheral bus maintaining connection with the outside world, and a peripheral sequence controller PSC inserted between the bus cycle time extending unit RY and 110 unit. The peripheral bus PB consists of operating data bus CPB, scanning data bus SB, peripheral address bus PAB, peripheral selecting signals PSB and peripheral strobe sgianl STR.To internal bus IB the CPU central processor unit is connected with its first output CB, as well as the memory unit M, communication unit COIl, I/O unit, means selecting unit SEL and peripheral sequence controller PSC, also with their first inputs MB, HB, IB, SB, CBP, respectively. Bus cycle time extending unit RY is connected through its first output R to the second input RDY of the centra processor unit CPU and to the third input PEN of peripheral sequence controller PSC, further through its second output RY to the fourth output RYP of peripheral sequence controller PSC. Again, the peripheral sequence controller PSC is connected through its second input PSE to the second output PSEL of means selecting unit SEL, and through its timing outputs CO to the timing inputs CI of the IIO unit.

The I/O unit contains operating driving circuit OB, scanning bus read circuit IL, peripheral address bus driving circu# AB, peripheral decoder circuit SD and peripheral strobe driving circuit STB. Timing outputs CO of peripheral sequence controller PSC are connected to data enable input ODE of operating bus driving circuit OB, to scanned data read input PRD and to scanned data sampling input IDW of scanning bus read circuit IL, to peripheral address enable input AEN of peripheral address bus driving circuit AB, to peripheral selection enable input SEN of peripheral decoder circuit SD and to peripheral strobe signal input SRI of peripheral strobe signal driving circuit STB.

Operation of the described example of the embodiment of the invention is as follows: The control program stored in memory M is carried out by the CPU central processor unit. The control program communicates with the telephone peripheral by means of scanning and operating functions through the I/O unit. These scanning and operating functions are effected by memory read and memory write instructions included in the program, since the I/O unit is assigned by selecting unit SEL in the memory address range. This offers the advantage of performing the often occurring peripheral scanning and operating functions by the much more efficient memory-based instructions.

Means selector unit SEL recognizes the address of the i/O unit from the address information present on internal bus IB, then, with the help of command and clock signals arriving through the command bus, it starts the synchronized run of bus cycle time extending unit RY. First output RYC of the latter brings about a state of waiting through second input RDY of the CPU central processor unit, preventing thereby the termination of the bus cycle.

Peripheral sequence controller PSC is started through its second input PSE by means selector unit SEL at the beginning of the bus cycle. From the signals of the command bus connected to its first input CBP, peripheral sequence controller PSC recognizes the type /write or read; of the bus cycle, and through the clock signal it is capable of performing time measurements as well. Bus cycle time extending unit RY indicates at its third input PEN that the bus cycle has been brought into waiting state, whereupon peripheral sequence controller PSC commences the execution of peripheral operation.

PSC contains a sequential circuit which measures the time elapsed since the beginning of the bus cycle and produces for each discrete time interval a definite combination of clock outputs CO for controlling the course of peripheral operation through the clock inputs of the l/O unit. After having performed the peripheral operation, a signal is issued by peripheral sequence controller PSC to bus cycle time extending unit RY through the fourth output RYP of PSC, removing thereby the signal from the first output RYO of RY, terminating thereby the bus cycle.

In the described embodiment of the invention, in the case of peripheral reading, i.e. in the course of scanning, peripheral sequence controller PSC performs, through its clock outputs CO, the following control functions: At the beginning of an operating function, the peripheral address bus driving circuit AB is opened by the input of peripheral address enable circuit AEN, and the corresponding part of the address present on internal bus IB appears on the periphery address bus.

After stabilization of the peripheral address bus and after the elapse of time specified for the activation of the address decoders of the peripheral, the peripheral decoder SD is enabled through its peripheral selection enerable input SEN, and peripheral selecting strobe signal PSB corresponding to the address is activated, whereby the scanning gate is started. Simultaneously, the scanned data sampling input IDW of scanning bus read circuit IL enables the scanned data to be entered. After the access time specified for the scanning gates, the data to be entered get stabilized on scanning gates, the data to be entered get stabilized on scanning bus SB. Now, on scanned data sampling input IDW of scanning bus read circuit IL, the write enable state ceases and the scanned data gets stored.Simultaneously, peripheral selecting signal SPB cases, then after the elapse of the hold time specified for the peripheral address bus, the peripheral address enable input AEN of peripheral address bus driving circuit AB is disabled. On completion of peripheral operation, at the end of the bus cycle, under the effect of a read signal applied to scanned data read input PRD of scanning bus read circuit IL, the scanned data appears on the data bus of internal bus IB, so it can be read by the CPU central processor unit.

Control of peripheral takes place as follows.

Similar to scanning, first the peripheral address bus is enabled. Simultaneously, an enable signal is given through the input of operating data enable circuit ODE, to the driving circuit of operating bus OB, under the effect of which the data present on internal bus IB is transferred to operating data bus OPB. In the next phase, peripheral strobe bus STB and peripheral decoder circuit SD are enabled, which generate the write pulses required for the peripheral stores and the gated selecting signal needed for other operations. After ceasing of this enable state, the peripheral operating data and peripheral address remain enabled for the specified hold time, then, in the next phase, also these data cease and the peripheral operation comes to an end.

Claims (2)

1. Circuit arrangement of a peripheral controller of stored program controlled telephone exchanges, comprising a central processing unit, a memory unit, an input-output unit consisting of several circuits, a bus cycle time extending unit, a means selecting unit, an optional communication unit, an interal bus to establish connection between the units and a peripheral bus keeping connection with the outside word, and where said peripheral bus incorporates a data bus to operate a scanning data bus, a peripheral address bus, a peripheral selecting signal and a peripheral strobe signal, where to the internal bus a central processor unit is connected through its first output, and to which the memory unit, the optional communicaRion unit, the input-output unit and the means selector unit are connected through their first outputs, and the input-output unit is connected through its second output to the peripheral bus, further the bus cycle time extending unit is con nected through its first output to the second input of the central processing unit, characterized by the peripheral controller comprising a peripheral sequence controlling unit/PSC/ being connected by its first output /CBP/ to an internal bus /IB/ by its second input /PSE/ to the second output /PSEL/ of a means selecting unit /SEL/ by its third input IPENI to the first output /RYO/ of a bus cycle time extending unit IRYI, and by its fourth output /RYP/ to the second input IRYII of the bus cycle time extending unit IRYI, further by timing outputs /CO/ contained by the peripheral sequence controller/PSC/, said clock outputs /CO/ being connected to the clock inputs of the input-output /1/0/ unit.

2. Circuit arrangement as claimed in claim 1, where the input-output unit comprise an operating bus driving circuit, a scanning bus read circuit, a peripheral address bus driving circuit, a peripheral decoder circuit and a peripheral strobe signal driving circuit, characterized by the clock outputs /CO/ of the peripheral sequence controller /PSC/ being connected to the operating data enable input /ODE/ of the operating bus driving circuit IOBI, to the scanned data read input /PRD/ and scanned data sampling input /IDW/ of the scanning bus read circuit II LI, to the peripheral address enable input /AEN/ of the peripheral address bus driving circuit IABI, to the peripheral selection input /SEN/ of the periphery decoder circuit /SD/ and to the peripheral strobe signal input /SRI/ of the peripheral strobe signal driving circuit/STB/.