GB2157516A - Delta modulator - Google Patents

Abstract

Analog-to-digital converters specifically optimized for use in seismic applications operate on the delta or delta-sigma modulator principles. A single incremental step voltage is supplied to a pair of field effect transistors 60, 62 controlled by logic circuitry 12 for supplying the incremental step voltage to an inverting op amp 72 supplying an integrator 16 for generating a predicted value g(t), whereby the effects of component instabilities or mismatches are minimized. <IMAGE>

Description

SPECIFICATION Method for Analog-to-digital Conversion and Converter Therefor This invention relates to improved circuitry for analog-to-digital conversion of seismic signals. More particularly, it relates to analog-to-digital converters for seismic signals which use delta and delta-sigma modulation techniques and which provide an improved signal to noise ratio coupled with superior resolution of signals of widely varying amplitude.

It has been commonplace in the seismic signal processing art for some time to convert analog signals output by geophones and hydrophones detecting return of a seismic wave after reflection from a rock layer within the earth into digital format for convenient storage and data processing. The search for improved analog-to-digital converters for this purpose has been incessant. Typical goals of improved analog-todigital converters include increased signal-to-noise ratio coupled with improved resolution. The amplitude of seismic signals of interest varies greatly, over at least as much as 100 d B. Moreover, very faint signals are frequently superimposed on very large signals.Accordingly, it is not merely sufficient to discriminate faint signals from noise, which could be possible using gain ranging amplifiers or the like, but it must also be possible to distinguish small signals superimposed on large signals from such large signals without destroying the relative amplitudes thereof if meaningful processing of these signals is to be carried out.

Accordingly, the art has recognized that improved analog-to-digital converters are required.

GB-A-21 31241 and G B-A-21 30829 describe respectively the use of delta and delta-sigma modulation in analog-to-digital conversion of seismic signals and the analog-to-digital conversion of seismic signals using differential pulse code modulation. The present invention relates to circuits for implementing the first of these, that is, delta and delta-sigma modulation for use in analog-to-digital conversion of seismic signals.

It will be apparent that in a design of any such circuit the accuracy of the digitized analog signal is of paramount importance, and this should be maintained insofar as possible without dependence on ambient temperature or component age, as well as such things as variation in humidity and the like, all of which tend to cause inaccuracy of electrical component values.

It will also be apparent that it is desirable to provide such a circuit which would be relatively straighfforward to assembly using readily available components, and that no extraordinary shielding or other complexities be required for its successful operation.

The term delta modulation is understood generally to be an analog-to-digital conversion process in which a series of single bits are output as a digitized signal. The meaning of each bit, however, varies in accordance with the specific modulation principle employed. For example, one process compares a sample of the analog value to be encoded at a point in time with a predicted value for that analog value. A "one" may be output if the predicted value is higher than the input value and a "zero" or negative "one" if it is lower. In the simplest case the sampled value is simply compared to the previous sample. If the present sample is higher, i.e. the wave form is increasing in value, a "one" is output; if on the other hand the waveform is declining, a "zero" is output. Other forms of generating a predicted value are also possible.A running sum of the bits output may be used as the predicted value. Alternatively, some incremental value may be added to or subtracted from the previous predicted value in dependence on the result of one or more previous comparisons. In this case the signal output, a stream of ones and zeros, may be regarded as an encoded version of the difference between the predicted and actual values, or "error" signal. For example, where the error is positive a one is output and where it is negative a zero is output. If the sampling rate is sufficiently high compared to the bandwidth of the input signal, a quite good signal-to-noise ratio can be developed. This is the approach adopted here; examples of achieveable signal to noise ratios are given below.

In delta-sigma modulation the error which is encoded is instead the predicted value minus the integral of the actual input value. This has the advantage of smoothing the input signal and in some cases the circuitry involved can be simplified over basic delta modulation. An example of such a circuit is also given below.

For purposes of clarification, reference should also be made to techniques broadly referred to as differential pulse code modulation. In this encoding scheme analog-to-digital conversion is again accomplished by comparison of a predicted analog input signal to an actual analog input signal, the difference or error signal being encoded. However, rather then encode the error signal as a single bit, the error may be coded with multiple bits. In this way the error signal can be encoded with higher resolution, substantialy larger error signals can be accommodated without overload for a given least significant bit value, and the sampling rate required to achieve a given signal-to-noise ratios can be much lower than in the single bit delta modulation method. However, the hardware involved is somewhat more complicated and in many cases more expensive.Such techniques are broadly described in GB-A-2130829 mentioned above.

According to the present invention, there is provided a delta modulator circuit in which incremental values of predetermined size are added or subtracted to an integrated predicted value in response to comparison of actual and predicted values. The polarity of the change is controlled by turning on one of a pair of field effect transistors operating as semiconductor switches. The size of the step is set by the same device regardless of its polarity, whereby both positive and negative-going changes are of equal magnitude, so that long-term drift in component values and the like do not lead to inaccurate responses.

Providing additional integrator stages allows the delta modulator to function as a delta-sigma modulator, the output of which need merely be low pass filtered to generate a digital value.

The invention will now be described in greater detail by way of example only with reference to the accompanying drawings, in which: Fig. 1 shows the general arrangement of seismic exploration operations; Fig. 2 shows a block diagram of a single integration delta modulator unit, as well as the decoder used to generate periodically sampled digital output words; Fig. 3 shows a breadboard block diagram, i.e., a block diagram of a circuit actually used to implement the delta modulator; Fig. 4 shows the test arrangement for the delta modulator; Fig. 5 shows a detailed circuit diagram of the delta modulator; Fig. 6 shows a block diagram of the delta-sigma modulator; Fig. 7 shows a compact and simplified form of the delta-sigma modulator of Fig. 6; Fig. 8 shows a breadboard delta-sigma modulator in block diagram form;; Fig. 9 shows a block diagram of the delta-sigma modulator test setup; and Fig. 10 shows a detailed schematic diagram of the delta-sigma modulator.

Differential pulse code modulation encoders for use in analog-to-digital conversion have been available for several decades. These are typically viewed as circuits which reduce transmission bandwidth and circuit complexity while achieving good instantaneous dynamic range. Broadly stated, the technique employed involves encoding the difference between a signal of interest and an estimate thereof; that is, encoding an error signal. Typically, the harmonics and intermodulation products of the input signal dominate the error signal spectrum.

If the estimate approaches the signal of interest accurately, then the resulting error signal is small. The error signal can accordingly be encoded with a small number of bits as compared to the number of bits required to represent the absoiute input signal amplitude to the same degree of accuracy of the least significant bit. Moreover, the information content of the signal can be entirely preserved. The concept is carried to the extreme case in delta and delta-sigma modulators as involved here wherein the error signal is encoded with a one bit digitizer.

The reason for interest in this type of encoder is their potential to measure signals of wide instantaneous dynamic range without the use of inaccurate gain ranging amplifiers. Circuit simplicity can also be achieved. Delta and delta-sigma modulators are particularly useful in connection with seismic signals because the signal-to-noise ratio of both modulators is directly proportional to the sampling frequency fs and inversely proportional to signal bandwidth fb. Accordingly, the very narrow, very low frequency seismic band of zero to 200 Hz is ideally suited for encoding according to this method.

Fig. 1 shows schematically conventional seismic exploration operations. Seismic energy is input to the earth at a source, typically a truck 1 raised upon a platen 2. Upon vibration of the truck 1, seismic energy is transmitted into the earth along a line 3. It is reflected from a rock layer 4 and detected by geophones 5.

Their output signals are amplified by amplifiers 6 and recorded by recording equipment 7, carried within a second truck 8.

Fig. 2 shows in block diagram form a typical single integration delta modulator circuit. The delta modulator encodes the difference e(t) between the input signal f(t) and the estimated signal output g(tn) by an integrator 16 during a sample period t. The estimate of f(t) is thus g(tn) and is varied each clock period by a +o step change, output by a one-bit digital to analog converter 14; that is, +o is the "height" of the "step" between adjoining predicted sample values. a is thus accordingly added or subtracted to the last predicted value in accordance with the sign of the error signal.Thus in accordance with the sign of e(t) output by comparator 10, +1 is sent by a quantizer 12 to the digitalto-analog converter 16 which outputs + to an analog integrator 16 which then feeds this next predicted value g(tn) back to the comparator 10. The stream of +1's can be integrated at 18 and digitally low pass filtered to generate digital words of any desired precision; that is, to say, the stream of +1's is added up overtime in a digital integrator 18, the output of which is low pass filtered at 20 to eliminate the "steps" from the output. Digital words are sampled therefrom at desired intervals to generate, for example, a 12-bit digital value for the analog signal at any given point in time. the following two equations thus describe the operations of this circuit f(t)-g(t) d e(t)= -[f(t)J as At~0 At dt g(tn)=g(tN~1)+cs where 1a!=o'At where f(t)=input seismic signal g(tN)=estimate of f(t) sample frequency time of Nth clock pulse e(t)=error signal to be encoded +a'=D/A output step change fo'=o'at=the integrated step change in the estimate of g(tN) Without going into detail, it will be understood by those skilled in the art that there are two sources of noise in the delta modulator scheme shown. When the encoder estimate g(tN) is not able to track the input signal f(t), "overload noise" occurs, i.e. when the rate of change in the input signal f(t) is greater than the rate of change in the estimate g(tn). Second, because the estimate g(tn) is constructed from a series of Ia discrete integrator steps there exists quantization noise proportional to the o step size. If the estimation step size Ia is too small, the estimation may not be able to track the input signal as it slews at high rate, producing overload error. If the step size o is too large, the estimator will produce a large quantization noise error.Hence, there is an optimal step size a which can be calculated as follows: Given f(t) as a sinusoid characterized by Asin(ot) d Maxima change: - [Asin(wt)] dt Acocos(cat) =A This is maximized &commat; wt=0 To avoid overload::

d a dt At a A(ss~ At oi~AsssAt f, #&alpha;#2n - f1/fg f5 where a=a'At=estimator step change #t= 1/fs A=amplitude of input signal f(t) signal input frequency sample frequency Since the modulator can be designed to avoid overload, the predominant noise in the encoder is therefore quantization noise.

The theoretical signal-to-noise ratio of the delta modulator can be calculated. Table I shows the results.

TABLE I N fj f, A a bits Hz Hz volts p volts MHz 15 100 200 5 5.8 .54 15 200 200 5 7.3 .86 16 100 200 5 3.6 .86 16 200 200 5 4.6 1.36 17 100 200 5 2.3 1.36 17 200 200 5 2.9 2.16 18 100 200 5 1.5 2.16 18 200 200 5 1.8 3.43 19 100 200 5 .9 3.43 19 200 200 5 1.2 5.43 20 100 200 5 .5 5.43 20 200 200 5 .7 8.60 In Table I, N indicates the equivalent number of bits, i.e. which would be provided by an ideal analog-to-digital converter of conventional type having a signal-to-noise ratio equal to that of the delta modulator defined by the other parameters given in Table I, fj is the input sample frequency, fb is the bandwidth, A is the maximum signal amplitude in volts, a is the step size in millivolts and fs is the sampling rate in MHz.Table I shows clearly that as sampling rates rise, it is possible to reduce a, thereby reducing the quantization noise and improving overall signal-to-noise ratio. High sampling rates are thus clearly desirable. Note in connection with Table I that the equivalent bit rate N rises as high as 20 for a sampling rate of 5.43 MHz. Cu rrently the best commercially available analog-to-digital converters are of 16 bit resolution and they carry with them the significant disadvantages of complexity, weight, high power requirement and cost.

To test the concepts described above, it was essential to build a prototypical model. Fig. 3 shows a breadboard version of this circuit and a detailed embodiment of the circuit will be discussed below in connection with Fig. 5. Test signals St (t) and S2(t) are sinusoids ranging from 5 Hz to 200 Hz, band limited to 200 Hz. The amplitude of S,(t) ranges from 1 millivolt RMS to 3.5 volts RMS and S2(t) ranges from 1 microvolt RMS to 256 millivolts RMS. In the test arrangement used (discussed below in connection with Fig.

4), a Hewlett-Packard Model 3325A signal synthesizer having guaranteed harmonic distortion of less than -80 dB was used to provide signal source S (t) while a Gus Company Model Attest oscillator with harmonic distortion guaranteed to less than -90 dB represents signal source S2(t). At a 6 mHz encoding rate, encoder harmonic distortion was not measurable in the presence of these signal source harmonics. As anticipated, the test results showed that higher sampling rate allowed smaller step sizes a without overload distortion and accordingly lowered quantization noise and yielded improved a signal-to-noise ratio overall.

The circuit of Fig. 3 basically carries out the function shown in the block diagram of Fig. 2. An input signal f(t) is supplied to a comparator 24, the polarity of the output of which controls a one bit analog-to-digital converter 26 which outputs digital non-return-to-zero (NRZ) data, i.e., a string of ones and zeroes. A step voltage reference 28 supplies a to a step generator 30 which adds either it to the contents of integrator 32, which supplies the predicted value g(tn) to the comparator 26. A clock circuit 34 conventionally controls synchronization of the circuit as shown.

The test procedure and results are as follows: The performance measurements were made by feeding the reconstructed analog signal (estimate) g(tn) into a Wavetek/Rockland 5830A spectrum analyzer. The analyzer computed an amplitude spectrum over the entire band fb. The coherent signals and harmonics were measured in decibels relative to one volt (r.m.s.) dBV. The noise floor due to quantization and random noise was measured in dBV/4, known as noise spectral density. This value represents the amount of noise power within a 1 Hz window. As an example of delta modulator performance, the SNR calculation was based upon measured values of a maximum output signal to r.m.s. noise floor over the seismic band fb.

Harmonic distortion was ignored since this is primarily due to the signal sources Si (t) and S2(t).

The maximum input signal was 3.53 V rms or 11 dBV. The noise spectral densities at 2,4, and 6 MHz sampling rate were - 100.6 dBWVWz, - 117.0 dBWVWz, and 120.1 dBV/ respectively over a 1000 Hz band. Measurements were taken over a 1000 Hz band so that harmonic and intermodulation products could be observed. These noise spectral densities can then be translated to a 200 Hz seismic band.

At a 2 MHz sampling rate, the noise spectral density of -100.6 dBV/Hz measured over a 1000 Hz band was converted to the appropriate value of power for a 200 Hz seismic band by the following calculation.

-100.6 dBV 9.33 V 87.09x10-t2 watts + Hz Total Noise Power=87.09x 1 0-12x 200=1 .74x 10-8 watts 200 Hz Delta Modulator signal-to-noise ratio (SNR) (dB) for a 2 MHz sampling rate:

(3.53) SNR (dB)=10 log =88.6dB L1/4 x10-3 Comparing with a conventional analog to digital converter 6.02 N+1.8=88.6 db N=14.4 equivalent bits At a 4 MHz sampling rate the noise spectral density of -117.0 dBV/Hz was converted to its appropriate value of power for a 200 Hz seismic band.

-117.0 dBV 1,413 uV 2x10-t2 watts i Vwz Hz Total Noise Power=2 x10-12x200=4x 10-13 watts 200 Hz Hz Delta Modulator SNR (dB) for a 4MHz sampling note:

(3.53)2 SNR (dB)=10 log ------ =105dB (4x1 10-1 ) Comparing with a conventional A/D converter: 6.02 N+1.8=105 N=17.1 equivalent bits At a 6 MHz sampling rate the noise spectral density of -120.1 dBIHz was converted to its appropriate value of power for a 200 Hz seismic band.

-120.1 dB .988 pV .977x10-12 ç Hz Total Noise Power=1.95x10-10 watts.

Delta Modulator SNR (dB) for a 6MHz sampling rate:

(3.53)2 SNR (dB)=10 log ------ =108dB 1.95x10-10 Comparing with a conventional A/D converter: 6.02 N+1.8=108 N=17.6 equivalent bits These results are summarized in Table II.

TABLE II f, NT SNR N MHz watts dB bits 2 1.74x10-8 88.6 14.4 4 4x10-'0 105 17.1 6 1.95x10-10 108 17.6 fs is the sample frequency in MHz, Nut is the total noise power over a 200 Hz seismic band, SNR (dB) is the ratio of the maximum R.M.S. output signal to R.M.S. Noise Floor, computed with respect to a maximum input of 10 v peak-to-peak, and N is the equivalent number of bits for a conventional AID converter having the same signal-to-noise ratio.

Fig. 4 shows the delta modulator test set-up which was employed. As discussed above, two input test signals, St (t) and S2(t) were used. These were sinusoidal inputs with a maximum frequency of 200 Hz and amplitude limited to +5 volts. Since one of the major problems of existing analog-to-digital converters using gain ranging amplifiers is that small signals cannot be detected in the presence of large signals, a two tone test was conducted to measure the instantaneous dynamic range, or in other words the dynamic resolution. Since the spectrum analyzer can only calculate spectra within an 80 dB range, attempting to directly observe a 120 dB difference between Si (t) and S2(t) would be impossible.Therefore, the analog estimate g(tn) was passed through a -70 dB dual twin tee notch filter 38, tuned to the frequency of the larger signal St(t) then analyzed by the spectrum analyzer 40. This exercise allowed determination of whether the small signal S2(t) could be reconstructed in the presence of the larger signal St(t). The experimental results showed that a 15 Hz signal at 11 dBV (3.5 V r.m.s.) added to a 95 Hz signal at -102dB (811V r.m.s.), encoded by the modulator at a 6 MHz rate, would yield an analog estimate g(tn). The notch filter 38 was used to reject the 15 he component of g(t,) by approximately -70 dB with the result that the small signal S2(t) could be seen. This result revealed that both signals were instantaneously encoded within a dynamic range of 110 dB. However, the signal source harmonics of S,(t) were also present so that was not possible to accurately measure any additional harmonic noise due to the modulator alone.

It will be appreciated by those skilled in the art that circuit performance measured as above amounts to evaluation of the analog estimate signal g(tn). Evaluating the filtered and subsampled digital data as output by the decoder of Fig. 1 will allow additional mathematical operations to be performed, i.e., mathematically filtering out undesirable frequencies such as 60 Hz, 120 Hz, 180 Hz, widening the spectrum, analyzing dynamic range, stacking, correlation, filtering, and many other conventional signal processing techniques.

Any and all of these might yield further improvements and these would also be available to signal processors working with actual seismic signals.

Fig. 5 shows a detailed circuit diagram embodying the breadboard of Fig. 3. Input signal f(t) is supplied to first and second op amps 50 and 52 which together provide the addition function of comparator 10 of Fig.

1. The predicted signal g(t) is also supplied to op amp 50. The output signal of comparator op amp 52 is supplied by way of two AND gates 54 and 56 and an inverter 58, to the gates of two FETs 60 and 62. The step a is supplied to FETs 60 and 62 from an op amp 64. The size of the step a is controlled by a potentiometer 66.

This changes the input voltage to the op amp 64. Depending on which of the FETs 60 or 62 is turned on by the AND gates 56 and 54 in accordance with the 11 output from comparator 52, a is supplied, after having been passed through buffers 68 and 70, to the inverting or non-inverting input terminal of another op amp 72. As shown the AND gates 54 and 56 are supplied with a delayed clock signal to provide accurately-timed, deglitched outputs which control the gates of the transistors 60 and 62. Depending on whether the positive or negative terminal had applied thereto via FET 60 or 62, the lavalue is supplied by op amp 72 to the integrator stage shown generally at 16, which then outputs g(t) again. A potentiometer 73 is used to balance the offset adjustment of op amp 72.The integrator 16 comprises a capacitor 78 and an op amp 76. The output of the AND gate 54 is a digital NRZ output; that is, a stream of ones and zeroes which can then be integrated, low pass filtered and subsampled to generate digital words indicative of instantaneous analog signal amplitude. The predicted value g(t) can also be used as an analog output, e.g., for test purposes or the like if desired; otherwise, it is simply fed back into op amp 50 for comparison to the next input signal f(t).

It will be appreciated by those skilled in the art that the circuit of Fig. 5 uses a single source for both the a steps regardless of whether a is to be added or subtracted from the contents of the integrator 16. The step size value is essentially passed through only low noise logic components and therefore it can be expected that the output of the integrator 16 will remain substantially consistant over time, so long as the analog input signal itself does not depart greatly from its initial average value. In this way, difficulties according to component tolerance and variance overtime and the like are substantially minimized.

Fig. 6 shows a block diagram of the delta-sigma modulator. The delta-sigma modulator encodes an error signal e(t) which is derived from the difference between the integral of the input signal, ff(t), and the integral of the estimate, fg(tn). By comparison, the delta modulator encodes an error signal e(t) which is derived from the difference between an input signal f(t) and its estimate g(tn). The error signal e(t) is thus expressed by:

gftw)=Jg(t1)IaN-1 Again, the basic loop comprises a comparator 10 and a one bit analog-to-digital converter 12, as in the case of the delta modulator. However, rf(t) is input to the comparator 10, from an additional integrator 24.

Then, a one-bit digital-to-analog converter 14 and integrator 16 are used, once again as in the case of the delta modulator, although the integrator's output now is rg(tn). As #t- > 0, that is, as the sample rate increases, the modulator encodes the signal itself instead of the slope of the signal, as did the delta modulator. This means that the delta-sigma modulator is much more immune to transients and high frequency noise affect the delta modulator's performance. However, since the delta-sigma modulator is amplitude sensitive, appropriate frontend amplitude limiting circuitry is necessary.

Delta-sigma modulators are confronted with both overload and quantization noise but the former can be minimized, and an optimum step size a can be chosen. The minimum integrator step size a such that overload does not occur can be demonstrated as follows: Given f(t) as a sunisoid characterized by A sin (t)

IA A f(t) cos (wt)= -cos (o)t) Co Co dA Maximal Change:d A-cos(wt) dt w Asln(wt)=A maximized & ommat; wt=90 To avoid overload: a At #t a#A#t A 0#A fs where a=a'At=estimator step change sample frequency A=amplitude of input signal f(t) At=1/f5 Table III is a table comparable to Table I showing theoretical design parameters for a delta-sigma modulator.In this case, however, the input signal frequency f(t) is no longer a factor in this calculation, TABLE Ill N f A a bits Hz volts p volts MHZ 15 200 5 5.6 0.88 16 200 5 3.6 1.4 17 200 5 2.3 2.2 18 200 5 1.4 3.5 19 200 5 0.9 5.6 20 200 5 0.56 8.8 Again, N represents the equivalent number of bits of a conventional analog-to-digital converter, fb is the bandwidth, A is the maximum signal amplitude in volts, o is the step size in microvolts, and fs is the sampling frequency. Again, the number of equivalent theoretical bits N available rises with the sampling frequency fs.

The results obtained with the delta-sigma modulator in general are very comparable with those achieved with the delta modulator, and hence their performance is largely equivalent. The choice between the two is therefore to be made on other considerations. One of these may be that the decoder used for the delta-sigma modulator is simply a low pass filter. Also, the encoder can be reconfigured into a compact form as shown in Fig. 7. This is comparable to Fig. 6, but uses the fact that e(t)='f(t)-fgft) which while is equivalent to S[f(t)-Sg(t,)l. Therefore, the two integrators 16 and 24 of Fig. 6 can be replaced by one integrator 26 as shown in Fig. 7.

A delta-sigma modulator circuit was built and tested; its circuit corresponded to the breadboard circuit diagram of Fig. 8. Circuit details are shown in Fig. 10. The configuration chosen was that of Fig. 6, rather than the compact form of Fig. 7 because this enabled many of the same components used in the prototypical delta modulator shown in Figs. 2 and 5 to be reused in the delta-sigma modulator circuit.

Again, input signals S, and S2(t) are summed at 60 to form input signal f(t) and integrated at 62. The integrated signal ff(t) is then supplied to the comparator 24, which feeds one-bit analog-to-digital converter 26. Its +1 output control step generator 30 and integrator 32 as in the circuit of Fig. 2. The same step voltage reference source 28 is also used.

The test set-up is shown in Fig. 9 and is also generally similar. Again, the spectrum analyzer 40 and the notch filter 38 are used to provide the appropriate filtering on the output side. Here, however, differentiator 64 must be added to correspond to the initial integrator on the input side of the delta-sigma modulator, i.e.

to provide an estimate of f(t). Test results were generally as follows: The dynamic range of 110 do was consistent with the performance of the single integration delta modulator, as expected. An increasing noise floor tilt ascended gradually over the 200 Hz bandwidth. A two-tone test was conducted whereby a 3.5 volt (r.m.s.) sinusoid at 15 Hz [S,(t)] was applied to the encoder in conjunction with a 16 volt (r.m.s.) sinusoid at 95 Hz [S2(t)j. Si (t) was notched -70 dBV at the output by filter 38 and processed by the spectrum analyzer 40. The results showed accurate reproduction of S2(t) in the presence of S,(t).The encoder did not contribute a noticeable amount of harmonic distortion to the harmonic distortion of the S,(t) signal source, although the test equipment employed did not permit measurement of encoder harmonic contribution in the presence of the large signal source harmonics to as high a degree of confidence as might be desired. For example, if the signal source contributed -80 dBV (100 pV) of harmonic distortion and the modulator contributed an equal amount of harmonic distortion, then the combined total was -74 dBV (-80 dBV+6 dBV). If the modulator contributed 10% (10 pV) of the signal source distortion, the total was -79.2 dBV. Finally, if the modulator contributed 1% (1 pV) of the signal source distortion, the total was then -79.9 dBV.The measured output of the modulator using the signal sources as described above showed that the encoder distortion was small and could not be discriminated from the signal source harmonic distortion. Also, the mathematical value of the encoder distortion was shadowed by the signal source distortion as shown in the example above.

Calculation of the delta sigma modulator SNR performance was based on measured values of a maximum output signal (r.m.s.) to noise floor spectral density over the seismic band fb. The maximum input signal was 3.53 V r.m.s. or 11 dBV. Since a "noise tilt" as previously discussed existed, the best and worst case values of the noise are used in the following performance evaluation. Table IV presents the delta sigma modulator test results in a similar manner as was presented in Table II for the delta modulator results.

TABLE IV NT SNR N watts db bits fs MHz Min Max Min Max Min Max 2 2x10-8 63x10-8 73 88 11.8 14.3 4 1 .27 xl 0-'0 5x10-8 84 110 13.6 18 6 6.3x10-" 2x10-8 88 113 14.3 18.4 fs is the sample frequency in MHz, Nazis the total noise power over a 200 Hz seismic band, SNR (dB) is the ratio of the maximum r.m.s. output signal to r.m.s. noise floor, and N is the equivalent number of bits for a conventional AID converter. The sNR was computed with respect to a maximum input of 10 V peak-to-peak.

Fig. 10 shows the circuit which was tested giving the results given above In connection with delta-sigma modulation. Most of the components in this drawing are the same as those shown in Fig. 5. The comparator arrangement 10 is similar, as is the use of the inverter 58 and two AND gates 54 and 56 in conjunction with the FETs 60 and 62 and in combination with the buffers 68 and 70 to supply either cos to the one bit AID converter 14 (i.e. op amp 72) which then supplies this output to the integrator 16, again comprising op-amp 76 and capacitor 78. The step size +s is controlled by op-amp 64 and potentiometer 66 as before. Added to that circuit is a front end integrator 62, comprising another comparator.Another comparator is used as a summing amplifier 60 containing input signal f(t), while comparator 24 provides the actual comparison between the estimated signal fg(t) and the integrated input signal f(t). As discussed above in connection with the compressed delta-sigma modulator of Fig. 7, in use, comparators 62 and 76, that is, the front end integrator and the integrator providing the rg(t) predicted signal could be combined as one. Again, AND gates 54 and 56 are clocked by the time delayed input sampling clock signal, and the output of gate 54 is the digital output. As mentioned above, this need simply be low-pass filtered and sampled to provide a digital output signal. The use of paired FETs 60, 62 for selectively transmitting the Ia value from the identical step generator 64 provides the same advantage here as in connection with the circuit of Fig. 5; that is, stability over time, no net dc build-up and simplicity of construction.

Claims (12)

1. An analog-to-digital converter for conversion of analog input signals into digital representations thereof comprising: means for generating a predicted analog signal value; a comparator for comparing the predicted analog signal value to a sampled analog input signal value; and a one-bit analog-to-digital converter for outputting a digital bit in response to the sign of the difference between the predicted input value and the actual input value; characterized in that the means for generating the predicted analog signal value comprises: means for supplying a predetermined step value; an integrator responsive to the one bit analog-to-digital converter for adding or subtracting the predetermined step value to the predicted analog signal; and means for supplying the contents of the integrator to the comparator for comparison with the next input sample.

2. An analog-to-digital converter according to claim 1, further comprising means for varying the predetermined step value for optimizing operation of the circuit.

3. An analog-to-digital converter according to claim 1 or claim 2, wherein the predetermined step value is supplied to a pair of transistors the outputs of which are supplied to inverting op amps for supplying the predetermined step value to the integrator and wherein the transistors are controlled by the one-bit analog-to-digital convertor responsive to the sign of the difference between the comparator for the predicted input value and the actual input value.

4. An analog-to-digital converter according to claim 3, wherein the transistors are field effect transistors.

5. An analog-to-digital converter according to claim 3, wherein the transistors are controlled by AND gates having as input clock signals and the sign of the output from the comparator, the output of the comparator being inverted before it is applied to one of the AND gates.

6. An analog-to-digital converter according to any one of claims 1 to 5, comprising means for integrating the actual analog input signal prior to presentation thereof to the comparator, whereby the integral of the predicted analog signal is compared by the comparator to the integral of the predicted signal.

7. A method for converting an analog input signal into a digital signal comprising the steps of: comparing the analog input signal to a predicted analog signal; outputting a sequence of digital bit in response to the sign of the results of the comparisons; integrating a sequence of predetermined step values, the signs of which are dependent on the digital bits; and supplying the result of the integrating step for use as the predicted analog signal in the comparing step.

8. A method according to claim 7, wherein the steps of integrating predetermined step values and supplying the result as the predicted analog signal comprise the steps of supplying the predetermined step value to a pair of switches and controlling one of the switches to pass the predetermined step value to means for controllably inverting the polarity of the predetermined step value prior to the integrating step, the controllable inverting being performed in accordance with the sign of the result of the comparing step.

9. A method according to claim 8, wherein the switches are transistors.

10. A method according to claim 9, wherein the transistors supply the step value to positive and negative terminals of an inverting operational amplifier, and further comprising the step of controlling only one of the transistors to be turned on, responsive to the sign of the result of the comparison step.

11. A method according to claim 10, wherein the one transistor is turned on by supplying the sign of the result of the comparison step to an inverter connected to an input of one of two AND gates and directly to an input of the other of the AND gates, the outputs of the AND gates controlling the transistors, a clock signal being supplied to the other input of both AND gates, whereby only one of the AND gates is controlled to turn on the corresponding transistor in response to any given comparison step.

12. A method according to any one of ciaims 7 to 11, comprising the additional step of integrating the input signal whereby the integrated actual input signal is compared to the integrated predicted input signal in the comparing step.