GB2150391A

GB2150391A - Sync signal generator

Info

Publication number: GB2150391A
Application number: GB08426270A
Authority: GB
Inventors: Ikuo Kurihara; Rikitaro Mita; Tetsuya Tateno
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 1983-10-21
Filing date: 1984-10-17
Publication date: 1985-06-26
Also published as: GB2150391B; GB8426270D0; JPS6089173A; DE3438459A1

Abstract

A monolithic semiconductor device for generating sync signals in a video signal processing circuit. The device includes an ROM in which data to determine the parameters for the sync signals is stored. The timing of the sync signal can be changed by merely changing the contents of the ROM. <IMAGE>

Description

SPECIFICATION Semiconductor apparatus for generating sync signals BACKGROUND OF THE INVENTION Field of the invention The present invention relates to a semiconductor apparatus for generating sync signals which are used in a signal processing circuit and, more particularly, to a monolithic semiconductor apparatus.

Description of the prior art Generally, sync signals are needed to process a video signal and there are a horizontal sync signal, a vertical sync signal and a composite sync signal as these sync signals. Namely, the horizontal sync signal is the signal synchronized with the horizontal scanning, the vertical sync signal is the signal synchronized with the vertical scanning, and the composite sync signal is the signal of which a few kinds of horizontal sync signals are overlapped into the vertical sync signal.

Conventionally, in many cases, when the abovementioned sync signals are generated, they are generated by a semiconductor apparatus including a sequential logic circuit consisting of a combination of a flip flop and a gate. Since a relatively high speed operation is required in this sequential logic circuit, its structure is complicated; furthermore, a complicated design for a mask is also needed to constitute such a semiconductor apparatus.

On the other hand, from the requirements of the signal processing circuit, as the sync signals, there is a case where a few kinds of sync signals having different pulse widths and phases and the like (hereinbelow, these are referred to as timings) as the parameters for the sync signals are necessary.

Also, there are NTSC system, PAL system and the like as standards on the video signal and peculiar frequencies are individually determined; therefore, to satisfy all of them by a single semiconductor apparatus, it is necessary to change the frequencies of the sync signals which are generated from the semiconductor apparatus.

However, in a conventional semiconductor apparatus, it is necessary to redesign a circuit to change the timing for the sync signals. However, as mentioned above, if a circuit is redesigned, it will take a considerable expense and time since the arrangements of the sequential logic circuit and semiconductor apparatus are complicated.

Summary of the invention It is an object of the present invention to realize a semiconductor apparatus for generating sync signals which can easily change timings for the sync signals in order to solve the above-mentioned drawbacks.

Another object of the invention is to provide a semiconductor apparatus for generating sync signals having an ROM in which data to determine the parameters for the sync signals is stored.

Brief description of the drawings Figure 1 is a block diagram showing an arrangement of a semiconductor apparatus for generating sync signal according to a first embodiment of the present invention; Figure 2 is an explanatory diagram showing data in ROM; Figure 3 shows time charts of outputs of the ROM; and Figure 4 is a block diagram showing an arrangement of a semiconductor apparatus for generating sync signals according to a second embodiment of the invention.

Detailed description of the preferred embodiments To accomplish the foregoing objects, the present invention has a feature such that it includes an ROM having data for generation of timing signals and can cope with a change of the timings by rewriting the content of the ROM.

The invention will now be practically described in detail hereinbelow with respect to the drawings.

Fig. 1 is a block diagram showing a schematic arrangement of a first embodiment of the invention.

In the diagram, a reference numeral 2 denotes a clock generator using a crystal or the like; 4 is a counter for counting a horizontal period; 6 a counter for counting a vertical period; and 8 an ROM using an output of the horizontal counter 4 as an address. The ROM 8 has the addresses of Q to 129. As shown in Fig. 2, the content of each address is written by "0" or "1" in each address. In this case, as shown in the diagram, since three kinds of data of A, B and C are written, the number of output bits from the ROM 8 is three. This number of output bits is increased and decreased in dependence upon a request by a video signal processing system. Fig. 3 shows time charts of the outputs A, B and C from the ROM 8 and they correspond to the data in the ROM 8 of Fig. 2. A numeral 10 indicates an ROM using an output of the vertical counter 6 as an address.The ROM 10 has addresses of 0 to 524 and has a similar structure as that of the ROM 8. The number of output bits from the ROM 10 is set to a necessary number. A logic circuit 12 inputs the outputs from the ROMs 8 and 10 and generates three kinds of signals, that is, a vertical sync signal 14, a horizontal sync signal 16 and a composite sync signal 18.

The operation will then be described.

A primary sync signal of the frequency of 130 fH (where, fH is a horizontal synchronizing frequency) is generated from the clock generator 2. This primary sync signal is frequency-divided into ill 30 by the horizontal counter 4 and the output of the horizontal counter 4 becomes an address input to the ROM 8. Namely, the contents of the addresses from 0 to 129 of the ROM 8 are sequentially read out in response to the output signals of the horizontal counter 4 and they become a horizontal sync signal. As this horizontal sync signal, a few kinds (three kinds of A, B and C in this invention) of such signals are generated in dependence upon a method of writing data in the ROM 8 and are in putted to the logic circuit 12.A signal of the period of 2 fH having two pulses is included in the horizontal sync signal and this 2fH-period signal is inputted to the vertical counter 6. The inputted 2fH- period signal is frequency-divided into 1/525 by the vertical counter 6, so that the signal which was frequency-divided into 1/525 is address inputted to the ROM 10. That is, the contents of the addresses of 0 to 524 of the ROM 10 are sequentially read out in response to the signal which was frequency-divided into 1/525 and they become a vertical sync signal. This vertical sync signal is inputted to the logic circuit 12.The outputs of the ROMs 8 and 10 are inputted to the logic circuit 12, where AND and OR of both outputs or the ROMs 8 and 10 are got and a composite sync signal is generated, so that the vertical sync signal 14, horizontal sync signal 16 and composite sync signal 18 are outputted from the logic circuit 12. In the first embodiment, the contents of the ROMs 8 and 10 may be merely changed to change the timings form the sync signals, and a part of mask pattern may be ordinarily modified to change the content of the ROM.

Fig. 4 shows a second embodiment of the invention, in which a numeral 2 denotes the clock generator; 20 is a horizontal/vertical (HN) counter for performing the frequency-dividing at one-frame period; and 22 is an ROM using an output of the H/ V counter 20 as an address.

This second embodiment functions in the manner as follows. Namely, a primary sync signal is generated from the clock generator 2 and this primary sync signal is inputted to the HN counter 20.

The H/V counter 20 frequency-divides the primary sync signal at one-frame period and the signal which was frequency-divided at this one-frame period is address-inputted to the ROM 22. Thus, the content of the ROM 22 is read out and the vertical sync signal 14, horizontal sync signal 16 and composite sync signal 18 are outputted from the ROM 22.

Even in this second embodiment, the timings for the sync signals can be changed by merely rewriting the content of the ROM 22.

As described in detail in the above, according to the present invention, even in the case where a few kinds of sync signals are needed, it is possible to cope with it by merely rewriting the data in the ROM without requiring a change in design of a circuit in the semiconductor apparatus. Therefore, the invention has a remarkable effect such that the cost and time can be extremely reduced.

Claims

CLAIMS:

1. A semiconductor apparatus for generating sync signals having an ROM in which data to determine parameters for sync signals is stored.

2. Semiconductor apparatus for generating sync signals comprising a ROM containing at a plurality of successive locations data determining the parameters of sync signals to be generated; a clock arranged to cause said locations to be addressed in succession, and a logic circuit arranged to receive data output by said ROM in response to said addressing and to produce sync signals therefrom.

3. Apparatus according to clairri 2, operable to produce horizontal and vertical synchronising pulses.

4. Apparatus according to claim 3, including first and second said ROM's, the first ROM being operable to produce the horizontal synchronising pulses and the second ROM being arranged to receive an output from the first ROM and in response thereto to produce vertical synchronising pulses.

5. Semiconductor apparatus for generating sync signals, substantiaily as herein described with reference to Figs. 1 to 3 of the accompanying drawings.

6. Semiconductor apparatus for generating sync signals, substantially as herein described with reference to Fig. 4 of the accompanying drawings.