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GB2149965A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
GB2149965A
GB2149965A GB08500267A GB8500267A GB2149965A GB 2149965 A GB2149965 A GB 2149965A GB 08500267 A GB08500267 A GB 08500267A GB 8500267 A GB8500267 A GB 8500267A GB 2149965 A GB2149965 A GB 2149965A
Authority
GB
United Kingdom
Prior art keywords
arsenic
oxide layer
layer
diffusion
generation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB08500267A
Other versions
GB8500267D0 (en
GB2149965B (en
Inventor
Hisao Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of GB8500267D0 publication Critical patent/GB8500267D0/en
Publication of GB2149965A publication Critical patent/GB2149965A/en
Application granted granted Critical
Publication of GB2149965B publication Critical patent/GB2149965B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

Landscapes

  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor device is designed to solve the problem of the instability of the surface state of a semiconductor substrate below an oxide layer, based on the generation of a positive charge. According to the invention, an arsenic diffusion-blocking layer (11) is formed between an oxide layer (1) which is formed over one main surface of a semiconductor substrate and an arsenic-containing layer (2) which is formed over the oxide layer (1), and into which hydrogen is diffused in order to block the diffusion of the arsenic contained in the arsenic-containing layer (2) into the oxide layer (1) when annealing is effected, thereby preventing the generation of a positive charge. The invention is applicable to, for example, the field-insulating layer of a complementary MOS integrated circuit or the silicon gate portion of a MOS transistor.
GB08500267A 1983-05-16 1984-05-16 Semiconductor device Expired GB2149965B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58085519A JPH0630355B2 (en) 1983-05-16 1983-05-16 Semiconductor device

Publications (3)

Publication Number Publication Date
GB8500267D0 GB8500267D0 (en) 1985-02-13
GB2149965A true GB2149965A (en) 1985-06-19
GB2149965B GB2149965B (en) 1986-12-31

Family

ID=13861153

Family Applications (1)

Application Number Title Priority Date Filing Date
GB08500267A Expired GB2149965B (en) 1983-05-16 1984-05-16 Semiconductor device

Country Status (5)

Country Link
JP (1) JPH0630355B2 (en)
KR (1) KR840009182A (en)
DE (1) DE3490241T1 (en)
GB (1) GB2149965B (en)
WO (1) WO1984004628A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8401250D0 (en) * 1984-01-18 1984-02-22 British Telecomm Semiconductor fabrication
JPH0691075B2 (en) * 1985-06-17 1994-11-14 新日本無線株式会社 Semiconductor device
EP0495991A4 (en) * 1990-08-07 1992-10-28 Seiko Epson Corporation Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3660735A (en) * 1969-09-10 1972-05-02 Sprague Electric Co Complementary metal insulator silicon transistor pairs
US3700507A (en) * 1969-10-21 1972-10-24 Rca Corp Method of making complementary insulated gate field effect transistors
JPS4964382A (en) * 1972-06-30 1974-06-21

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2102918A1 (en) * 1970-01-26 1971-08-05 Itt Ind Gmbh Deutsche Method for producing field insulation for semiconductor components
JPS4979782A (en) * 1972-12-08 1974-08-01
JPS582866A (en) * 1981-06-29 1983-01-08 Ricoh Co Ltd Discharging method for recording body

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3660735A (en) * 1969-09-10 1972-05-02 Sprague Electric Co Complementary metal insulator silicon transistor pairs
US3700507A (en) * 1969-10-21 1972-10-24 Rca Corp Method of making complementary insulated gate field effect transistors
JPS4964382A (en) * 1972-06-30 1974-06-21

Also Published As

Publication number Publication date
WO1984004628A1 (en) 1984-11-22
DE3490241T1 (en) 1985-05-15
KR840009182A (en) 1984-12-24
GB8500267D0 (en) 1985-02-13
JPH0630355B2 (en) 1994-04-20
GB2149965B (en) 1986-12-31
JPS59211235A (en) 1984-11-30

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Legal Events

Date Code Title Description
PE20 Patent expired after termination of 20 years

Effective date: 20040515