GB2148620A

GB2148620A - Voltage multiplying rectifier

Info

Publication number: GB2148620A
Application number: GB08423424A
Authority: GB
Inventors: Yoshio Takamura; Akira Nakajima
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 1983-09-30
Filing date: 1984-09-17
Publication date: 1985-05-30
Also published as: DE3435444A1; JPS6077678A; GB8423424D0

Abstract

The rectifier includes a plurality of AC power sources (V1,V2) generating AC signals eg. square waves, an even number of rectifying elements (D1-D8) to rectify the AC signals, a plurality of output capacitors (C3,C4,C5,C6) connected in series across the rectifying elements, and a plurality of capacitors (C1,C2,C7,C8) connected between the nodes of the rectifying elements and the terminals (a,b) of the AC power sources. <IMAGE>

Description

SPECIFICATION Voltage multiplying rectifier The present invention relates to a voltage multiplying rectifier which generates an output which is a multiple of the input voltage by using a plurality of AC power sources, diodes and capacitors.

As is well known in the art, a conventional voltage-multiplying rectifier is constructed of a combination of transformers, capacitors and diodes. However, transformers present disadvantages when used in voltage-multiplying rectifiers, because they are heavy and they are difficult to construct using IC (Integrated Circuit) techniques. In recent years, it has become desirable to have a voltage-multiplying rectifier which is constructed by IC techniques alone, but this need has not been satisfied by the attempt to apply these techniques to a conventional rectifier using a transformer.

An object of this invention is to provide a voltage-multiplying rectifier which is suitable for manufacture by integrated circuit techniques.

According to the present invention, a voltage-multiplying rectifier comprises first and second AC power sources, each having a first output terminal connected to each other and to ground, and having a second output terminal; a plurality of rectifying elements connected in series and aligned in the same direction of rectification, and having one terminal connected to said first output terminals of said first and second AC power sources, and another terminal which provides an output terminal for the rectifier, and nodes formed between the rectifying elements; a plurality of output capacitors connected in series with each other between said first output terminals and said rectifier output terminal, and parallel to said rectifying elements so that each of said output capacitors is connected to selected nodes; and a plurality of second capacitors connected to one of said second output terminals of said first and second AC power sources and to nodes to which said output capacitors are not connected.

In order that the invention may be more readily understood, it will now be described, by way of example only, with reference to the accompanying drawings, in which: Figure I is a circuit diagram of one embodiment of a voltage-multiplying rectifier constructed according to the present invention; and Figure 2 is a circuit diagram of another embodiment constructed according to the present invention.

In Fig. 1, AC power sources V, and V2 are each exemplified by AC inverters which generate square waves of preferably identical output voltage and frequency. The power sources V, and V2 are connected in series. First output terminals of each source are connected to each other and to ground. The resultant node m between the AC power sources V, and V2 is thus grounded. An even number of rectifying elements, here eight diodes D, to Dss, are connected in series between the node m and an output terminal 0 with their rectification directions aligned. Specifically, the anode of diode D1 is connected to node m, and the cathode of diode D8 is connected to the output terminal 0.Capacitors C, and C2 are connected in series between the other output terminal a of the AC power source V, and a node i between diodes D7 and D8. The node between the capacitors C, and C2 is connected to a node e between the diodes D3 and D4.

Output capacitors C3 to C6 are connected in series with each other between node m and the output terminal or node 0. Of these, output capacitor C3 is connected in parallel across diodes D, and D2 to nodes m and d; output capacitor C4 is connected in parallel across diodes D3 and D4 to nodes d and f; and, similarly, output capacitors C5 and C5 are connected in parallel across diodes D5 and D6 to nodes f and h and across diodes D7 and D8 to nodes h and 0, respectively. Capacitors C7 and C8, which have a common node connected to a node c between diodes D, and D2, are connected in series between another output terminal b of the AC power source V2 and a node g between diodes D5 and D6.In the construction described above, nodes c, e, g and i, to which no output capacitors are connected, are alternately connected through capacitors to the AC signal sources V2 and VX, respectively.

The operation of the circuit of Fig. 1 is as follows: First, the output terminal b of the AC power source V2 is at a voltage of - E (V) with respect to ground potential. In this case, diode D, is turned on so that capacitor C7 is charged to a voltage E (V), in the direction such that the node c becomes positive, by a current which flows through the AC power source V2, node m, diode D, node c, capacitor C7 and the output terminal b. Next, the output terminal b of the AC power source V2 is at at voltage of + E (V).In this case, the diode D2 is turned on so that capacitor C3 is charged to a voltage of 2E (V) which is the sum of the output voltage E (V) of the AC power source V2 and the charged voltage E (V) of capacitor C7, in the direction such that node d becomes positive, by a current which flows through the output terminal b, capacitor C7, node c, diode D2, node d, capacitor C3 and node m.

Next, the output terminal a of the AC power source V, is at a voltage of - E (V). In this case, diode D3 is turned on so that capacitor C, is charged to a voltage of 3E (V) which is the sum of the output voltage E (V) of the AC power source V, and the charged voltage 2E (V) of capacitor C3, in the direction such that node e becomes positive, by a current which flows through node m, capacitor C3, node d, diode D3, node e, capacitor C1, and the output terminal a. The output terminal a of the AC power source next has a voltage of + E (V).

In this case, diode D4 is turned on so that capacitor C4 is charged to a voltage of 2E (V), in the direction sucbh that node f becomes positive with respect to ground potential, by a current which flows through the output terminal a, capacitor C1, node e, diode D4, node f, capacitor C4, capacitor C3, and node m.

The subsequent steps of charging capacitors C8, C5, C2 and C6 are similar to what has just been described. The output terminal b changes from - E (V) to + E (V) and the output terminal a changes from - E (V) to + E (V) so that output capacitors C5 and C6 are charged 2E (V) in the direction such that nodes h and o become positive with respect to ground potential. As a result, node h and the output terminal 0 are raised to voltages of 6E (V) and 8E (V), respectively, with respect to ground potential.

The operation described above is based on the assumption that the AC voltage sources V, and V2 operate independently of each other.

From the circuit operation, however, it can be understood that output capacitors C3 to C5 are each charged within each cycle by the multiplied output voltages of one of the AC power sources V or V2. Since each output capacitor is charged by one of the AC power sources alone, these AC power sources V, and V2 need not necessarily be held in synchronism with each other, but can be set at suitable frequencies and at suitable phases, independently of each other. Furthermore, the AC voltage sources V, and V2 need not have the same output voltage.

Another embodiment of the present invention will now be described with reference to Fig. 2.

The embodiment of Fig. 2 is identical to that of Fig. 1, except that capacitors C, and C2 are connected in parallel to nodes e and and capacitors C7 and C5 are connected in parallel to nodes c and g from the respective output terminals of the first and second AC signal sources V, and V2. A further, detailed description of the circuit construction is omitted herein.

The operation of the circuit of Fig. 2 will now be described.

First, node b of the AC signal source V2 is at a voltage of - E (V). This turns diode D, on so that a current flows through a loop consisting of node m, diode D,, node c, capacitor C7 and node b to charge the capacitor C7 until node c is at a voltage of + E (V).

Next, when node b of AC power source V2 has a voltage of + E (V), diode D2 is turned on so that a current flows through a loop consisting of node b, capacitor C7, diode D2, capacitor C3, and node m to charge the capacitor C3 until node d is at a voltage of + 2E (V).

Subsequently, when node a of the AC power source Vl is at a voltage of - E (V), diode D3 is turned on so that a current flows through a loop consisting of node m, capacitor C3, diode D3, node e, and capacitor C, to charge capacitor Ct until node e is at a voltage of + 3E (V).

When node a of the AC power source V1 is at a voltage of + E (V), diode D4 is turned on so that a current flows through a loop consisting of node a, capacitor Cl, diode D4, capacitor C4, capacitor C3 and node m to charge capacitor C4 until node f is at a voltage of 2E (V).

Subsequently, the cycle of voltages at nodes b and a repeats, i.e. the voltage at node b changes from - E (V) to + E (V), and that at node a changes from - E (V) and + E (V). As a result, capacitors C6, C2 and C5 are charged in turn until nodes g, h and i and the output terminal 0 are at voltages of 5E (V), 2E (V), 7E (V) and 2E (V), respectively.

As a result, an output voltage of 8E (V) is obtained between node m and the output terminal 0.

With this construction, each of the capacitors C1 to C8 can operate without being adversely affected by any phase relationship between the AC signal sources V, and V2 because each of them is charged by only one of the first and second signal sources V, and V The descriptions of these embodiments are directed to the case in which there are two AC signal sources. However, the present invention can be similarly constructed even when three or more AC power souces are used.

Claims

1. A voltage-multiplying rectifier comprising first and second AC power sources, each having a first output terminal connected to each other and to ground, and having a second output terminal; a plurality of rectifying elements connected in series and aligned in the same direction of rectification, and having one terminal connected to said first output terminals of said first and second AC power sources, and another terminal which provides an output terminal for the rectifier, and nodes formed between the rectifying elements; a plurality of output capacitors connected in series with each other between said first output terminals and said reCtifier output terminal, and parallel to said rectifying elements so that each of said output capacitors is connected to selected nodes; and a plurality of second capacitors connected to one of said second output terminals of said first and second AC power sources and to nodes to which said output capacitors are not connected.

2. A voltage-multiplying rectifier as claimed in claim 1, wherein selected ones of said second capacitors are connected in series.

3. A voltage-multipling rectifier as claimed in claim 1, wherein said second capacitors are connected in parallel.

4. A voltage-multipling rectifier as claimed in claim 1, wherein said second capacitors are alternately connected to the second output terminals of the first and second AC power sources.

5. A voltage-multipling rectifer as claimed in claim 1, in which there are an even number of rectifying elements connected in series; the terminals of the output capacitors are connected to alternate ones of said nodes; and the second capacitors comprise first and second groups of equal numbers of capacitors, the first group being connected in series between the second output terminals of the first AC power source and a node and each connection of the capacitors being also connected to a node, said nodes being ones which are not connected to a terminal of the output capacitors, and the second group of capacitors being connected in series between the second output terminals of the second AC power source and a node and each connection of the capacitors being also connected to a node, said nodes being ones which are not connected either to a terminal of the output capacitors or said first group of capacitors.

6. A voltage-multipling rectifier as claimed in claim 1, in which there are an even number of rectifying elements connected in series; the terminals of the output capacitors are connected to alternate ones of said nodes; and the second capacitors comprise first and second groups of capacitors with each capacitor having first and second terminals, each first terminal of the capacitors of the first group being connected to said second terminal of the first AC power source and each second terminal being connected to a different node which is not connected to a terminal of said output capacitors; and each first terminal of the capacitors of the second group being connected to said second terminal of said second AC power source and each second terminal being connected to a different node not connected to either a terminal of said output capacitors or said first group of capacitors.

7. A voltage-multipling rectifier substantially as hereinbefore described with reference to the accompanying drawings.