GB2147771A - A synchronising pulse regenerating circuit for a CRT display monitor - Google Patents

Abstract

When a CRT raster display monitor is fed with RGB colour video signals and field and line sync. signals e.g. from a video game, the picture may require to be offset more than can be adjusted by conventional centering controls, due to the relative phasing of the video and sync. signals. A synchronising pulse regenerating circuit to provide wide phase adjustment has separate portions V and H for vertical and horizontal scans respectively. Each circuit portion comprises three monostable elements (1,2,3) or (9,10,11) connected in cascade. The first two monostable elements in each introduce two consecutive selected delays from the beginning of each received sync. pulse, and the third monostable element provides a restituted sync. pulse beginning at the end of these two delays. The vertical circuit may include a switchable inverter (7). <IMAGE>

Description

SPECIFICATION Synchronising pulse regenerating circuits This invention relates to synchronising pulse regenerating circuits and more particularly to such a circuit for regenerating synchronising pulses for a CRT (cathode ray tube) display monitor.

The invention has a particular but non-exclusive application for regenerating horizontal and vertical synchronising pulses produced by a coin-operated (arcade) video game device for application to a CRT display monitor.

Digitally implemented video game devices are made by many independent manufacturers throughout the world and whilst, in principle, these may operate notionally to a common standard of line and field raster display, in practice the vertical and horizontal synchronising pulses which are produced by different video game devices can have wide variations in their phase positions relative to the data contained in accompanying RGB video signals. As a result, their exists the problem that a CRT display monitor may not be able to handle such wide variations, with the circuit techniques presently used in a standard television receiver for field and line adjustment, to effect a desired positioning of a displayed picture on the screen of the CRT display monitor.

It is an object of the present invention to provide in orfor a CRT display monitor a synchronising pulse regenerating circuit which mitigates this problem.

According to the invention, a synchronising pulse regenerating circuit for a CRT display monitor comprises a first circuit portion for regenerating vertical (field) synchronising pulses and a second circuit portion for regenerating horizontal (line) synchronising pulses, each of which circuit portions comprises a first monostable element connected to receive a train of synchronising pulses, vertical or horizontal as the case may be, and responsive to each received pulse to produce at an output a first active logic level for a predetermined period less than the duration between corresponding instants of two successive synchronising pulses, each circuit portion further comprising a second monostable element which is responsive to the termination of said first active logic level to produce at an output a second active logic level for a predetermined period which is also less than the duration between corresponding instants of two successive synchronising pulses, and a third monostable element in each circuit portion being responsive to the termination of said second active logic level to produce at an output a third active logic level for a period appropriate to the relevant synchronising pulse, which latter is constituted by said third active logic level.

Thus, a synchronising pulse regenerating circuit according to the invention can produce restituted vertical and horizontal synchronising pulses of predetermined constant width, as determined by the period of said third active logic level, which are suitable for a CRT display monitor into which they are to be fed from, say, a video game device along with RGB video signals. The phases of the restituted vertical and horizontal synchronising pulses relative to the RGB video signals can be altered as necessary by a suitable selection of the periods of said first and second active logic levels so as to provide accurate positioning of the picture on the screen of the CRT display monitor in both vertical and horizontal directions.

In one embodiment of the invention which is contemplated the duration of said first active logic level is made less than nine-tenths the duration between said corresponding instants of two successive synchronisng pulses, to accommodate time variations due to temperature and life of a display monitor to be fed with the restituted synchronising pulses, and the duration of said second active logic level is made greater than one-tenth but less than nine-tenths the duration between said corresponding instants of two successive synchronising pulses.

Suitably, at least the first circuit portion is arranged to be responsive to the leading edge of each received vertical synchronising pulse, to provide a common start instant for this circuit portion irrespective of variations in the width of these pulses. (It has been found that vertical synchronising pulses can vary in width from different video game devices over the range 100 to 1000s.) This width variation has been found not to be problem with horizontal synchronising pulses because of their very short notional duration of around 4.7 > s. Thus, either edge of the horizontal synchronising pulses can be used to initiate the response of the second circuit portion.

In carrying out the invention vertical synchronising pulses of either positive or negative polarity can be catered for by providing at the input of the first monostable element in the first circuit portion an inverter which is arranged to be bypassed for one polarity of the pulses. Thus, the leading edge of either polarity of vertical synchronising pulse as applied to the first monostable element always changes in the same sense to an active logic level.

The first monostable element in the second circuit portion can have a trigger circuit connected at its input to receive the horizontal synchronising pulses and effectivey re-shape them priortotheirapplica- tion to this first monostable element.

Also in carrying out the invention vertical synchronising pulse trains of different frequency (e.g. either 60 Hz or 50 Hz) can be catered for a given implementation of the first monostable element circuit by providing therefor an RC time constant element the value of which can be changed selectively to alter the period of said first active logic level.

The synchronising pulse regenerating circuit can have an input circuit appropriate for receiving either separate synchronising signals or a composite vertical and horizontal synchronising signal.

In order that the invention may be more fully understood, reference will now be made by way of example to the accompanying drawings, of which Figure 1 shows a block diagram of a synchronising pulse regenerating circuit according to the invention; Figure 2 shows explanatory idealised waveform diagrams which are not drawn to scale; and Figure 3 shows diagrammatically the display screen of a CRT display monitor.

Referring to the drawings, the synchronising pulse regenerating circuit shown in Figure 1 comprises a circuit portion Vfor restituting received vertical synchronising pulses and a circuit portion H for restituting received horizontal synchronising pulses.

The circuit portion V comprises three monostable circuits 1,2 and 3 connected in cascade. The input of the monostable circuit 1 is connected to an input terminal 4 via an integrator 5 and two inverters 6 and 7. The output of the monostable circuit 3 is connected to an output terminal 8. The circuit portion H also comprises three monostable circuits 9, 10 and 11 connected in cascade between an input terminal 12 and an output terminal 13. An inverter 14 is connected between the input of the monostable circuit 9 and the input terminal 12. This inverter 14 is suitably a schmitt trigger circuit for effectively re-shaping the horizontal synchronising pulses Hs prior to their application to the monostable circuit 9.

In operation of the synchronising pulse regenerating circuit there is received from a video game device (not shown) vertical and horizontal synchronising pulses Vs and Hs which are applied to the input terminals 4 and 12, respectively. Alternatively, a composite synchronising signal Cs comprising both vertical and horizontal synchronising pulses can be applied to either terminal 4 or 12 when a link 15 interconnects these two terminals. Due to its time contant, the integrator 5 allows only the vertical synchronising pulses to be fed to the input of the monostable circuit 1 via the inverter 6. The inverter 6 only is connected in circuit for active positive vertical synchronising pulses so that the leading edge of each of these pulses is negative going to operate the monostable circuit 1.For active negative vertical synchronising pulses the inverter 7 is also connected in circuit by means of links 16 and 17 so as to maintain negative going leading edges of these pulses at the input of the monostable circuit 1.

Since the two circuit portions V and H function in essentially the same manner in providing restituted synchronising pulses of constant width and selected phase relative to the relevant applied synchronising pulses, only the operation of the circuit portion V will now be considered in detail. Due to the action of the circuit elements 5, 6, and possibly 7, there is applied to the input of the monostable circuit 1 a train of active negative pulses Vsn which correspond in pulse width and phase with the applied pulses Vs (or equivalent pulses in Cs). This pulse train is shown as waveform (a) in Figure 2. In response to the leading negative-going edge of each pulse Vsn, the monostable circuit 1 provides at its output a negative-going active logic level 1/NL for a period lid. This is illustrated by waveform (b) in Figure 2.At the termination of each period lid, the positive-going change in the logic level causes the monostable circuit 2 to provide at its output a negative-going active logic level 2/NLfor a period lid. This is illustrated by waveform (c) in Figure 2. The periods lid and 2/dare predetermined by two time constant circuits 18 and 19 which are associated with the two monostable circuits 1 and 2, respectively. The setting of the time constant circuit 18 provides either one of two different durations for the period 1/dto cater for received vertical synchronising pulses of 50 Hz and 60 Hz repetition frequency.The duration of the period lid is preferably less than nine-tenths the duration of the vertical synchronising pulse duty cycle period Void, as mentioned previously. The setting of the time constant circuit 19 provides a range of different possible durations for the period 2/dto cater for a desired extent of phase shift relative to the vertical synchronising pulses Vs. The duration of the period 2/dips preferably greater than one-tenth but less than nine-tenths the period Vsid, as also mentioned prviously. A fixed time constant circuit 20 determines the period of operation of the monostable circuit 3.

Since each of the two periods lid and 21d has a duration which is less than the duration between the leading edges of two successive pulses Vsm, these two periods lid and 2/dan together have a total duration less or greater than the duration Vsm, but not greater than two such durations. At the terminal tion of each period 21d, the positive going change in the logic level causes the monostable circuit 3 to provide at its output a positive going active logic level 3/PLfor a period 3/d. This is illustrated by waveform (d) in Figure 2. This logic level 31PL serves as a restituted vertical synchronising pulse Vs' at the output terminal 8.The duration of the period 3/dips selected to conform to the vertical synchronising pulse width which is required by a CRT display monitor into which the restituted vertical synchronising pulses Vs' are fed to effect field synchronisation. Since each period 3/dcommences after the consecutive durations of the preceding two periods lid and 2/d, it can be seen that the restituted vertical synchronising pulses Vs' can be arranged, by a suitable choice of the respective durations of these two periods, to occur anywhere between the leading edges of each two successive pulse Vsn as derived from the vertical synchronising pulses received at the input terminal 4.The circuit portion H achieves the same effect of constant pulse width and selected phase shift for restituted horizontal synchronising pulses Hs' at the output terminal 13 in response to horizontal synchronising pulses received at the input terminal 12. Thus, data contained in RGB video signals applied to a CRT display monitor along with the restituted vertical and horizontal synchronising pulses Vs' and Hs' can be given a different phase relative to these pulses, compared with the phase of this data relative to original vertical and horizontal synchronising pulses with which they are associated when generated by a video game device. As a result, a displayed picture represented by this data can be positioned where desired on the screen of the CRT display monitor.

Figure 3 shows by way of illustration a screen SC of a CRT display monitor on which a picture area PA is displayed. In accordance with the convention used extensively in video game display the screen SC is shown rotated 90 relative to a standard television screen to give a 3:4 aspect ratio. This means that the picutre lines occur vertically on the screen SC as viewed. The picture area PA is shown displayed offset towards the bottom right of the screen SC. In the absence of positional correction, this or some other offset display can be quite feasible due to the original relative phasing of data and synchronising pulses from a video game device. This is because there is no established protocol for software programmers of video games. In accordance with the present invention, such a positional offset can be readily corrected, to centre or otherwise re-position the picture area PA, as represented by the dotted rectangle PA', by providing for the raster scan of the CRT display monitor restituted vertical and horizontal synchronising pulses which are suitably phase shifted.

The implementation of a pulse regenerating circuit according to the invention can readily be effected using commercially available integrated circuits and other components. Also, the pulse regenerating circuit may be arranged to operate using active logic levels which are opposite to those used in the specific embodiment which has been described.

Claims (10)

1. Asynchronising pulse regenerating circuit for a CRT display monitor, comprising a first circuit portion for regenerating vertical synchronising pulses and a second circuit portion for regenerating horizontal synchronising pulses, each of which circuit portions comprises a first monostable element connected to receive a train of synchronising pulses, vertical or horizontal as the case may be, and responsive to each received pulse to produce at an output a first active logic level for a predetermined period less than the duration between corresponding instants of two successive synchronising pulses, each circuit portion further comprising a second monostable element which is responsive to the termination of said first active logic level to produce at an output a second active logic level for a predetermined period which is also less than the duration between corresponding instants of two successive synchronising pulses, and a third monostable element in each circuit portion being responsive to the termination of said second active logic level to produce at an output a third active logic level for a period appropriate to the relevant synchronising pulse, which latter is constituted by said third active logic level,

2.A synchronising pulse regenerating circuit as claimed in Claim 1, wherein the duration of said first active logic level is made less than nine-tenths the duration between said corresponding instants of two successive synchronising pulses, and the duration of said second active logic level is made greater than one-tenth but less than nine-tenths the duration between said corresponding instants of two successive synchronisng pulses.

3. A synchronising pulse regenerating circuit as claimed in Claim 1 or Claim 2, wherein at least the first circuit portion is arranged to be responsive to the leading edge of each received vertical synchronising pulse.

4. A synchronising pulse regenerating circuit as claimed in any preceding Claim, adapted to cater for vertical synchronising pulses of either positive or negative polarity by having at the input of the first monostable element in the first circuit portion an inverter which is arranged to be bypassed for one polarity of the pulses.

5. A synchronising pulse regenerating circuit as claimed in any preceding Claim, wherein the first monostable element in the second circuit portion has a trigger circuit connected at its input to receive the horizontal synchronising pulses and effectively re-shape them prior to their application to this first monostable element.

6. A synchronising pulse regenerating circuit as claimed in any preceding Claim, wherein vertical synchronising pulse trains of different frequency are catered for, for a given implementation of the first monostable element in the first circuit portion, by providing therefor an RC time constant element the value of which can be changed selectively to alter the period of said first active logic level.

7. A synchronising pulse regenerating circuit as claimed in any preceding Claim, having an input circuit appropriate for receiving either separate synchronising signals or a composite vertical and horizontal synchronising signal.

8. A synchronising pulse regenerating circuit as claimed in any preceding Claim, in combination with a CRT display monitor.

9. The combination claimed in Claim 8, together with a video game device connected to supply vertical and horizontal synchronising pulses to the pulse regenerating circuit for restitution, and RGB video signals directly to the CRT display monitor.

10. A synchronising pulse regenerating circuit, in or for use with a CRT display monitor, substantially as herein before described with reference to the accompanying drawings.