[go: up one dir, main page]

GB2138633A - Bonding semiconductor chips to a lead frame - Google Patents

Bonding semiconductor chips to a lead frame Download PDF

Info

Publication number
GB2138633A
GB2138633A GB08409512A GB8409512A GB2138633A GB 2138633 A GB2138633 A GB 2138633A GB 08409512 A GB08409512 A GB 08409512A GB 8409512 A GB8409512 A GB 8409512A GB 2138633 A GB2138633 A GB 2138633A
Authority
GB
United Kingdom
Prior art keywords
layer
semiconductor device
alloy layer
lead frame
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB08409512A
Other versions
GB2138633B (en
Inventor
Toshio Tetsuya
Hiroyuki Baba
Osamu Usuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of GB2138633A publication Critical patent/GB2138633A/en
Application granted granted Critical
Publication of GB2138633B publication Critical patent/GB2138633B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/4827—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4924—Bases or plates or solder therefor characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Die Bonding (AREA)

Abstract

In a semiconductor device a metal layer (3, 5) is deposited on the bottom plane of a semiconductor chip (1). An alloy layer (7) acts as a brazing agent for brazing together the metal layer (3, 5) and a lead frame (9). The alloy layer (7) comprises tin and copper and it may further include antimony, phosphorus and bismuth. The layers 3, 5 are of vanadium and nickel respectively. All the layers may be formed by evaporation, thermal deposition or by plating. A layer of gold may be applied beneath the alloy layer 7. <IMAGE>

Description

SPECIFICATION A semiconductor device This invention relates to an improvement on a semiconductor device and more particularly to a semiconductor device in which a semiconductor chip and lead frame are bonded together by a brazing agent prepared from an alloy of tin and copper.
Fig. 1 illustrates the construction of a common semiconductor device described, for example, in the Japanese disclosed patent applications No.
55-19805 and No. 55-19806. Referring to the construction of the semiconductor device of Fig. 1, a vanadium layer 3 is deposited on the bottom plane of a semiconductor chip 1. A nickel layer 5 is formed underneath the vanadium layer 3 to prevent the gold component of the later-described gold-germanium (Au-Ge) alloy from harmfully affecting said semiconductor chip 1 as a P type impurity. Said nickel layer 5 is bonded to a lead frame 9 by a brazing layer 7 prepared from an alloy mainly consisting of gold and germanium (hereinafter referred to as "the alloy layer 7").
The conventional semiconductor device constructed as described above is generally received in a mold of, for example, #synthetic resin (not shown). When, however, a semiconductor device of such construction is applied for long hours in an atmosphere of, for example, high humidity, moisture tends to seep into an interstice defined between said synthetic resin mold and semiconductor device. As a result, a local battery is likely to be produced between the nickel layer 5 and alloy layer 7. In such cases, the nickel layer 5 acts as a negative electrode, and the alloy layer 7 functions as a positive electrode.The nickel layer 5, now acting as a negative electrode, undergoes electrolytic corrosion and melts, probably resulting in the formation of a gap in part of the interface between said vanadium layer 3 and alloy layer 7 or giving rise to the brittle condition of the nickel layer 5 itself. When, therefore, the nickel layer 5 undergoes electrolytic corrosion, the semiconductor chip 1 tends to be dislodged from the lead frame 9. Further, when the lead frame-9 is applied as a collector electrode and the nickel layer 5 undergoes electrolytic corrosion, insufficient electrical connection results between the semiconductor chip 1 and lead frame 9, deteriorating the electrical property of the semiconductor device.For instance, the saturated voltage Vce (set) between the collector and emitter raises during the application of the semiconductor device, or its electric property falls off the prescribed initial level. Further, when the nickel layer 5 is subject to electrolytic corrosion, heat transmission between the semiconductor chip 1 and lead frame 9 falls (thermal conductivity decreases). In such cases, heat radiated from the semiconductor is not fully released due to the failure of not being sufficiently transmitted to the lead frame 9. The Au-Ge alloy needed as a brazing agent is extremely expensive because it mainly consists of gold and this has obstructed the reduction in cost for a semiconductor device.
This invention has been accomplished in view of the above-mentioned circumstances, and is intended to provide highly reliable semiconductor device which can be cheaply manufactured.
To attain the above-mentioned object, this invention provides a semiconductor device which comprises a semiconductor chip, at least one metal layer mounted on the bottom plane of the semiconductor chip, a lead frame, and a tincopper alloy layer for brazing together the at least one metal layer and the lead frame.
This invention provides an inexpensive semiconductor device of high reliability which offers the advantages that regardless of the rigid condition in which the subject semiconductor device is applied for long hours, no local battery is created between the at least one metal layer and alloy layer; the semi-conductor chip does not fall off the lead frame; the subject semiconductor device does not deteriorate in electrical property; the saturated voltage impressed between the collector and emitter of the subject semiconductor device is not raised; the electrical property of the subject semiconductor device does not fall off the specified initial level; heat transmission between the semiconductor chip and lead frame does not decline; noticeable reduction is ensured in the cost of manufacturing a semiconductor device, and particularly the cost of the alloy layer; and the normal cost of a tin-copper alloy is lower than one tenth of that of the Au-Ge alloy.
This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a cross sectional view of a common semiconductor device; Fig. 2 is a cross sectional view of a semiconductor device according to a first embodiment of this invention, showing one step of the sequential steps of its manufacturing; and Fig. 3 is a cross sectional view of a semiconductor device according to a second embodiment of the invention, s#howing one step of the sequential steps of its manufacturing.
A description may now be made with reference to Figs. 1 and 2 of a semiconductor device according to a first embodiment of this invention.
A semiconductor device embodying this invention is characterized in that the alloy layer 7 shown in Fig. 1 is prepared from a tin-copper alloy. A semiconductor device of such construction can be manufactured through the undermentioned steps.
A vanadium layer 3 is formed on the backside (which is bonded to a lead frame) of a semiconductor wafer before being divided as a semiconductor chip. This vanadium layer 3 is produced by the evaporation process with a thickness ranging, for example, between 30 nm and 70 nm. A nickel layer 5 is formed underneath said vanadium layer 3 by the evaporation process with a thickness ranging, for example, between 100 nm and 300 nm. This nickel layer 5 reduces the P type impurity effect executed on the semiconductor chip 1 by the copper included in the above-described tin-copper alloy layer 7. The tin-copper alloy layer 7 is formed underneath said nickel layer 5 by evaporation process. And the tincopper alloy layer 7 comprises 38 % to 92.4 % by weight of tin and copper as the remainder.This tin-copper alloy layer 7 is deposited with a thickness ranging between, for example, 0.5 ym and 10 ym. Tin and copper have substantial the same temperature under the same vapor pressure.
For instance, when the vapor pressure stands at 0.1 Torr, the tin has a temperature of 1685 K and the copper has a temperature of 1690 K.
Therefore, tin-copper alloy layer 7 which is deposited by the evaporation process has substantially the same composition as the tincopper alloy used as a evaporation source. A semiconductor wafer on the backside of which aforesaid three layer 3, 5, 7 are mounted is divided into individual semiconductor chips by scribing. Thus is obtained a semiconductor chip of Fig. 2, on the backside of which the three layers 3, 5, 7 are deposited. The alloy layer 7 is pressed against a heated lead frame 9 to effect the melting of said tin-copper alloy layer, which is later cooled into the solid form. As a result, the nickel layer 5 deposited below the semiconductor chip 1 and lead frame 9 are secularly bonded together by the alloy layer 7. The subject semiconductor device having a construction shown in Fig. 1 is produced through the above-mentioned steps.
The manufactured semiconductor device was subjected to a pressure cooker test. This test was carried out by applying the normally molded semiconductor device embodying this invention to the following conditions for 300 hours: Pressure 2 atmospheres Humidity 100 % Temperature 12100 The semiconductor device of this invention proved by the test to offer the advantages that no electrolytic corrosion took place in the nickel layer 5, no change appeared in the property of said semiconductor device, and the semiconductor chip 1 ? did not fall off the lead frame 9.
The foregoing embodiment referred to the case where the alloy layer 7 comprised of 38 % to 92.4 % by weight of tin and copper as the remainder. The tin-copper alloy whose composition falls within the above range retains a liquid phase over a temperature of 4150 C and melts at a relationly low temperature (4150 C). Therefore, the semiconductor chip 1 can be easily fixed to the lead frame 9 and, moreover, is not-thermally effected. However, it will be noted that this invention is not limited to the above-mentioned embodiment. In so far as this invention goes, tin and copper are alloyed together in any optional proportions.
The aforementioned embodiment referred to the case where the alloy layer 7 comprises tin and copper. But this invention is not limited to this specific alloy. In other words, any alloy mainly comprising of tin and copper well serves the purpose, provided said alloy extents no harmful effect on the semiconductor chip 1. In other words, said alloy 7 may further comprise, for example, antimony (Sb), phosphorus (P), or bismuth (Bi). These metals reduce the effect of P type impurity exerted on the semiconductor chip 1 by the copper component of said alloy layer 7.
When, therefore, the aforesaid vanadium layer 3 and the nickel layer 5 can fully eliminate the harmful effect of P type impurity exerted on the semiconductor chip 1 by the copper component of said alloy layer 7, it is not always necessary to add any of the above-listed metals: (Sb), (P) and (Bi).
In the foregoing embodiment, the alloy layer 7 was deposited with a thickness ranging between 0.5 ym and 10 ym. However, this invention is not limited to this. In other words, thickness of the alloy layer 7 may be selected optionally in consideration of the surface roughness of the lead frame 9.
The above-mentioned embodiment referred to the case where said alloy layer 7 was first formed and then fixed to the lead frame 9. However, this invention is not limited to this process. For instance, it is possible to deposit a gold layer 1 1 underneath the alloy layer 7 as shown in Fig. 3.
The gold layer 11 prevents oxidation of the alloy layer 7. And later the gold layer 1 1 bonds together both semiconductor chip 1 and lead frame 9 by the same process as previously mentioned. During this step, the layers 7 and 1 1 melt, and later are cooled into a solid form. At this time, the gold constituting said layer 11 seeps into the alloy layer 7.
Throughout the foregoing embodiments, the vanadium layer 3 having a thickness ranging between 30 nm and 70 nm and the nickel layer 5 having a thickness ranging between 100 nm and 300 nm was deposited on the backside of the semiconductor chip 1. However, no limitation is imposed on the kind, number and thickness of metal layers deposited on the backside of the semiconductor chip 1. In other words, it is possible to apply any layer prepared from a known material provided it has a good brazing property, high conductivity and satisfactory thermal conductivity, exerts no harmful electric effect on the semiconductor chip 1, and prevents the copper component of the alloy layer 7 from undesirably affecting said semiconductor chip 1.
Further, it is advised that the number and thickness of the above-mentioned metal layers, deposited on the backside of the semiconductor chip 1, be determined in consideration of the extent to which the copper component of the alloy layer 7 may affect the semiconductor chip.
Further, the above-mentioned layers can be optimally formed, for example, by thermal deposition or plating.

Claims (10)

1. A semiconductor device which comprises: a semiconductor chip; at least one metal layer deposited on the bottom plane of said semiconductor chip; a lead frame; and an alloy layer acting as a brazing agent for bonding together said at least one metal layer and lead frame, and wherein said alloy layer comprises tin and copper.
2. The semiconductor device according to claim 1, wherein said alloy layer comprises 38 % to 92.4 % by weight of tin and copper as the remainder.
3. The semiconductor device according to claim 1, wherein said alloy layer has a thickness ranging from 0.5 micron to 10 microns.
4. The semiconductor device according to claim 1 , wherein said alloy layer further comprises antimony (Sb).
5. The semiconductor device according to claim 1, wherein said alloy layer further comprises phosphorus (P).
6. The semiconductor device according to claim 1 wherein said alloy layer further comprises bismuth (Bi).
7. The semiconductor device according to claim 1, wherein a gold layer is deposited on the plane, which is to be bonded to said lead frame, of said alloy layer; and later said alloy layer and gold layer are melted, thereby causing the molten gold to seep into said alloy layer.
8. The semiconductor device according to claim 1 , wherein said at least one metal layer comprises: a first metal layer deposited on the bottom plane of said semiconductor chip; and a second metal layer formed of a different metal from that of said first metal layer and mounted thereon, and said alloy layer bonds together said second metal layer and lead frame.
9. The semiconductor device according to claim 8, wherein said first metal layer is formed of vanadium and said second metal layer is prepared from nickel.
10. A semiconductor device, substantially as hereinbefore described with reference to Figs. 2 and 3 of the accompanying drawings.
GB08409512A 1983-04-16 1984-04-12 Bonding semiconductor chips to a lead frame Expired GB2138633B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58066340A JPS59193036A (en) 1983-04-16 1983-04-16 Semiconductor device

Publications (2)

Publication Number Publication Date
GB2138633A true GB2138633A (en) 1984-10-24
GB2138633B GB2138633B (en) 1986-10-01

Family

ID=13313027

Family Applications (1)

Application Number Title Priority Date Filing Date
GB08409512A Expired GB2138633B (en) 1983-04-16 1984-04-12 Bonding semiconductor chips to a lead frame

Country Status (3)

Country Link
JP (1) JPS59193036A (en)
DE (1) DE3413885A1 (en)
GB (1) GB2138633B (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0186411A2 (en) * 1984-12-28 1986-07-02 Kabushiki Kaisha Toshiba Semiconductor device in which a semiconductor chip is fixed to a base
US4791031A (en) * 1986-10-29 1988-12-13 Sumitomo Metal Mining Co. Ltd. Lead frame for IC having a wire bonding part composed of multi-layer structure of iron containing alloy, refractory metal and aluminum
US20100089498A1 (en) * 2006-12-25 2010-04-15 Sanyo Special Steel Co., Ltd. Lead-Free Jointing Material and Method of Producing the Same
US7776452B2 (en) 2004-08-10 2010-08-17 Neomax Materials Co. Ltd. Heat sink member and method of manufacturing the same
US7830001B2 (en) 2005-05-23 2010-11-09 Neomax Materials Co., Ltd. Cu-Mo substrate and method for producing same
US8763884B2 (en) 2006-09-29 2014-07-01 Kabushiki Kaisha Toshiba Joint with first and second members with a joining layer located therebetween containing Sn metal and another metallic material; methods for forming the same joint
CN104465578A (en) * 2013-09-13 2015-03-25 株式会社东芝 Semiconductor device and semiconductor module

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3446780A1 (en) * 1984-12-21 1986-07-03 Brown, Boveri & Cie Ag, 6800 Mannheim METHOD AND JOINING MATERIAL FOR METALLICALLY CONNECTING COMPONENTS
JPS61156823A (en) * 1984-12-28 1986-07-16 Toshiba Corp Semiconductor device
JPH0783034B2 (en) * 1986-03-29 1995-09-06 株式会社東芝 Semiconductor device
JP2008221290A (en) * 2007-03-14 2008-09-25 Toshiba Corp Joined member and joining method
JP5758242B2 (en) * 2011-09-06 2015-08-05 山陽特殊製鋼株式会社 Lead-free bonding material
JP5744080B2 (en) * 2013-02-04 2015-07-01 株式会社東芝 Bonded body and semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB907734A (en) * 1959-06-06 1962-10-10 Teizo Takikawa Method of soldering silicon or silicon alloy
GB1548756A (en) * 1975-04-05 1979-07-18 Semikron Gleichrichterbau Semicondutor device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1298387C2 (en) * 1964-02-06 1973-07-26 Semikron Gleichrichterbau Semiconductor arrangement
GB1389542A (en) * 1971-06-17 1975-04-03 Mullard Ltd Methods of securing a semiconductor body to a support
US3821785A (en) * 1972-03-27 1974-06-28 Signetics Corp Semiconductor structure with bumps
DE2930789C2 (en) * 1978-07-28 1983-08-04 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Semiconductor device
JPS592174B2 (en) * 1978-07-28 1984-01-17 株式会社東芝 semiconductor equipment
JPS592175B2 (en) * 1978-07-28 1984-01-17 株式会社東芝 semiconductor equipment
JPS5521106A (en) * 1978-07-31 1980-02-15 Nec Home Electronics Ltd Method of forming ohmic electrode
JPS55107238A (en) * 1979-02-09 1980-08-16 Hitachi Ltd Semiconductor device and method of manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB907734A (en) * 1959-06-06 1962-10-10 Teizo Takikawa Method of soldering silicon or silicon alloy
GB1548756A (en) * 1975-04-05 1979-07-18 Semikron Gleichrichterbau Semicondutor device

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0186411A2 (en) * 1984-12-28 1986-07-02 Kabushiki Kaisha Toshiba Semiconductor device in which a semiconductor chip is fixed to a base
EP0186411A3 (en) * 1984-12-28 1987-04-01 Kabushiki Kaisha Toshiba Semiconductor device in which a semiconductor chip is fixed to a base
US4954870A (en) * 1984-12-28 1990-09-04 Kabushiki Kaisha Toshiba Semiconductor device
US4791031A (en) * 1986-10-29 1988-12-13 Sumitomo Metal Mining Co. Ltd. Lead frame for IC having a wire bonding part composed of multi-layer structure of iron containing alloy, refractory metal and aluminum
US7776452B2 (en) 2004-08-10 2010-08-17 Neomax Materials Co. Ltd. Heat sink member and method of manufacturing the same
US7830001B2 (en) 2005-05-23 2010-11-09 Neomax Materials Co., Ltd. Cu-Mo substrate and method for producing same
US8763884B2 (en) 2006-09-29 2014-07-01 Kabushiki Kaisha Toshiba Joint with first and second members with a joining layer located therebetween containing Sn metal and another metallic material; methods for forming the same joint
US20100089498A1 (en) * 2006-12-25 2010-04-15 Sanyo Special Steel Co., Ltd. Lead-Free Jointing Material and Method of Producing the Same
US9157135B2 (en) * 2006-12-25 2015-10-13 Sanyo Special Steel Co., Ltd. Lead-free jointing material and method of producing the same
CN104465578A (en) * 2013-09-13 2015-03-25 株式会社东芝 Semiconductor device and semiconductor module

Also Published As

Publication number Publication date
JPH0226376B2 (en) 1990-06-08
GB2138633B (en) 1986-10-01
DE3413885C2 (en) 1990-02-22
DE3413885A1 (en) 1984-10-25
JPS59193036A (en) 1984-11-01

Similar Documents

Publication Publication Date Title
US5794839A (en) Bonding material and bonding method for electric element
EP0253691B1 (en) Silicon die bonding process
JP5487190B2 (en) Power semiconductor module manufacturing method
CA2080931C (en) Bonding method using solder composed of multiple alternating gold and tin layers
US6140703A (en) Semiconductor metallization structure
US4954870A (en) Semiconductor device
GB2138633A (en) Bonding semiconductor chips to a lead frame
US8110437B2 (en) Method for attaching a semiconductor chip in a plastic encapsulant, optoelectronic semiconductor component and method for the production thereof
US5332695A (en) Method of manufacturing semi conductor device mounted on a heat sink
EP0880801B1 (en) DIE ATTACHED SiC AND DIE ATTACH PROCEDURE FOR SiC
JPS6141135B2 (en)
US3480842A (en) Semiconductor structure disc having pn junction with improved heat and electrical conductivity at outer layer
GB2300375A (en) Bonding method for electric element
CA1244147A (en) Die bonding process
US4921158A (en) Brazing material
JPS61156823A (en) Semiconductor device
JPS6352461B2 (en)
US20010017377A1 (en) Chip-type semiconductor device
JPH0864799A (en) Semiconductor chip, semiconductor device using it and manufacture thereof
US2953729A (en) Crystal diode
JPH04352432A (en) Semiconductor device and manufacture thereof
JPS61156824A (en) Semiconductor device
JPH0118580B2 (en)
JPS61156825A (en) Semiconductor device
JPS5936822B2 (en) Pressure contact type semiconductor device

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19980412