GB2135552A - Television receivers for time division multiplexed signals - Google Patents

Abstract

In a television receiver for signals according to the C-MAC system where the chrominance and luminance signals are compressed and transmitted sequentially during television line periods, the demodulated analogue signal is applied to an analogue-to-digital converter 9. The zero level of chrominance reference is extracted by a clamp circuit 10 whilst the black level reference is extracted by a further clamp circuit 13. These reference levels are applied to a difference circuit 18 and the resulting difference subjected to amplification in an amplifier 19. The output of amplifier 19 is applied to the reference input of the converter 9. In the received signal the chrominance component has a larger maximum amplitude than that of the luminance component. To enable the converter 9 to produce digital signals proportional to content rather than absolute value the amplifier 19 is arranged to change its gain such that its output is greater during periods containing the chrominance component than during periods containing the luminance component. <IMAGE>

Description

SPECIFICATION Television receivers for time division multiplexed signals The invention relates to a television receiver for a time division multiplexed television signal discrete lines of which sequentially contain a time compressed chrominance component and a time compressed luminance component, the maximum amplitude of the chrominance component being greater than the maximum amplitude of the luminance component, each line also containing a first and a second reference level outside the periods occupied by the chrominance and luminance components, said receiver comprising demodulating means for producing said signal from a received television transmission, means for applying said demodulated signal to an analogue signal input of an analogue-to-digital converter for producing digital signals from the analogue chrominance and luminance components applied thereto and means for applying a reference to a reference input of said analogue-to-digital converter.

Following the decision in March 1 982 that direct broadcast by satellite (DBS) of television programmes for the United Kingdom would commence in 1982 an Advisory Panel was established to report on technical transmission standards. The Report published in November 1 982 by Her Majesty's Stationary Office as Cmnd 8751 recommended the Independent Broadcast Authority's Multiplexed-Analogue Component (C MAC) system should be adopted for DBS, which recommendation has subsequently been accepted.

Figure 1 of the accompanying drawings diagrammatically shows one line period of a C MAC television signal which occupies 64,us and each line is divided notionally into a number of bit or sample periods at a clock rate of 20.25 MHz, there being 1296 such samples per line. Each line contains the following in the sequence given:: a=196 bits-synchronisation, sound/data b=4 samples-transition from end of data c=1 5 samples-main clamp period (zero-level of chrominance reference) d=355 samples-chrominance (C) e=4 samples-grey-to-black transition f=10 samples-black level clamp period (black level reference) 9=710 samples-luminance (Y) h=4 samples-transition into data The chrominance component is time compressed at a rate of 3::1 so that 52.59 ys of chrominance information is compressed to occupy 17.53 Ms (355 samples) with the R-Y colour difference signal being transmitted on alternate lines and the B-Y colour difference signal being transmitted on the intervening lines. The luminance component is time compressed at a rate of 3:2 so that 52.59,us of luminance information is compressed to occupy 35.06 ,us (710 samples).

A television receiver for the above television signal will need to expand the chrominance and luminance components which can be more conveniently done by converting the analogue components into digital signals and subjecting these to expansion by shift registers or the like.

When converting the components to digital signals it is essential to ensure that correct conversion takes place especially as the maximum amplitude of the chrominance component (1.3 V p-p) is greater than the maximum amplitude of the luminance component (1 Vp-p).

It is an object of the present invention to provide a television receiver for a time multiplexed television signal which substantially ensures a correct conversion of the analogue components to digital signals.

The invention provides a television receiver for a time division multiplexed television signal discrete lines of which sequentially contain a time compressed chrominance component and a time compressed luminance component, the maximum amplitude of the chrominance component being greater than the maximum amplitude of the luminance component, each line also containing a first and a second reference level outside the periods occupied by the chrominance and luminance components, said receiver comprising demodulating means for producing said signal from a received television transmission, means for applying said demodulated signal to an analogue signal input of an analogue-to-digital converter for producing digital signals from the analogue chrominance and luminance components applied thereto and means for applying a reference to a reference input of said analogue-to-digital converter, characterised in that the demodulated signal is additionally applied to sampling means for sampling the respective values of said first and second reference levels during their occurrence and storing these values, means for producing the difference between the stored first and second reference levels and subjecting this difference to amplification the degree of which has a first value during periods of the compressed chrominance component and a second value which is less than said first value during periods of the compressed luminance component, means for applying the resulting amplified difference as the reference to said analogue-to-digital converter, the values of amplification being such that the applied reference has a first value during periods of the compressed chrominance component and a second value during periods of the compressed luminance component which voltage values are proportional or correspond to the respective maximum amplitudes of the chrominance and luminance components as applied to said analogue-to-digital converter.

The means for producing the difference and for amplifying the difference may comprise a differential amplifier having first and second current paths, from which the output is derived, the current through each path comprising a first component determined by the difference between the first and second reference levels and a second component whose magnitude changes such that it has a first value during periods of the compressed chrominance component and a second value during periods of the compressed luminance component. The second current component may have the same given value in each current path during periods of the compressed luminance component and may be zero in one current path and twice the said given value in the other current path during periods of the compressed chrominance component.The given value may be dependent upon the difference between the first and second reference levels.

The said differential amplifier may comprise first and second transistors the collector circuits of which respectively form the first and second current paths, the collector circuits of the first and second transistors being additionally connected to respective first and second current sources during periods of the compressed luminance component whilst the collector circuit of one of the transistors is connected to both first and second current sources during periods of the compressed chrominance component.

When the transmitted signal is subjected to energy dispersal to reduce interference with other transmitted information in the same frequency band the demodulated signal is modulated at a frequency corresponding to the frame frequency as a result of this energy dispersal in which case the reference voltage as applied to the analogueto-digital converter may be subjected to a corresponding frame frequency modulation to compensate for changes in level of the demodulated signal as applied to the analogue input of the converter. To achieve this the common mode voltage of the amplified difference may be compared with a corresponding one of said reference levels to provide a control for the current flowing in a stage providing amplification.

The common mode voltage may be derived from the junction of first and second equal value resistors connected between the collector circuits of said first and second amplifier transistors, this common mode voltage and the corresponding one reference level being applied to a differential amplifier whose output controls the conduction of a further transistor forming a current source in the emitter circuits of the first and second transistors.

The above and other features of the invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 2 is a block diagram of a television receiver according to the invention, Figure 3 is a block diagram of an analogue-todigital converter for use in the receiver of Figure 2, Figure 4 shows the energy dispersal waveform as applied to a transmitted C-MAC television signal, Figure 5 is a modification of part of the receiver of Fig. 2, and Figure 6 is a circuit diagram of certain components in Figure 5.

The television receiver to be described in relation to Figure 2 is intended for the reception of frequency modulated television signals transmitted by a satellite using the C-MAC system in the 12 GHz broadcasting band. In Figure 2 these signals are received by a dish aerial 1 of appropriate size, the received signals being immediately applied to a down converter 2 in which the incoming signal is frequency converted to a frequency just above the UHF broadcast bands. This conversion to a lower frequency allows signals to be conveyed to the input terminal 3 of the receiver by way of a co-axial cable. The receiver input 3 is connected to an RF and frequency changer stage 4 where the frequency of the received signal is further down converted to an intermediate frequency of say 134 MHz which is applied for further amplification to an IF amplifier stage 5.The amplified i.f. signals from stage 5 are frequency demodulated in an FM demodulator stage 6 to produce signals at a teminal 7 which correspond (during picture information lines) with that shown in Figure 1. These demodulated signals are applied to a sync. separator and generator stage 8 which from the incoming synchronising information produces the necessary clock and other control pulses as will become apparent. In addition the demodulated signals are also applied to terminal A an analogue-to-digital converter 9 where the compressed chrominance and compressed luminance components are converted to digital form before being subjected to further signal processing.

The demodulated signals at terminal 7 are also applied to a zero-level of chrominance clamp circuit 10 comprising a controlled switch 11 and a storage capacitor 12 and a black level clamp circuit 1 3 also comprising a controlled switch 14 and a storage capacitor 1 5. Switch 11 is closed during the time during each picture line period when the zero level of chrominance reference is present i.e. during samples 199 to 213 inclusive approximately between 9.78 to 10.52 Ms from the start of each line (data) period (Figure 1, period c). Closure of the switch 11 is controlled by a pulse of appropriate duration also corresponding to period c in Figure 1 generated in the sync. separator and generator stage 8 and conveyed over a connection 1 6 to the control input of controlled switCh 11. During the period when switch 11 is closed the voltage value corresponding to the zero level of chrominance reference is applied to capacitor 12 on which this value is stored once switch 11 is opened, this process being repeated during successive picture line periods.

In a similar manner switch 14 is closed during the time during each picture line period when the black level reference is present i.e. during samples 573 to 582 inclusive approximately between 28.25 to 28.74 ,us from the start of each line (data) period (Figure 1, period f). Closure of switch 14 is effected by a pulse of appropriate length also corresponding to period fin Figure 1 from sync. separator and generator stage 8 and applied to the control input of switch 14 over connection 1 7. When switch 14 is closed the voltage value corresponding to the black level is applied to capacitor 1 5 on which this value is stored once switch 14 is opened, the process also being repeated during successive picture line periods.

The stored voltages from the two capacitors 12 and 1 5 are applied to separate high impedance inputs of a difference circuit 18 which produces as an output the difference between the two applied reference levels. In the case of a C MAC signal as described in relation to Figure 1 with the given signal amplitudes it will be appreciated that the difference between these two levels is 0.5 volt as the zero level of chrominance coincides with half the maximum amplitude of the luminance component.The output voltage from the difference circuit 1 8 is applied to an amplifier stage 1 9 the amplified output voltage of which is applied as a reference to the reference input R of the analogue-to-digital converter 9 a clocking input C of which receives clock pulses at the clock frequency of 20.25 MHz over a connection 20 from the sync. separator and pulse generator stage 8.

A suitable analogue-to-digital converter 9 is shown in some detail in Figure 3. In Figure 3 a potential divider comprising a plurality of resistors 211 212 213. . . 21n-2, 21n-1, 21n s connected between two reference voltage input terminals R', R" as the applied reference would have two levels as will be described later. The number of resistors in the potential divider is equal to the number of incremental steps in the applied analogue chrominance or luminance components to be represented in the digital signal produced by the converter.The voltage points on the potential divider 21 are each connected to a first input of a corresponding number of voltage comparators 221 222, 223...22"-2, 22n-1, 22n a second input of which receive the analogue chrominance or luminance component present at terminal A. The voltage comparators 22 are of the type which produce a binary '0' at their output if the analogue component then present at input A is below the voltage received from the potential divider but produces a binary '1' if the analogue component is at or above the potential divider voltage.The resulting binary outputs from the comparators 22 are applied to a digital encoder 23 which produces at the digital output D an n bit parallel digital code for the changing content of the analogue component at a rate determined by the clock pulse at the input C which is also applied to the encoder 23. The number of parallel bits in the output code will obviously be determined by the number of incremented steps it is desired to resolve in the analogue component.

As described in relation to Figure 1, the maximum amplitude of the compressed chrominance component (1.3 voltage peak-topeak) is greater than the maximum amplitude of the compressed luminance component (1 volt peak-peak) and without further steps this would be reflected in the digital output of the analogueto-digital converter 9 if a substantially constant reference voltage directly related to the difference voltage from the difference circuit 1 8 were applied to the reference input R of the converter 9 from the amplifier 19 over the whole of each picture line. For this reason the gain of the amplifier 1 9 is switched during each picture line period so that it has a higher gain during the presence of the compressed chrominance component than during the presence of the compressed luminance component.For the type of analogue-to-digital converter 9 described in relation to Figure 3 the gain of amplifier 19 is switched such that during the occurrence of the two voltage components of the reference applied to input R equal the maximum amplitude for the component present at a given time. Thus for a difference output of 0.5 volts from difference stage 18 the gain of amplifier 19 is arranged to be 2.6 during the occurrence of the compressed chrominance component to produce for the input R a reference of 1.3 volts (which corresponds to the maximum amplitude for this component) whilst the gain is arranged to be 2.0 during the occurrence of the compressed luminance component to produce a reference of 1.0 volts (which corresponds to the maximum amplitude for this component).

In the above description it has been assumed that the circuitry of the l.F. amplifier stage 5 and the F.M demodulator stage 6 are proportioned such that the signal recovered at the output of the demodulator has signal levels corresponding to those at the transmitter i.e. the two components having maximum amplitudes of 1.3 and 1.0 volts.

Due to the possible spread in the circuit components employed in these stages the signal levels may not exactly correspond with those at the transmitter and this would also give rise to an incorrect digital output if the reference voltage for input R were held constant for each component.

With the arrangement described this is compensated for. If, say, the spread is such that the compressed chrominance component at the output of the FM demodulator 6 has a maximum amplitude of 1.43 volts and that for the compressed luminance component is 1.1 volts, the voltage difference produced in the difference stage 1 8 from the increased zero-level of chrominance and black level references will be 0.55 volts. The reference voltage applied to the input R of the converter 9 will then be 2.6x0.55=1.43 volts during the compressed chrominance component and 2.0x0.55=1.1 volts during the compressed luminance component, which reference voltages correspond with the maximum amplitudes of the components applied to terminal A of the converter 9.Thus it will be seen that with the arrangement described the reference voltage not only changes for the two different components but also corrects for differences in the nominal value of the signal from the FM demodulator 6.

The digital output D from the analogue-todigital converter 9 is applied to the digital input of a digital processing circuit 25 in which the compressed chrominance and luminance digital signals are expanded to occupy the normal part of a television line period. Thus if these signals are read into respective stores at the clocking rate of 20.25 MHz and the chrominance components are read from their separate U and V stores at a rate of 6.75 MHz whilst the luminance component is read out from its store at 1 3.5 MHz then the expanded components will occupy a period of 52.59 ys per television line.The connection 26 from the sync. separator and generator stage 8 to the processor 25 is assumed to be a multiple connection conveying the 6.75 MHz, 13.5 MHz and 20.25 MHz pulse trains from the stage 8 to the processor 25.

The expanded digital components, that is the luminance Y and separate R-Y and B-Y chrominance components, are applied to respective digital-to-analogue converters 27 whose outputs produce their respective signals in analogue form, the necessary clocking signals being applied from generator 8 over a connection 28. These analogue signals are applied to a matrix circuit 29 which produces respective red (R), green (G) and blue (B) colour signals which are applied in turn to a display stage 30 where these signals are prepared for application to a display device 31 included in the display stage 30 and to which line and field synchronising signals are applied from the generator 8 over a connection 32.

In the above description it has been assumed that the analogue signals for the analogue-todigital converter 9 are not subjected to a reduction in level prior to application to or in the converter 9. If this should happen then the reference voltage applied to the converter should be correspondingly reduced. The converter itself need not take the form shown in Figure 3 but could be of any other suitable design requiring a reference voltage input and capable of operating at the required conversion rate.

Although in Figure 2 the outputs of the digitalto-analogue converter 27 are shown connected to a matrix 29 to produce signals for display, the portions of the described apparatus up to and including the converters 27 could be incorporated in an adaptor in which the outputs of the converters are re-modulated according to another transmission system, such as PAL at UHF for application to a television receiver of that type.

With the C-MAC system the chrominance and iuminance components of the video signal are to be frequency modulated where the deviation of the carrier is to be 13.5 MHz per volt of the preemphasised signal. In addition an energy dispersal signal is to be added to the video signal consisting of a frame synchronous triangular waveform of frequency 25 Hz with a peak-to-peak amplitude of 600 KHz after modulation in the radio frequency channel. The dispersal waveform to be added to the video signal is shown in Figure 4, the deviation at the start of line 1 corresponding to a reduction of carrier frequency by 300 KHz. The vertical lines in Figure 4 indicate that the dispersal waveform is returned to zero during each data period.With the d.c. connection shown in Figure 2 between the FM demodulator 6 and input A of analogue-to-digital converter 9 it will be appreciated that the video signal applied to that input will have the 25 Hz triangular waveform superimposed on it. In the presence of reference voltages which are constant for the two video components correct digital codes would only be produced by the converter 9 during four lines of each frame period. Figure 5 diagrammatically shows a way in which this can be overcome, this figure corresponding in part to that of Figure 2 and where like references are used for like components.

A detailed description of the parts of Figure 5 aiready described in relation to Figure 2 will not be given. In Figure 5 it will be seen that the switched gain amplifier 1 9 has two outputs from which the R' and R" inputs of the analogue-todigital converter 9 are derived and which represent the maximum and minimum amplitudes of the respective compressed video components.

Each output is connected to a first input of a respective adder circuit 33 and 34 whose outputs are respectively connected to the R' and R" inputs of the converter 9. Between these adder outputs is provided a potential divider two resistors 35 and 36 of equal value. The junction of these resistors is at the common mode voltage of the levels applied to inputs R' and R", this junction being connected to the inverting input (-) of a differential amplifier 37. The noninverting input (+) of this differential amplifier is connected to the junction of capacitor 12 with switch 11 to receive the zero level of chrominance reference stored on that capacitor which changes from line to line as a result of the energy dispersal waveform.The output of the differential amplifier 37 is connected to the second input of each adder circuit 33 and 34 and the action of the differential amplifier is such that the common mode voltage follows the changes in the zero level of chrominance reference and hence the voltage levels applied to the reference inputs R' and R" of the converter are incrementally changed line by line with the incremental changes in the zero level of chrominance reference.

Figure 6 shows a circuit diagram of a practical embodiment of parts of a television receiver according to the invention. In Figure 6 the video signal present at terminal 7 is applied to the base of a transistor T1 the collector of which is connected to a supply rail connected through a terminal 38 to the positive terminal of a supply whilst the emitter of this transistor is connected through a resistor R1 to a second supply rail connected through a terminal 39 to the negative terminal of the supply. This transistor functions as an emitter follower and its emitter is connected to the switches 11 and 14 and the base of a transistorT2 connected in a similar manner to that of transistor T1 with an emitter resistor R2.

The emitter of this second emitter follower transistorT2 is connected to the terminal A of analogue-to-digital converter 9. Switch 11 is formed from two transistors T3 and T4 of like conductivity type (i.e. both npn) with their main current paths (emitter-collector) connected back to back, transistor T3 being reversed with respect to transistor T4. These main current paths are connected between the emitter of transistor T1 and the upper electrode of capacitor 12 whose lower electrode is connected to terminal 39. The base electrodes of transistors T3 and T4 are connected through a terminal 40 which receives from the sync. separator and generator stage the pulse necessary to render these transistors conducting at the appropriate times when the zero-level of chrominance reference is present in the incoming video signal.Switch 14 is formed in a similar way to switch 11 from two transistors T5 and T6 connected between the emitter of transistor T1 and the upper electrode of capacitor 1 5 whose lower electrode is also connected to terminal 39. The base electrodes of transistor T5 and T6 are connected through a terminal 41 to the generator stage and periodically receives the pulse necessary to render these transistors conducting at the appropriate times when the black level reference is present in the incoming video signal.

The junction of switch 11 and capacitor 12 is connected to a level shift stage comprising a transistor T7 and emitter resistor R3 connected as shown to a current source 42 whilst the junction of switch 14 and capacitor 15 is simiiarly connected to a corresponding level shift stage comprising transistorT8 and emitter resistor R5 also connected as shown to a further current source 43. the base of a transistor T9 is connected to the junction of resistor R3 with current source 42 whilst the base of a further transistor T10 is connected to the junction of resistor R5 with current source 43, the collectors of these transistors being connected to the terminal 38 through respective resistors R7 and R8.The emitters of transistors T9 and Ti 0 are interconnected through two resistors R9 and R10 their junction being connected through a current source comprising a transistor Tri 1 and its emitter resistor R 1 to the terminal 39.

As previously explained the periodic conduction of switches ii and 14 applies the appropriate reference level to the appropriate capacitors 12 and 1 5 which store these levels and apply them through their associated emitter follower stage which acts as a buffer to the transistors T9 and T10 which form a differential amplifier and performs the combined functions of the difference stage 1 8 and the amplifier stage 1 9. The change of gain of the amplifier is achieved by changing the current flowing rh rough the collector resistors R7 and R8. To this end the junction of the collector of transistor T9 and resistor R7 is connected to one terminal of a current source 44 and to the collector of a transistor T12, the other terminal of current source 44 being connected to terminal 39.The junction between the collector of transistor T10 and resistors R8 is connected to the collector of a transistor T1 3, transistors T12 and T1 3 forming a long tailed pair whose commoned emitters are connected to one terminal of a current source 45 whose other terminal is connected to terminal 39.

The bases of transistors T1 2 and T13 are respectively connected to terminals 46 and 47 which receive a control signal from the generator stage such that transistor T1 2 conducts during the time of a line period occupied by the compressed chrominance component whilst transistors T13 conducts during the remaining times during each line period.

Resistors R7 and R8 each convey a current component determined by the relative conduction of transistors T9 and T10 due to the difference in the reference levels applied to these transistors from capacitors 12 and 1 5. With transistor T1 3 conducting and transistor T12 non-conducting resistor R7 additionally conveys a current component determined by current source 44 whilst resistor R8 additionally conveys a current component determined by current source 45.

During those periods during which transistor T1 2 conducts and transistorT13 is non-conducting the additional current conveyed by resistor R7 is determined by current sources 44 and 45 whilst the current through resistor R 8 is solely determined by the degree of conduction of transistor T1 0. The different magnitudes in current present through resistors R7 and R8 during the different periods changes the voltage drop across these resistors in the presence of the compressed chrominance component compared with other times to also change the voltage difference present between the junction of resistor R7 with transistor T9 and the junction of resistor R8 with transistor T10 which forms the amplifier output.In this way the required change in gain is achieved such that for the applied difference in reference levels (0.5 volts) the amplifier output alternates between 1.0 volts and 1.3 volts. The currents supplied by the sources 44 and 45 may be equal to each other and may also be determined by the applied reference levels to compensate for component spreads and ensure that the reference voltages applied to terminals R' and R" of converter 9 follow the maximum amplitude for the chrominance and luminance components.

The voltages at the above mentioned junctions are applied to respective emitter follower circuits comprising respective transistors T14, T15 and associated emitter resistors R12, R13 connected as shown and which are respectively connected to the terminals R' and R" of converter 9.

Between the collectors of transistors T9 and T10 are serially connected two resistors R14 and R1 5 whose junction provides the common mode voltage which is connected to the non-inverting (+) input of the differential amplifier 37 the inverting (-) input of which is connected to the emitter of transistor T7 and receives the zerolevel of chrominance reference. The output of the differential amplifier 37 is applied to the base of the current source transistor Tri 1. In the absence of this portion of the circuit the difference output voltage for the converter would be assymetric and its d.c. level would not be correct in relation to the applied reference levels when these follow the energy dispersal waveform. The differential amplifier 37 produces an output dependent upon the difference between the common mode voltage and the zero-level of chrominance reference to control the current produced by the transistor T1 1. An increase in the output voltage from differential amplifier 37 will produce an increase in the current supplied by transistor T1 1 which in turn will produce a decrease in the common mode voltage.

Although in Figure 7 the current source 44 is shown connected directly to transistor T9 it may be so connected through two parallel transistors switched in the same way as transistors T1 2 and T1 3 to ensure that when current sources 44 and 45 are formed by transistors they operate on the same portion of their IJVce characteristic.

Claims (9)

1. A television receiver for a time division multiplexed television signal discrete lines of which sequentially contain a time compressed chrominance component and a time compressed luminance component, the maximum amplitude of the chrominance component being greater than the maximum amplitude of the luminance component, each line also containing a first and a second reference level outside the periods occupied by the chrominance and luminance components, said receiver comprising demodulating means for producing said signal from a received television transmission, means for applying said demodulated signal to an analogue signal input of an analogue-to-digital converter for producing digital signals from the analogue chrominance and luminance components applied thereto and means for applying a reference to a reference input of said analogue-to-digital converter, characterised in that the demodulated signal is additionally applied to sampling means for sampling the respective values of said first and second reference levels during their occurrence and storing these values, means for producing the difference between the stored first and second reference levels and subjecting this difference to amplification the degree of which has a first value during periods of the compressed chrominance component and a second value which is less than said first value during periods of the compressed luminance component, means for applying the resulting amplified difference as the reference to said analogue-to-digital converter, the values of amplification being such that the applied reference has a first value during periods of the compressed chrominance component and a second value during periods of the compressed luminance component which values are proportional or correspond to the respective maximum amplitudes of the chrominance and luminance components as applied to said analogue-to-digital converter.

2. A receiver as claimed in Claim 1 characterised in that said means for producing said difference and for amplifying the difference comprises a differential amplifier having first and second current paths from which the output is derived, the current through each path comprising a first component determined by the difference between said first and second reference levels and a second component whose magnitude changes such that it has a first value during periods of the compressed chrominance component and a second value during periods of the compressed luminance component.

3. A receiver as claimed in Claim 2, characterised in that said second current component has the given value in each current path during periods of the compressed luminance component and is zero in one current path and twice the said given value in the other current path during periods of the compressed chrominance component.

4. A receiver as claimed in Claim 3, characterised in that said given value is dependent upon the difference between said first and second reference levels.

5. A receiver as claimed in Claim 2, 3 or 4, characterised in that said differential amplifier comprises first and second transistors the collector circuits of which respectively form said first and second current paths, the collector circuits of said first and second transistors being additionally connected to respective first and second current sources during periods of the compressed iuminance component whilst the collector circuit of one of said transistors is connected to both said first and second current sources during periods of the compressed chrominance component.

6. A receiver as claimed in any of the preceding Claims, in which said demodulated signal is modulated at a frequency corresponding to the frame frequency as a result of energy dispersal, characterised in that the reference as applied to said analogue-to-digital converter is subjected to a corresponding frame frequency modulation to compensate for changes in level of the demodulated signal so applied to the analogue input of said converter.

7. A receiver as claimed in Claim 6, characterised in that the common mode voltage of the amplified difference is compared with a corresponding one of said reference levels to provide a control for the current flowing in a stage providing said amplification.

8. A receiver as claimed in Claim 7, when dependent upon Claim 5, characterised in that said common mode voltage is derived from the junction of first and second equal value resistors connected between the collector circuits of said first and second transistors, said common mode voltage and the said corresponding one reference level being applied to a differential amplifier whose output controls the conduction of a further transistor forming a current source in the emitter circuits of said first and second transistors.

9. A television receiver substantially as herein described with reference to the accompanying drawings.