GB2118795A - A timing pulse generator and a dynamic memory using the generator - Google Patents

Abstract

A timing pulse generator includes a bootstrap capacitor (CB). This capacitor having been brought into a discharged state in advance in charged up when one terminal is fed with an input pulse ( phi IN) through a transmission gate MOSFET (Q5). A boosting pulse to be applied to the other terminal of the capacitor is generated at a suitable timing to generate a boosted voltage. A voltage detector including MOSFETs (Q6- Q10) is provided for detecting the charging voltage level of the capacitor. The timing at which the boosting pulse is generated is controlled by the voltage detector, thereby minimising the effect of input pulse level, temperature and other changes in component characteristics on the timing of the output pulse, ensuring reliable operation and minimising switching time and heavy current consumption resulting therefrom. <IMAGE>

Description

SPECIFICATION A timing pulse generator and a dynamic memory using the generator The present invention relates to a timing pulse generator, which is constructed of insulated gate type field effect transistors (which will hereinafter be referred to as "IGFET" or "MOSFET"), and a dynamic memory using the timing pulse generator.

One known type of timing pulse generator is shown in Figure 1 of the accompanying drawings.

The timing pulse generator shown in Figure 1 is constructed as follows.

A MOSFET Q, is an element, which constitutes a a bootstrap circuit together with a MOSFET Q2 and a bootstrap capacitor #CBT and has a gate which is to be fed with an input pulse ~IN through a transmission gate MOSFET Q5. The bootstrap capacitor CB is connected between the gate and source of the MOSFET Q,. The MOSFET Q2 is connected between the source of the MOSFET Q, and the earth of the timing pulse generator.

Output MOSFETs Q3 and Q4 are elements which constitute a push-pull output circuit. The output MOSFETs Q3 and Q4 are connected in series between a power source terminal Vcc and earth and have their respective gates connected in common with the gates of the MOSFETs Q, and 02.

TheMOSFETsQ2,Q4 and Q5 have their respective operations controlled by a delay circuit, which is constituted by MOSFETs Q11 to O,,, so as to retain the charge-up time of the bootstrap capacitor CB. The power source terminal side MOSFET Q2 having its gate fed with the input pulse ~IN and the earthed terminal side MOSFET Qz3 having its gate fed with a precharge (or reset) pulse} are connected in series between the power source terminal and earth.The earth side MOSFET Q,5 having its gate fed with a signal at the junction N2 between the series MOSFETs Qr2 and 013 and the power source terminal side MOSFET Q,4 having its gate fed with the precharge pulsed are connected in series with each other. A delay signal to be generated at the common node N3 of the series MOSFETs Qq4 and Q,5 is transmitted firstly to the gates of the MOSFETs Q2 and Q4 and secondly to the gate of the MOSFET Q5 through the cut MOSFET Q11 which has its gate fed with the power source voltage Vcc.

The timing pulse generator thus constructed has its delay time (i.e. the charge-up time of the capacitor CB) fixed in one-to-one relationship by the MOSFETs Q.2, Q15 and so on and has the following defect.

First, in the case where the rising rate of the charge voltage at the bootstrap capacitor CB to be charged up through the MOSFET Q5 is high as is indicated by curve A in Figure 2 of the accompanying drawings, the current consumption is increase, and the low level of an output pulse ~OUT is shifted to a higher side so that a low level margin cannot be retained. On the other hand, in the case where the rise of the charge voltage at a node N, is low as is indicated by curve B in Figure 2, the rise of the output pulse ~OUT is also delayed.

More specifically, the nodes N2 and N3, which have been respectively precharged to the low and high levels through the MOSFETs Q13 and Q14 having their gates fed with the precharge pulses, are made to respectively have the high and low levels in response to the fact that the input pulse ~IN takes the high level. The delay time from the instant when the input pulse ~IN is made to have the high level to the instant when the node N3 is made to have the low level is determined by the on-resistance of the MOSFET Q12 a capacitance such as a parasitic capacitance (not shown) coupled to the node N2, the on-resistance of the MOSFET Q,5, a capacitance such as a parasitic capacitance (not shown) coupled to the node N 3.

In the case where the rising rate of the input pulse ~IN is high, the charge voltage of the node N1 is increased at a high rate. On the other hand, the node N, is made to have the low level after a predetermined delay time. As a result, the time period from the instant when the node N1 is made to have a sufficiently high level to the instant when the node N3 is made to have the low level is elongated.As a result, the time periods required for simultaneously rendering the MOSFETs Q, and Q2 conducting and for simultaneously rendering the MOSFETs Q3 and Q4 conducting are respectively elongated, so that the through currents to flow through the MOSFETs Q, and Q and the MOSFETs Q3 and Q4 are increased. On the other hand, since the output MOSFET 03 is rendered sufficiently conducting at an excessively early time in response to the potential of the node N1, the level of the output pulse ~OUT is slightly raised before it is changed to the high level. In other words, the low level of the output pulse ~OUT is made to have an undesired level.

On the contrary, in the case where the rising rate of the charge voltage at the node N1 is low in response to the fact that the rising rate of the input pulse ~IN is low, the node N3 is made to have the low level before the charge voltage at the node N1 is made to have the sufficiently high level. The MOSFET Q5 for applying the charge voltage to the bootstrap capacitor C5 is rendered nonconductive in response to the result that the node N3 is made to have the low level. As a result, the charge voltage of the bootstrap capacitor C5 is not made to have the sufficiently high level. Since the charge voltage of the bootstrap capacitor C5 does not have a sufficient level, the output MOSFET Q3 is not rendered sufficiently conducting. As a result, the rising rate of the output pulse ~OUT is lowered.

A similar undesired operation of the timing pulse generator is caused even if the rising rate of the input pulse ~IN is constant, because the rising rate and delay time of the node N1 are dispersed in response to the dispersion of the characteristics of the M0SFETs05, Q12 and 015.

Secondly, in the case where the delay time from the input pulse ~IN to the output pulse cut is to be set at a large value, it is remarkably difficult to make the charge time of the node N, and the delay time of the node N3 coincident because they are highly influenced by the dispersion of the element characteristics.

Thirdly, in the case where the rising rate of the input pulse ~IN is changed, there arise an increase in the current consumption caused by the first reason, the short of the low-level margin, and the shortage of the driving capacity of the load (not shown) by the output pulse so that the desired stable operations cannot be expected.

It is an object of the present invention to overcome the above referred to disadvantages by providing a timing pulse generator which has its operating status freed from the influences of the dispersion and fluctuation of the rise of an input pulse.

The present invention will now be described in greater detail by way of example with reference to the remaining figures of the accompanying drawings, wherein.~ Figure 3 is a circuit diagram of one preferred form of a timing pulse generator; Figure 4 is a waveform diagram for explaining the operations of the timing pulse generator shown in Figure 3; Figure 5 is a block diagram showing a D-RAM which is equipped with the timing pulse generator shown in Figure 3; Figures 6 and 7 are waveform diagrams illustrating the operations of the D-RAM shown in Figure 5; Figure 8 is a circuit diagram showing an essential portion of the D-RAM shown in Figure 5; and Figure 9 is a waveform diagram for explaining the operations of the same.

Referring to the timing pulse generator shown in Figure 3, comprises MOSFETs Q, to Q0. It includes a voltage detector which is constructed of the MOSFETs Q6 to Q10, which is attached to the bootstrap output circuit which is shown in Figure 1 to be composed of the MOSFETs Q, to Q5 and the boostrap capacitor CB. The voltage detector takes the place of the delay circuit shown in Figure 1. In the bootstrap output circuit, the MOSFETs Q, and Q2 substantially constitute the boostrap capacitor driving circuit. in the timing pulse generator shown in Figure 3, the voltage detector and the bootstrap capacitor driving circuit may be construed to substantially constitute one driver.

In the voltage detector, the earth potential side MOSFET Q7 is connected in series with the power source terminal side MOSFET 0, which has its gate fed with the gate voltage applied to the MOSFET Q,. In other words, the MOSFET Q7 is connected between the source of the MOSFET Q6 and the earth point of the voltage detector. The earth potential side MOSFET Q9 has its gate and drain cross-connected with those of the MOSFET Q7.The power source terminal side MOSFET $ its connected in series with the MOSFET Q and has its gate fed with a precharge pulses.The MOSFET #1O is connected in parallel phh the MOSFET Q1O~S connected in parallel with the precharge pulse ~. The drain output signal of the MOSFET Q9 is fed firstly to the gates of the MOSFETs O2 and Q4 and secondly to the gate of the MOSFET Q5 through the cut MOSFET Q11 which has its gate fed with the power source voltage Voc.

The MOSFET so far described are of the Nchannel type, although this is not an essential requirement. The MOSFETs and the bootstrap capacitor CB are formed on a semiconductor substrate in accordance with the well-known MOS integrated circuit technique which is made of N-type single-crystalline silicon. The bootstrap capacitor CB is constructed of the MOS capacitor which has a construction similar to that of the MOSFET. The capacitor CB has its gate electrode coupled to the node N, and its source and drain electrodes connected with the common node of the source electrode of the MOSFET Q, and the drain electrode of the MOSFET Q2 The operation of the timing pulse generator shown in Fig. 3 will now be described with reference to the waveform diagrams shown in Fig.

4. It should be noted that the precharge pulse) and the input pulse ~IN to be applied to the timing pulse generator shown in Fig. 3 are supplied from a suitable circuit (not shown).

The precharge pulses is preset at a high level approximately close to the power source voltage Vcc, as illustrated in Fig. 4, and falls to a low level approximately zero volts before the input pulse ~IN to be delayed is received, i.e. before the input pulse ~IN is raised to the high level. Moreover, the precharge pulsed is raised to the high level in synchronism with the fact that the input pulse ~IN is returned to the low level.

When the precharge pulsed is at the high level, MOSFETs Q8 and 0,, are accordingly rendered conductive. When the MOSFETs QB and Q10 become conductive, the MOSFET Q7 is rendered conductive whereas the MOSFET Q, is rendered non-conductive.At this time, since the MOSFET Q, is non-conductive whereas the MOSFET O, is conductive, the MOSFETs Q2 Q4 and Q5 have their gates precharged to the high level, which is approximately equal to the power source voltage of Vcc#Vm (VTH being the threshold voltage of the MOSFET), through the MOSFET Q8. As a result, the MOSFETs Q2 Q4 and Q5 are rendered conductive. The level at the node N, falls to the same level as that of the input pulse ~IN' i.e. the low level because the MOSFET 05 is conductive.

The MOSFETs Q6TQ. and Q3 having their respective gates coupled to the node N, are rendered non-conductive because the node N, is at the low level. The output pulse ~OUT fed from the common node of the source of the output MOSFET Q3 and the drain of the output MOSFET 04 is at the low level because the output MOSFET Q4 is conductive. In this status, at least one of paired MOSFETs, which are connected in series between the power source terminal and the earth terminal, such as the MOSFETs Q3 and Q4 is held in its non-conductive state. As a result, the current consumption of the timing pulse generator in this status is substantially reduced to zero.

Next, the precharging operation is ended as a result that the precharge pulsed is changed to the low level. After that, if the input pulse ~IN rises to the high level, the bootstrap capacitor CB is charged up through the MOSFET 05. The potential at the node n, is raised in accordance with the charge of the bootstrap capacitor CB. Here, the MOSFET Q5 having been rendered conductive by the precharge constitutes a MOS capacitor which substantially acts as the bootstrap capacitor. The gate electrode of the MOSFET 05 is construed as one electrode of the MOS capacitor, whereas the channel induced below the gate electrode of the MOSFET 05 is construed as the other electrode of the MOS capacitor.This MOS capacitor, which is substantially constructed of the MOSFET Q, is charged up at the precharge, i.e., when the precharge pulse} is at the high level. The voltage is the channel of the conducting MOSFET 05 is raised in accordance with the rise of the input pulse ~IN to the high level.During the precharge period, the MOS capacitor between the gate ,electrode and channel of the MOSFET Q5 has been charged up so that the gate voltage of the MOSFET 05 is raised in response to the voltage rise of the input pulse ~IN In other words, the gate potential of the MOSFET Q5, which has been raised to the high level by the precharge, is further raised to such a high level by the so-called "selfbootstrap action" as exceeds the power source voltage level. The MOSFET Q5 begins to exhibit the satisfactory on-characteristics when its gate potential is sufficiently raised. As a result, the input pulse ~IN is transmitted to the node N, without having its level substantially lost.

Immediately after the input pulse ~IN is raised to the high level, the node N3 is still left at the high level. The electrode of the cut MOSFET 011, which is coupled to the gate of the MOSFET Q5, acts as the drain electrode if it is fed with the bootstrap voltage through the MOSFET 05. At this time, the voltage to be applied between the gate electrode of the cut MOSFETO11 and the electrode acting substantially as the source electrode (i.e., the electrode coupled to the node N3) is sufficiently low because the node N3 is at the high level. As a result the cut MOSFET 011 is automatically rendered non-conductive because the bootstrap voltage generated by the MOSFET Q5 rises to a level higher than the power source voltage.Thus, the bootstrap voltage is prevented from leaking.

The MOSFET Q6 which has been rendered non-conductive during the precharge period, is rendered conducting to have its conductance increased in accordance with the rise of the potential of the node N,. The potential at the node N2 rises, as illustrated in Fig. 4, in accordance with the ratio of the conductances of the MOSFETs Q6 and Q7 now being conductive.

If the voltage at the node N2 exceeds the threshold voltage VTH of the MOSFET Q9 in accordance with the potential rise of the node N,, the MOSFET 09 is accordingly switched from its non-conductive state to its conductive state. At this instant, the conductive state of the MOSFET Q7 and Q9~S is abruptly inverted by the action of the positive feedback due to action of the MOSFETs Q7 and Q9 which are cross-connected.

Accordingly, the MOSFET 05 is switched from "off" to "on" whereas the MOSFET 07 is switched from "on" to "off".

The node N3 is changed from the precharge level, i.e., the high level to the low level as a result that the MOSFET 09 is rendered conductive. The MOSFETs Q2 and Q4 are rendered non-conductive as a result that the node N3 is at the low level..

The cut MOSFET 011 is rendered conductive when the node N3 is at the low level, because the voltage to be applied between the gate thereof and the electrode acting substantially as the source electrode is accordingly raised. The MOSFET 05 is rendered non-conductive because its gate potential is charged to the low level through the cut MOSFET Q" in the conducting state.

The common node of the MOSFETs Q, and Q2 is raised to the high level as a result that the MOSFET 03 is rendered non-conductive. Since the bootstrap capacitor Orb is precharged, the potential at the commonly connected gates of the MOSFETs Q1 and Q3, i.e., the potential at the node N, is raised to a level higher than the power source voltage Vcc in accordance with the rise of the potential at the common node to the high level. The MOSFET Q, is rendered non-conductive when the voltage of the node N, is raised. As a result, the charge for maintaining the bootstrapped voltage of the node N, is prevented from leaking to the side of the input pulse ~IN through the MOSFET Q.

The output MOSFET 03 is designed to have a sufficiently low on-resistance when the potential of the node N, is sufficiently raised by the bootstrapping operation. As a result, the output pulse ()ouT rises at a high rate to the high level even if the load capacitor (not shown) is coupled to the common node of the output MOSFETs Q3 and Q4, i.e., the output terminal.

The level shift voltage, which has its level shifted to a value according to the conductance ratio of the MOSFETs Q6 and Q7 with respect to the charge-up voltage applied to the bootstrap capacitor CB is generated at the common node of those MOSFETs. This level shift voltage has its magnitude compared by the MOSFET 06. In this case, the threshold voltage of the MOSFET 09 is construed as the reference voltage for the voltage comparison. If the potential at the node N, is raised to a predetermined value, as has been described above, the "on" and "off" states of the MOSFETs Q7 and Q are accordingly inverted in an abrupt manner. Accordingly, the bootstrap voltage by the bootstrap capacitor CB is applied to the node N,.

That value of the charge-up voltage of the bootstrap capacitor CBI which is to be detected, can be set at a proper value by suitably setting the circuit constants which are determined by those MOSFETs. As a result, the bootstrap capacitor CB is enabled to start the bootstrap operation at the correct time when it has been charged up to the proper charge-up voltage. Even if the charging rate of the bootstrap capacitor C6 varies, due to for example changes in the changing rate of the input pulse ~IN' the MOSFETs Q2 and Q4 are switched from their conductive state to their nonconductive states at the correct time in spite of any fluctuations. As a result, there is no substantial current loss.Moreover, it is possible to increase the low-level margin and to ensure a sufficient driving capacity.

The generation of the output pulse ~OUT after a long delay time relative to the input pulse ~IN can be realized with remarkable ease by reducing the conductance of the MOSFET Q5 or by delaying the input pulse ~IN itself.

Since the operating time of the bootstrap circuit is controlled by the monitor result of the charge-up voltage at the bootstrap capacitor CBT the influences from the dispersions of the elements are substantially reduced so that a large degree of freedom of the design can be enjoyed.

The timing pulse generator described above can be used with a dynamic type RAM (which will hereinafter be referred to as "D-RAM") as will now be described in greater detail with reference to Fig. 5.

Referring to Fig. 5, each of the circuit blocks surrounded by broken lines is formed as an integrated circuit (which will hereinafter be referred to as "IC") on one semiconductor substrate (not shown). Each circuit of the IC is constructed of a dynamic circuit. The IC adopts an address multiplex system so as to reduce the number of the external terminals thereof. The IC is rendered operative by having its power source terminal and earth terminal fed with the power source voltage Vcc, which is generated by a power source unit (not shown), and an earth voltage Vss.The external terminals of the IC are fed with the row address strobe signals RAS, colum address strobe signal CAS, write enable signal WE row address signals A, to Aj, column address signals Aj+, to Aj, and input data signal Din which are generated by an electronic unit such as a CPU (not shown). The external terminal of the IC generates a data signal DOUBT which is to be fed to an electronic unit such as the CPU.

In the IC, the block surrounded by doubledotted chain lines is the timing pulse generator which is constructed of a circuit for generating a signal for controlling the operations of the respective circuits of the D-RAM.

Figs. 6 and 7 are waveform diagrams illustrating the operations of the read cycle and write cycle of the D-RAM shown in Fig. 5.

The output of the D-RAM will now be described with reference to the block diagram of Fig. 5 and the waveform diagrams of Figs. 6 and 7.

First, the levels of the respective row address signals Ao to Aj are set at such levels as select the row address of a desired memory cell within a memory array (which will hereinafter be referred to as "M-ARY"). Thereafter, the RAS, signal is made the low level. The timing pulse generator (which will hereinafter be referred to as "TGB") provides a control signal ~AR in response to the fall of the RAS signal. When the signal ~AR has been provided, a row address buffer (which will hereinafter be shortly referred to as "ADB") held in the precharged state in advance is brought into the operating state. As a result, the row address signals Ao to Aj are applied to the ADB and latched therein.In response to the row address signals Ao to Aj, the ADB generates internal address signals aO, a, to aj, a; of true and false levels. The reason why the RAS signal is made later than the row address signals Ao to A is so as to reliably supply the ADB with the row address signals Ao to Aj as the row address in the memory array.

Upon the generation of the signal ~AR' the internal address signals aO, a, to a;, aj produced by the ADB are transmitted to a row and column decoder and driver circuit (which will hereinafter be referred to as "RC-DCR"). The RC-DCR ~~ decodes the internal address signals aO, aO, to aj, aj.

Amongst the decoded signals of the RC-DCR, only one to be selected is left at the high level, whereas the others not to be selected are brought to the low level.

Subsequently, a signal ~x which is delayed for a predetermined period of time with respect to the signal ~AR is delivered from the TGB. Upon the generation of the signal ~x, the decoded signals formed by the RC-DCR are transmitted to the row address lines of the memory array M-ARY. The reason why the signal ~x is delayed with respect to the signal ~AR is to operate the RC-DCR after the operation of the ADB has ended. In this way, the row address in the M-ARY is set. That is, one row address line in the M-ARY is selected by onehigh-level signal among the 2'+' output signals of the RC-DCR.

Next, data signals corresponding to the information of "1" or "0" read out from the respective memory cells, which are connected to the selected signal row address line in the M-ARY, are amplified by the sense amplifier (which will hereinafter be referred to as "SA"). The amplifying operation of the SA is started upon the generation of the signal ~PA- At a correct time indicated by waveform E in Fig. 6, the respective levels of the column address signals Aj+ to Aj are set at such levels as select a column address of the desired memory cell.

Thereafter, when the CAS signal has been made the low level so as to provide a signal ~AC from the TGB, the column address signals Aj+, to Aj are applied to the ADB and latched therein. The reason why the CAS signal is made later than the column address signals Aj+, to Aj is in order to reliably supply the ADB with the column address signals as the column address in the memory array.

Upon the generation of the signals ~ACR the ADB transmits internal address signals aj+" aj+, to aj, a corresponding to the column address signals, to the RC-DCR. This RC-DCR generates 2i+' decoded signals by an operation. Amongst the decoded signals, one corresponding to the combination of the internal address signals is brought to the high level. Next, a signal ~y delayed with respect to the signal ~AC is applied to the RC DCR. Upon the generation of the signal ~yt the decoded signals are delivered from the RC-DCR and transmitted to a column switch (which will hereinafter be referred to as "C-SW"). In this way, the column address in the M-ARY is set.That is, one of bit lines in the M-ARY is selected by the C SW.

One memory address in the M-ARY is set by such setting of the row address and the column address.

Next, the read and write operations for the set address will be explained.

A read mode is specified by the high level of the WE signal. This WE signal is made the high level before the CAS signal is made the low level.

Preparations for the read operation are made by bringing the WE signal to the high level.

Accordingly, when the WE signal has been brought to the high level in advance, the read operation gets ready before one address of the M ARY is set by making the CAS signal the low level.

As a result, the period of time for starting the reaa operation can be shortened.

When a signal ~Op which is a CAS-group signal has been provided from the TGB, an output amplifier (although not shown, which is included in the data output buffer (which will hereinafter be referred to as "DOB") is responsively activated.

Information read out from the set address, namely, information supplied through the C-SW is amplified by the activated output amplifier. The amplified information is delivered through the DOB to the data output terminal. Thus, the read operation is effected. When the CAS signal takes the high level, the read operation ends.

A write mode is specified by the low level of the WE signal. A##aI signal~RW is brought to the high level by the WE signal of low level and the CAS signal of low level. The signal ~RW is applied to the data input buffer (which will hereinafter be referred to as "DIB"). This DIB is activated by the signal ~RW of high level, and then transmits write data from the input data (Dln) terminal to the C SW. The write data are transmitted to the set address of the M-ARY through the C-SW. As a result, the write operation is performed.

In the write operation, the DOB is inactivated by being supplied with the inverted signal of the signal ~RW' namely, the signal; of low level.

Thus, the data in the write operation are prevented from being read out.

The respective clock pulses ~xt ~y are formed on the basis of the address strobe signals (e.g., the RAS signal and the CAS signal) in the TGB which receives these address signals as has been previously stated. The clock pulse #RW is formed on the basis of the WE signal and the output signal from the TGB in the read/write clock pulse generator R/W-SG.

Fig. 8 is a circuit diagram showing an essential portion of the D-RAM.

The circuit shown in Fig. 8 is constructed of Nchannel IGFETs (which is the abbreviation of "Insulated-Gate Field Effect Transistor"), which is made of an N-channel MOSFET.

The one-bit M-CEL is composed of an information storing capacitor Cs and an address selecting MOSFET 0M and stores the information "1" or "O" in the form whether the capacitor Cs has a charge or not.

The read operation of the information is conducted by turning on the MOSFET QM to connect the capacitor Cs with a common column data line DL and by subsequently sensing how the potential of the data line DL has changed in accordance with the quantity of the charge stored in the capacitor Cs. If it is assumed that the potential charged in advance in a stray capacitor CO be the power source voltage Vcc, the potential (VDL) of the data line DL, which is determined during the addressing operation, is left at the potential Vcc in the case where the information stored in the capacitor Cs is at "1" (i.e., the potential of the voltage Vcc).In the case the potential at the capacitor Cs is at "O" (i.e., O V), the potential (VDL)'O" at the data line DL is expressed by (C0. VCC CS(VW Vth)}/CO The term Vw designates the gate voltage of the MOSFET 0M' and the term Vth designates the threshold voltage of the MOSFET QM. Moreover, the potential change, which will be imparted to the data line DL in a manner to correspond to the logic "1" or "O", i.e. the signal quantity AV5 to be detected is expressed in the following formed #Vs=(VDL)"1"-1- (VDL)"O =(VW~Vth) ' C#C0.

If Vw=Vcc holds, the signal quantity #Vs is expressed by the following equation: AVs=(VCC~Vth) ' C5/C0.

In the case of a memory matrix of high integration and capacity in which memory cells are small-sized and connected with a common data line, an inequality of Cs Co holds. That is, the ratio Cs/Co has a substantially small value.

Therefore, the signal quantity AV5 becomes a signal of fine level.

A A dummy cell D-CEL is used as a means for providing a reference when such fine signal is to be detected. The D-CEL has the same fabricating conditions and design constants as those of the M-CEL except that a capacitor Cds has a capacitance about one half as large as that of the capacitor Cs. One electrode of the capacitor Cds is charged to earth potential (the other electrode being fixed at Vcc) by the action of a MOSFET QD2 'prior to the access of the D-RAM.Therefore, the signal change AVR which is imparted to the column data line DL by the action of the D-CEL when the D-RAM is accessed, is expressed in similar manner to that of (AV8) of the memory cell by the following equation, wherein: the term Vow designates the gate voltage of a MOSFET QD1; and the term Vth' designates the threshold voltage of the MOSFET QDI AVR=(VDW~Vth) Cds/C0.

If VDW=VCC holds, the signal change AVR is expressed by the following equation: ISVR=(VCC~Vth ) Cds/CO.

Since the capacitor Cds is set to have about one half of the capacitance of the capacitor Cs, the signal change AVR becomes equal to about one half of the signal quantity AV8. Therefore, the information "1" or "0" can be discriminated in dependence upon whether the potential change to be imparted to the data line DL by the memory cell is larger or smaller than that (air) of the dummy cell.

A sense amplifier SA, enlarges such a difference in the potential changes as takes place during the addressing operation to the sense period which is determined by a timing signal (i.e., the sense amplifier control signal). This operation will hereinafter be described in greater detail. The sense amplifier SA, has input and output nodes which are coupled to a pair of complementary data lines DL,~, and DL,~, arranged in parallel. The numbers of the memory cells to be coupled to the data lines DL,~, and DL1#1 are made identical so as to enhance the data detecting precision, and one dummy cell is coupled to each of the data lines DL,~, and DL,~,. Each memory cell is coupled between one word line WL and one of the complementary data lines.When the memory cell coupled to one of the complementary data lines DL,~, and DL,~, is selected, one of a pair of dummy word lines DWL,Oa and DWL,, is selected so that the dummy cell coupled to the other data line may be selected.

An undesired coupling capacitor such as a parasitic capacitor (not shown) exists at the intersection between each word line and each data line. As a result, if the potential of a word line is changed, the potential change which is construed as noises is imparted to each data line through the undesired coupling capacitor. In the case of the memory array of folded bit line type, as shown in Fig. 8, each word line WL intersects any of the couples of the data lines. As a result, the noise having a substantially equal level as that of the noises, which will be transmitted to one data line by the potential change of the word line WL, are also transmitted to the data line which is coupled with the former data line.Since the differential sense amplifier is substantially insensitive to the common node noises, the fine signal which is fed to the coupled data lines is correctly amplified irrespective of the presence of the noises.

The sense amplifier SA, has a pair of crosscoupled MOSFETs Osa and Q59 so that it differentially amplifies the fine signal by the positive feedback operations of these MOSFETs.

The positive feedback operations are started simultaneously with the start of the conduction of a a MOSFET Qs10 by the timing signal (i.e., the sense amplifier control signal) ~PA As a result of the operations of the sense amplifier SA1, the data line potential (VH), which has been set at the high level on the basis of the potential difference imparted in advance during the addressing operation to the paired data lines, falls at a low rate, whereas the low data line potential (V,) falls at a high rate. As a result, the potentials of the paired data lines fall whilst the difference between them increases. When the low data line potential VL reaches the threshold voltage Vth of the cross-coupled MOSFET, the positive feedback operation substantially ends.The high data line potential VH is left at such a potential as is lower than Vcc and higher than Vth. The low data line potential VL finaíly reaches 0 V.

Upon the addressing operation, the stored information of the memory cell, which as once been broken, is restored (or rewritten) as a result that it is written as it is in the memory cell in which the potential VH or VL provided by that sensing operation is selected.

If the high potential VH falls more than a predetermined level with respect to the level Vcc, there arises an erroneous operation by which the potential VH is read out as the logic "0" after the repetitions of the reading and rewriting operations. An active restore circuit AR, is provided to prevent that erroneous operation. This circuit AR, has a function to boost only the high potential VH to the potential Vcc without imparting any influence to the low potential V.

The sense amplifier SA1, also includes MIS type variable capacitance elements CB1, and CB12 which have their electrostatic capacitances changed in accordance with the voltage applied to a terminal which is located at the lefthand side of the drawing. It will be appreciated that these variable capacitance elements theoretically provide capacitors for a high voltage with reference to the threshold voltage Vth but not for a low voltage.

When MOSFETs Q54 and Q55 are rendered conducting by a timing signal (i.e. an active restore control signal ~rgx the variable capacitor element C8 belonging to the data line at the potential VH is charged up. When a timing signal (i.e., an active restore control signal) ~,5 takes the high level, the gate potential of a MOSFET Qs6 or Q57 belonging to that data line becomes sufficiently higher than Vcc. As a result the MOSFET Qs6 or Q57 has a sufficiently high conductance, and the potential VH is restored to the level Vcc. In order to reduce the power losses at the MOSFETs 056 and Q57 in this case, the respective threshold voltages Vth are so designed as to be lower than those MOSFETs not asterisked.

The sequential operations of the D-RAM transistor circuit thus far described will be explained with reference to the waveform diagram of Fig. 9.

If the signal ~PC has a high level such that it exceeds the level Vcc, MOSFETs Qs2 and Qs3 are accordingly rendered conducting so that the stray capacitor CO of the coupled complementary data lines DL,~, and DL,~, is precharged to the level Vcc. Since a MOSFET Qs1 is simultaneously rendered conducting at this time, the coupled complementary data lines DL,~, and DL,~, are short-circuited, even if an imbalance takes place in the precharge by the MOSFET 082 and Q53 SO that they are set under the condition of the same potential.The MOSFETs Q5, to Q53 are so constructed that they have lower threshold voltages than the MOSFET asterisked, so that no voltage loss may be caused between their respective sources and drains.

The MOSFET QD2 at each dummy cell is rendered conducting at this time by a timing signal (i.e., a discharge control signal) ~dCs As a result, the dummy cell D-CEL is similarly reset to a predetermined state.

The row address signals Ao to A,, which are fed in synchronism with the timing signal (i.e., the address buffer control signal) ~AR from the address buffer ADB, are decoded by the decoder RC-DCR and are fed to the memory cell M-CEL and the dummy cell D-CEL simultaneously with the rise of the word line control signal (nix.

As a result, a voltage difference of AV#2 is established between the coupled complementary data lines DL,~1 and DL1#1, as has been described hereinbefore, on the basis of the stored content of the memory cell.

When the MOSFET 0,,, begins to become conductive by the timing signal (i.e., the sense amplifier control signal) ~PAT the sense amplifier SA1 starts the positive feedback operation and amplifies the detected signal of AV#2 which has been fed during the addressing operation to the complementary data lines DL1~1 and DL1~,.

After the amplifying operation has substantially ended, the timing signal (i.e., the active restore control signal) ~rs is generated. When this timing signal ~rs is generated, the active restore circuit AR, is synchronously operated so that the logical level "1" of one of the complementary data lines DL,~, and DL1~1 restores the level Vcc.

The column address signals A,+1 to Aj, which have been fed from the address buffer ADB in synchronism with the timing signal (i.e., the address buffer control signal) ~ACT are decoded by the decoder RC-DCR. Next, the decoded signals of the RC-DCR are fed to the column switch C-SW, when the timing signal (i.e., the column switch control signal) ~y is generated. As a result, the stored information of the memory cell M-CEL belonging to the column address selected is transmitted through the column switch C-SW, to common data lines CDL, and CDL,.

Next, a main amplifier/data output buffer OASDOB is operated as a result that the timing signal (i.e., the data output buffer and main amplifier control signal) ~Op is generated. As a result, the stored information read out from the selected memory cell is fed out to the output terminal Dout of the chip. The OAi-2DOB is made inoperative during the writing operation by the timing signal (i.e., the data output buffer control signal) ~RW The precharging, addressing and sensing operations are absolutely identical to those of the above described reading operation.First of all, the stored information of the memory cell, which should be intrinsically written in, is read out at the coupled complementary data lines DL,~, and DL1~l irrespective of the logical value of the input write information Dine The read information at this time is ignored by the writing operation which will be described hereinafter.

The selection of the row address is substantially conducted by the operations thus far described.

When the timing signal (i.e., the column switch control signal) ~y is generated as in the reading operation, the coupled data lines DL,~, and DL,~,, which belong to the column selected in synchronism with that generation, are coupled to the common data lines CDL, and CDL, through the column switch C-SW,.

Next, when the timing signal (i.e., the data input buffer control signal) ~RW is generated, complementary write input signals din and d; which are fed from the data input buffer DIB in synchronism with that generation, are written in the memory cell M-CEL through the column switch C-SW,. At this time, the sense amplifier SA, also operates, but the output impedance of the data input buffer DIB is low.As a result, the information to appear at the coupled column data lines DL,~, and DL,~, is determined by the information of the input D;n A refreshing operation is conducted by once reading out the information, which is stored in the memory cell M-CEL but is being lost, to the common column data line DL and by writing again the read-out information in the memory cell M-CEL after it has been made at such a level as has been restored by the sense amplifier SA, and the active restore circuit AR,. Therefore, the refreshing operation is similar to that operation during the row addressing and sensing period, which has been described in connection with the reading operation. In this case, however, the operation of the column switch C-SW, is not required. As a result, the refreshing operation is performed simultaneously for all the columns and in the order of the respective rows while the column switch C-SW, is held in its inoperative state.

The timing pulse generators having the construction shown in Fig. 3 are used in the TGB shown in Fig. 5 so that the timing signals ~ARI ~XI ~PAT ~Y and so on of the D-RAM may be generated.

For example, a timing pulse generator (not shown) which will hereinafter be referred to as "~AR-GEN" is made operative to generate the timing signal ~AR for controlling the address buffer ADB, and has a construction similar to that of the circuit shown in Fig. 3. The precharge pulse and input pulse, which is required by the ~AR-GEN, are generated by a suitable input buffer (not shown) which is located in the TGB and which is to be fed with the RAS signal through an external terminal.

The precharge pulse required by the ~AR-GEN is in phase with the RAS signal, whereas the input pulse is in phase opposition with the RAS signal.

As a result, the ~AR-GEN is maintained in its precharge state, when the RAS signal is not generated or made at the high level, but is rendered inoperative when the RAS signal is made at the low level. In this case, the delay time period required from the instant when the RAS is generated to the instant when the timing signal ~AR is generated is set at a suitable value by suitably setting the conductance characteristics of the MOSFET in the #AR#GEN, which corresponds to the MOSFET Q5 shown in Fig. 3. In other words, the delay time required is set at the suitable value by suitably setting the size (e.g., the channel width W/the channel length L) of the MOSFET corresponding to the MOSFET 05.

Likewise, the timing pulse generator (not shown) which will hereinafter be referred to as "(iIx-GEN", is made operative to generate the timing signal ~x for controlling the decoder RC DCR, and has a construction similar to that of the circuit shown in Fig. 3. The generator~x-GEN is to be fed with the precharge pulse and input pulse which are identical to those fed to the ~AR GEN.

The delay time to be set by the ~X-GEN is set by suitably setting the conductance characteristics of the MOSFET, which corresponds to the MOSFET Q5 of the circuit of Fig. 3, in similar manner to that of the ~AR-GEN.

Incidentally, in the case where a relatively long delay time can be set from the instant when the timing signal ~AR is generated to the instant when the timing signal ~x is generated, namely, in the case where delay time to be set is longer than the minimum delay time that can be substantially set by the ~X-GEN, the timing signal ~AR may be applied as the input signal to the ~X-GEN.

Thus, the plural timing signals having different timings can be generated by providing in parallel a plurality of circuits having a construction similar to that of the circuit shown in Fig. 3 and/or by providing those circuits in series.

The delay time of the timing pulse generator shown in Fig. 3 can have its value easily determined in accordance with the conductance characteristics of the MOSFET Q5 and by the voltage detecting means consisting of the MOSFETs Q6 to Qg. The delay time can have its value changed with ease merely by changing the conductance characteristics of the MOSFET OB As a result, the design of the D-RAM is facilitated if the timing pulse generators shown in Fig. 3 are used. On the contrary, the delay time of the circuit shown in Fig. 1 is influenced, as is apparent from the above description, not only by the MOSFET Q5 but also by the MOSFETs 012 and Ois. This makes it relatively difficult to design the MOSFETs for changing the delay time.As a result, the design of the D-RAM is complicated if the known timing pulse generator shown in Fig. 1 is used.

In the D-RAM, some timing signals are required to have especially precise timings. Amongst these signals, the timing signal ~PA has to rise precisely in synchronism with the selection ending timing of the memory cell. If the timing signal ~PA is generated at an excessively early timing, more specifically, the sense amplifier SA, accordingly starts its amplifying operation notwithstanding that the coupled data lines are not fed with the signal AV8 of sufficient level yet. As a result, the sense amplifier SA, is liable to perform an erroneous operation. On the other hand, the output timing of the timing signal ~PA is set at a sufficient late value, an erroneous operation of the sense amplifier SA, can be prevented.In this case, however, the access time of the D-RAM is limited by the late start of the sense amplifier SA,.

In order to prevent the erroneous operation of the circuit and to shorten the access time, it is necessary to precisely set the timing signal ~PAT as has been described above.

Moreover, the proper output timing of the timing signal ~PA is also influenced by the fluctuations of the circuit characteristics, which are brought about by the dispersion due to manufacturing techniques and fluctuations in the operating temperature of the MOSIC.

For example, word lines WL,~, and WL,~2 shown in the circuit diagram of Fig. 8 are made of a layer of a material having a high melting point such as a conductive polysilicone layer or a molybdenum silicide layer, which is formed simultaneously with the gate of the switch MOSFET QM. Each of these word lines has a not negligible tesistance perse. Moreover, each of the word lines is coupled to a parasitic capacitor which is formed as the gate capacitor of the switch MOSFET QM As a result, each of the word lines substantially constitutes a distribution constant circuit. In other words, each word line has a not negligible delay characteristic. With regard to the two terminals of each word line extending on the semiconductor substrate, the terminal to be fed with the output of the decoder RC-DCR will be referred to as the "near terminal of the word line", whereas the terminal furthest from the decoder RC-DCR will be referred to as the "remote terminal of the word line".

The time period from the instant when the decoded signal is applied to the near terminal of the word line to be selected to the instant when the potential at the remote terminal of that word lines rises to a level higher than the desirable value is influenced by the delay characteristics of the same word line. If the timing signal ~PA is generated at a relatively early timing, it becomes impossible to correctly read out the information of the memory cell which is arranged in the vicinity of the remote terminal of the word line.

In order to make the data read possible irrespective of the delay characteristics of each word line, which are brought about by the dispersion arising from the IC manufacturing techniques employed and by fluctuations of the operating temperature, the delay characteristics of a suitable line are detected. The generation timing of the timing signal ~PA for controlling the sense amplifier SA, is changed in accordance with the value detected.

One embodiment for enabling those operations to be carried out is constructed as follows.

The signal at the remote terminal of the paired dummy word lines, to which the dummy cell is coupled, as shown in Fig. 8, is construed as the input pulse which is to be fed to the pulse generator~pA-GEN (not shown) made to have a construction similar to that of the circuit shown in Fig. 3. In this case, in order to prevent the remote terminals of the paired dummy word lines from being short-circuited and to allow the pulse generator ~pA-GEN to respond to the potential change at the remote terminal of each dummy word line, there is provided a suitable voltage composer.This voltage composer may be constituted by a pair of input MOSFETs, which have sources commonly connected with an output node, gates coupled to the remote terminals of the respectively corresponding dummy word lines, and drains commonly connected with a power source terminal; and a precharge MOSFET which has a drain-source path connected between the output node and earth and a gate fed with a precharge signal which is in phase with the RAS signal.The output of the voltage composer is fed as an input pulse to the pulse generator~pA-GEN. The output of this pulse generator ~pA-GEN is used as the timing signal ~PA This construction makes use of the feature that the paired dummy word lines have the same construction as each word line of the memory array M-ARY shown in Fig. 8 so that they have substantially the same delay characteristics as those of each word line. As a result that the operating level of the input pulse by the pulse generator~pA-GEN is properly set, the timing signal ~PA can be generated simultaneously as the potentials at the remote terminals of the dummy word lines are raised to a proper value.

The simulation of the delay characteristics of each word line can be conducted by providing and making use of an additional dummy word line which is made independent of the paired dummy word lines. In this case, the additional word line is held at the selected level even when either of the paired dummy word lines is selected in response to the same signal as the timing signal ~x, for example. In the case where the additional dummy word line is provided, its remote terminal may be directly coupled to the input of the pulse generator ~pA-GEN.

In accordance with the construction thus far described, the erroneous operation can be prevented because the timing signal ~PA can be reliably generated in synchronism with the selecting ending timing of the memory cell which is located at the remote terminal side of the word line, Moreover, the D-RAM of high-speed operation can be provided because a time margin more than necessary need not be provided for the rise of the timing signal ~PA Still moreover, this timing signal ~PA can be generated in accordance with the fluctuations and dispersion of the word line selecting operations.

The following modifications and additions can be made to the timing pulse generator described above.

The following MOSFETs may be added to the circuit shown in Fig. 3.

In order to shorten the access time of the D RAM, for example, the timing pulse generators are desired to be returned to their precharge states within a relatively short time period when the RAS signal and the CAS signal are not fed to the D-RAM. In the circuit shown in Fig. 3, the time period from the instant when the precharge is started to the instant when the node N, takes the sufficient precharge level (i.e., the low level ) is relatively elongated. More specifically, since the precharge of the node N, is conducted through the MOSFET Q5, it is not started so long as the MOSFET Q5 is held in its non-conductive state even if the input pulse ~IN falls to the low level simultaneously with the generation of the precharge pulse4.The on-timing of the MOSFET Q5 is delayed by such a delay time with respect to the precharge pulsed as is determined by the precharge MOSFET Q8 and the cut MOSFET 011.

The precharging rate of the node N, when the MOSFET Q5 is turned on is restricted by the conductance characteristics of the same MOSFET 05.

In order that the MOSFET Q5 may be brought from its non-conducting state into its conducting state within a time period as short as possible after the precharge pulsed has been generated, a first MOSFET may be provided which has a drainsource path connected between the power source terminal Vcc and the gate of the MOSFET Q5, and a gate fed with the precharge pulses.

Moreover, in order to allow the node N, to directly restore its precharge state, a second MOSFET may be provided which has a drain source path connected between the node N, and earth, and a gate fed with the precharge pulse}. If necessary, a third MOSFET may be provided which has a drain-source path connected between the node N, and the drain of the second MOSFET, and a gate fed with the power source voltage.

Both of either of the first and second MOSFETs may be provided.

Furthermore, in order to allow the output pulse ~out to more directly restore its precharge level, a fourth MOSFET may be provided which has a drain-source path connected in parallel with the drain-source path of the output MOSFET 04, and a gate fed with the precharge pulses.

In the case where the first, second and fourth MOSFETs are provided, the precharging rate of the timing pulse generator is further raised.

Additionally the voltage detecting means for starting the bootstrap operation may be modified in various forms including the means which makes use of a voltage comparator using differential MOSFETs.

Claims (15)

Claims

1. A timing pulse generator including: (a) a first node; (b) a first IGFET for applying an input pulse to said first node; (c) a second node; (d) a bootstrap capacitor coupled between said first node and said second node; and (e) a driver made receptive to a voltage appearing at said first node as an input voltage thereof for generating such an output voltage at said second node as is made to have a low level, when said input voltage is lower than a value to be detected, and a high level when said input voltage is higher than said value, whereby a signal at a boosted level is generated at said first node.

2. A timing pulse generator according to claim 1, wherein said driver includes: a voltage detector for generating the output voltage appearing at said first node; and a bootstrap capacitor driving circuit made receptive of a signal, which is generated by said voltage detector, for generating an output voltage to be applied to said second node.

3. A timing pulse generator according to claim 2, wherein said voltage detector is made operative to generate a signal which has a high level, when an input voltage thereto is lower than the value to be detected, and a low level when said input voltage is higher than said value; and wherein the bootstrap capacitor driving circuit is made operative to generate a signal which is in phase opposition with the signal which is detected by and fed from said voltage detector.

4. A timing pulse generator according to claim 3, wherein said first IGFET has: a drain-source path coupled between a node, which is fed with said input pulse, and said first node; and a gate fed with the output of said voltage detector.

5. A timing pulse generator according to claim 4, further including a second IGFET having a drain-source path coupled between the output terminal of said voltage detector and the gate of said first IGFET, and a gate fed with a reference voltage.

6. A timing pulse generator according to claim 3, wherein said voltage detector includes: third and fourth IGFETs having their drains and gates cross-coupled to each other, a fifth IGFET having a a drain-source path coupled between a power source terminal and the drain of said third IGFET, and a gate coupled to said first node; and a load element coupled between the power source terminal and the drain of said fourth IGFET.

7. A timing pulse generator according to claim 6, wherein said load element includes a sixth IGFET having a drain-source path coupled between said power source terminal and the drain of said fourth IGFET, and a gate to be fed with a pulse signal, whereby said voltage detector is dynamically operated.

8. A timing pulse generator according to claim 7, further including a seventh IGFET having a drain-source path connected in parallel with the drain-source path of said third IGFET, and a gate to be fed with said pulse signal.

9. A timing pulse generator according to claim 3, wherein, said bootstrap capacitor driving circuit includes: a second IGFET having a drain-source path coupled between said second node and earth of said driving circuit, and a gate to be fed with the output of said voltage detector; and a load element coupled between the power source terminal and said second node.

1 0. A timing pulse generator according to claim 9, wherein said load element includes a third IGFET having a drain source path coupled between the power source terminal and said second node, and a gate coupled to said first node.

11. A timing pulse generator according to claim 3, further having an output circuit including: a first output IGFET having a gate to be fed with the output of said voltage detector, a drain and a source; and a second output IGFET having a gate coupled to said first node, a drain and a source.

12. A dynamic memory including: (a) a memory array having a plurality of memory cells arranged in a matrix form, a plurality of data lines, to which the data input and output terminals of the respective memory cells are coupled, and a plurality of word lines to which the selection terminals of the respective memory cells are coupled; (b) a plurality of dummy cells coupled respectively to said data lines; (c) a dummy word line for selecting said dummy cells; (d) a plurality of sense amplifiers coupled respective to said data lines; and (e) a plurality of timing pulse generators for generating timing pulses, wherein each of said timing pulse generators includes: (f) a first IGFET for applying an input pulse to a first node through its drain-source path; (g) a bootstrap capacitor coupled between said first node and a second node; (h) a voltage detector which is receptive to a voltage appearing at said first node as an input voltage thereof for generating an output voltage which has a high level, when said input voltage is lower than a value to be detected, and a low level when said input voltage is higher than said value; (i) a bootstrap capacitor driving circuit for generating such a signal at said second node as is made to have a phase opposite to that of the output voltage fed from said voltage detector; and (j) a push-pull output circuit including first and second output IGFETs arranged to be driven by both an output voltage generated by said voltage detector and a voltage appearing at said first node.

13. A dynamic memory according to claim 12 wherein each of said sense amplifiers has its operation controlled by one of said timing pulse generators, and wherein the input pulses to be applied to the timing pulse generator for controlling the operations of said sense amplifiers are generated from a terminal of the dummy word line which is remote from a terminal supplied with a drive signal.

14. A timing pulse generator constructed and arranged to operate substantially as herein described with reference to and as illustrated in Figure 3 of the accompanying drawings.

15. A dynamic memory constructed and arranged to operate substantially as herein described with reference to and as illustrated in Figure 5 of the accompanying drawings.