GB2114403A - Computer-telex interface - Google Patents

Abstract

An interface device for use between a computer and a telex line and/or local teleprinter for telex print comprises level converting circuits 30 for conversion form the standard level of the computer to the interface level, series-parallel converting circuits 31, a microprocessor 32 comprising an at least 8-bit CPU, a permanent memory 23 (PROM) for code translation from EBCDIC into Baudot and for implementing computer end and telex end connection and communication procedures, a reversible data memory (RAM) 34 and data, address, and check lines 35-37 (BUS), parallel-series conversion circuits 38, and level converting circuits 39 for conversion from the interface level to the standard level of the telex line. <IMAGE>

Description

SPECIFICATION A telex interface device This invention relates to a device adapted to function as an interface between a computer and telex line and/or local teleprinter for telex print.

With information production and transmission systems, the problem is encountered of overcoming the difficulties connected with the different types of information supplied or receivable on one side by a computer and on the other by a telex system. Such information is first of all of different types because the computer produces and receives synchronous binary communications (BSC), whereas the telex line supplies and receives asynchronous serial data at five levels (Baudot method). Secondly, different is the information production and reception rate, which is much higher for the computer, it being for example 1200 Baud, whereas the telex line transmits and receives at the rate of 50, or in accordance with a more recent trend, even of 75 Baud.Such differences make direct communication between the computer and telex line, or local teleprinter transmitting and receiving telex communications, impossible, thereby it requires the action of an operator, in its most elementary of the solutions to the problem. Thus, the need is felt in the industry of communication means of automatically implementing the transmission of telex messages, notwithstanding the aforesaid difficulties.

This invention solves the problem by providing a device to be connected on one side to the computer and on the other side to the telex line and/or local teleprinter, capable of functioning as an interface therebetween and of enabling automatic transmission of information from/to each other, in either directions.

In its general form, the inventive device is characterized by the combination of the following circuit means: 1) level converting circuits for conversion from the standard level of the computer to the level of the central unit, explained hereinafter, practically from the V24 standard to the TTL (Transistor Transistor Logic) level; 2) series-parallel converting circuits; 3) a central unit (microprocessor) comprising: 3A) an at least 8-bit CPU; 3B) a permanent memory (PROM) constructed (programmed) for code translation from EBCDIC into Baudot, and for implementing the computer end and telex end connection and communication procedures; 3C) a reversible data memory (RAM); 3D) data, address, and check lines (BUS) which interconnect the components 2, 3A, 3B, 3C, and 4; 4) parallel-series converting circuits; and 5) converting circuits for conversion from the level of the central unit to the standard level of the telex line, in practice from the TTL level to current loop according to CCITT standard, preferably with telegraphic fork for local teleprinter.

The component 3A) is preferably an 8-bit CPU.

More specifically, the features and functions of the components of the inventive device, and their constructional and functional relationships, are as follows.

The circuits 1) serve the function of converting the pulses or information from the computer, which they are receiving, into others corresponding to a voltage level such that they can be received and processed by the following circuits, i.e. in practice at a suitable level for one of the conventionally available microprocessors such as a Z80, INTEL 8085, and the like.

The pulses brought up to the TTL level are still transmitted serially and must be converted to parallel if they are to be stored in the central unit memories and suitably processed. This is performed by the circuit means 2), serially connected to the former.

The information issuing from the circuit means 2) is ready for processing by the central unit. The latter, which comprises a CPU, a program memory (typically in the form of one or more PROM's), a data memory (typically in the form of one or more RAM's), and the various BUS (DATA, ADDRESS and CONTROL), constitutes altogether a microprocessor.

Said central unit is preferably an 8-bit microprocessor; a unit with a higher number of bits would be functional, but practically excessive. It receives the serial information which is transmitted to it from the computer or telex line (the local teleprinter, if any, would normally be no source of information). Of course, that unit has a finite storage capacity, and once this has been saturated, it will signal the occurrence in well known and obvious ways, which need not be described herein. Within the limits of its storage capacity, therefore, said unit will process the information in the required manner for its use by the telex line or local telex, when coming from the computer, and by the computer, when coming from the telex line.

At this stage, since the telex also operates on serial information and at a different level from the microprocessor, the information must be re-converted from series to parallel and brought to a suitable level.

This is done by the circuit means 4) and 5).

The listing order of the components of the inventive device, and the order followed in describing their functions, apply to the instance of the information being passed from the computer to the telex, but should it be passed instead from the telex line to the computer, then the same components may be considered in the reverse order, since their operation is reversible. Thus, the level converters operate a reversible conversion, and the series-to-parallel converters can also convert from parallel into serial, and viceversa.

All of the components of the device according to the invention, as individually considered, are known and commercially available without any difficulties by an expert in the art. Their combination into a unitized device, for the purposes and with the functions specified hereinabove, constitutes novelty and a significant inventive step in the specific art involved.

The invention will be more clearly understood from the following description of a preferred embodiment thereof, with reference to the accompanying drawings, where: Figure 1 is a diagram showing the connections between the interface device of this invention and computer, on one side, and the telegraphy line and/or local teleprinter, on the other; Figure 2 is a schematical representation of the inner structure of the inventive device, according to a preferred embodiment thereof; Figure 3 shows schematically one possible flow chart or operating schedule of the device according to this invention; Figures 4, 4a, and 4b schematically illustrate one possible informational exchange procedure between the inventive device and a computer operating in conformity with the BSC procedure, which represents a preferred embodiment of this invention; and Figures 5-9 illustrate an electronic diagram of an interface device according to the exemplary embodiment of the invention, and specifically, Figure 5 shows a level adaptor unit, Figure 6 a frequency generating unit, Figure 7 a microprocessor unit, Figure 8 a feed unit, and Figure 9 a diagram of the interconnections of the units, of Figures 5-8.

Making now reference to Figure 1, the numeral 10 schematically designates the interface device of this invention, which communicates with the computer 13 through the gate 11 and line 12, the computer being of preference a medium-large size computer, e.g. of the IBM S/34 type.

The unit 10 is connected, through a gate 14 and line 15 through the line Protection device 16, to the telegraph line 17, which leads to the telex station. Through the gate 18 and line 19, the unit 10 communicates with the local teleprinter 20. The dash line 21 indicates the communication between the telex station and local teleprinter.

Making now reference to Figure 2, the inventive device comprises, starting with the gate 11 toward the gates 14 and 18, the components specifically described hereinbelow.

The reference numeral 30 designates the level adapter, which comprises circuit means for level conversion from standard V24 to TTL level, and has been designated as component 1) in the general definition of the device, hereinabove.

Level adapters of this kind are commercially available, e.g. like the LM 1488, LM 1489,75188,75189.

The component 31 is a series-parallel converter, which is effective to receive and convert information at the same rate as the computer synchronous information, in practice at 1200 Baud. This type of component is known commercially as USART (Universal Synchronous Asynchronous Receiver Transmitter) and can be supplied in a construction suitable for conversion from/into synchronous or asynchronous information, and for the various frequencies used in the industry. Thus, the component 31 will be a synchronous 1200 Baud USART.

The information from the component 31 is supplied to the central unit BUS's. The central unit includes all the elements of a microprocessor, namely: a CPU 32; a programmed memory 33, typically comprising one or more PROM's; a data storage memory 34, typically comprising one or more RAM's; a DATA BUS 35; an ADDRESS BUS 36; and a CONTROL BUS 37. The use of different type memories is not to be ruled out, in principle. The construction and operation of these components are too well known to require an explanation.

It will be sufficient to say that the input program of the memory 33 is such as to enable the processing of data supplied from the computer such that they can be received and utilized by the telex line or local teleprinter.

At that stage, the data must be re-converted from parallel to serial in a suitable way for the telex, and accordingly, the device will include a parallel-series converter 38 which comprises an asynchronous 50 Baud USART (or, as mentioned, one having a slightly higher frequency, such as 75 Baud).

The reference numeral 39 designates the level adapterfrom TTL to current loop in conformity with the CCITT standard. The information from the component 39 may be passed preferably through a fork 40 which will direct it, according to occasion, either to the telex line through the gate 14, or to the local teleprinter, through the gate 18. However, communication to a local teleprinter or telex line could be missing.

The device is, as mentioned, reversible. The arrows on the diagram of Figure 2 emphasize this reversible feature. The data flow in either direction between the various components of the central unit is typical of any microprocessor and will readily occur to the person skilled in the art. The flow in both directions between the central unit and the USART's, and between the latter and level adapters, will be apparent from the diagram and require no further explanation.

The flow diagram or operating schedule shown in Figure 3 by way of example requires no additional discussion besides the information given in the Figure legenda.

Figure 4a illustrates the talk between the computer and interface device according to the invention, in conformity with the procedure BSC (Binary Synchronous Communications). In the Figure, the reference characters C and I designate the computer and interface, respectively.

The computer initiates a request for line checking by transmitting the characters ENQ (Enquiry) (1) preceded by the synchronization characters sp (specified in Figure 4c). The interface responds to this request with ACK ~ (2) indicating that the reception is correct and that transmission may continue. The computer resumes operation by supplying the first data block (3) (country prefix, name of the addressee, reply name) preceded by the characters STX (Start of Text) and terminated with ETB (End of Block); trailing are the control characters W (specified in Figure 4b). The interface computes internally the control characters (BCC, BCC) and compares them to those received. If the two characters are the same (no errors in the data reception), the interface response is an ACK (block (4)).The computer resumes the transmission to send the second block of data (5) represented in this specific case by 69 exclamation marks, to which the interface responds with the block (6) followed by text closing (block (7)) by the computer. After this stage, the interfaces releases the synchronous communication lines and initiates the connection procedure to the telex line by performing the operations of name giving and reply checking.After requesting and comparing the name of the selected user for two times, the interface resumes the synchronous communication by supplying the computer with a request for line checking with the block (8) and upon affirmative response from the computer (block (9)) transmits the symbol ITC (block (10)) followed by a numeral indicating the outcome of the hook up with the telex line (in the example, in the Figure ~i indicates correct selection). After the computer response (block (11)) the interface closes the transmission with EOT (block (12)). At this stage, fthe computer resumes control of the line (blocks (13) and (14)), and passes the text, line by line (blocks (15) and (16)), as repeated N times, where N = number of lines in the text).After passing the last line of the text (in this specific case MMMMM) the computer closes the text (block (17)) and upon affirmative response (18), terminates the transmission (19). The interface again releases the synchronous lines and effects the exchange and check on the names with the user called, to them re-hook the synchronous lines (block (20)), and upon response from the computer (21), transmits the symbol ITC (block (22)) followed by a number as described above. Upon response from the computer (block (23)), the interface terminates the talk (block (24)) and is restored to the initial step in readiness for a fresh request from the computer to send out a successive cable.

Figures 5-8 illustrate the electronic circuits of the interface device and auxiliary circuits, according to a preferred embodiment of the invention, showing them rather than in the functional arrangement followed by the description, as they are physically assembled together on the individual plates, as individual units.

Figure 5 shows the wiring diagram of the level adaptor unit. This unit comprises the level adapter 30 and gate 11 for passing information between the microprocessor and computer and adapter 39, the fork 40, and gates 14 and 18 for passage between the microprocessor and telex line or local teleprinter.

To exemplify the description, the diagram of Figure 5 has been divided into 6 blocks, each block including the components which perform said function.

The following Table summarizes the functions and operating levels of the individual blocks.

Block Function Signal levels 1 telex line to microprocessor In +20 mA Out 0,+5V 2 microprocessor to local teleprinter In= 0,+5V Out= f20 mA 3 microprocessor to telex line In= 0,+5V Out= +20 mA 4 local teleprinter to microprocessor In j20 mA Out 0,+5V 5 microprocessor to computer In= 0,+5V Out= +12V 6 computer to microprocessor In= +12V Out= 0,+5V The level adapter unit further comprises a relay, indicated at RLA, serving the function of galvanically connecting the telex line to the local teleprinter in the inoperative condition.

The task of generating the frequencies required for the operation of the whole device is performed by the circuit of Figure 6.

Starting with a single quartz oscillator having a frequency of 4,915.2 kHz, the required frequencies can be obtained through independent division chains, which may be summarized as follows: Symbol Frequency Function USART ~ 1,228.8 kHz Clock signal of the series/ parallel converters (USART) Z80 ~ 2,457.6 kHz Clock signal of the CPU Z80 CL ~ 1.2 kHz Signal emission frequency, synchronous side (1,200 Baud) CL1 800.0 kHz Signal emission frequency, asynchronous side (x 16) The circuits illustrated in Figures 5 and 6 are connected, in conformity with the interconnections diagram of Figure 9, to the microprocessor unit, the electric diagram whereof is shown in Figure 7.

The microprocessor plate of Figure 7 actually comprises, additionally to the microprocessor or central unit 3, also the two series/parallel converters (USART) 2 and 4.

On this plate, the CPU (Z80) is connected through the address and data buses to the program memories (EPROM 2716), to the data memories (RAM 2114), and to the two series/parallel converters, of which one (8251 a) effects the synchronous connection to the computer, and the other (8251b) transmits and receives in a synchronous manner toward the telex line and local teleprinter.

The above-described three units, depending on the functions they perform, require different feed voltages, namely: Microprocessor plate or unit (Fig 7) feed = - 5V, + 5V Generating unit (Figure 6) feed = - 5V, + 5V Level adapter unit (Figure 5) feed = - 5V, + 5V CPU side = + 12V, - 12V computer side = + 60V, - 60V telex side All of the above feed voltages are generated by the circuit of Figure 8.

Claims (6)

1. An interface device between a computer and a telex line and/or local teleprinter for telex print out, comprising in combination the following elements: 1) level converting circuits from the computer standard to the level of the central unit 3, 2) series-parallel conversion circuits, 3) a central unit including: 3A) an at least 8-bit CPU, 3B) a permanent memory (PROM) arranged to translate codes from EBCDIC into Baudot and for implementing the connection and communication procedures on the computer side and telex side; C) a reversible data memory (RAM); 3D) data, address and check lines (BUS) which connect the components 2, 3A, 3B, 3C and 4; 4) parallel-series conversion circuits; and 5) converting circuits from the level of the central unit to the telex line standard.

2. A device according to Claim 1, wherein the component 3A comprises an 8-bit CPU.

3. A device according to Claim 1 or 2, characterised in that the component 1) comprises level converting circuits from the standard V24 to the TTL level, and that the component 5) comprises level converting circuits from TTL to current loop in conformity with the CCITT standard.

4. A device according to Claim 1, 2 or 3, characterised in that it comprises a fork adapted to put the device into communication alternately with a telex line and a local teleprinter.

5. A device according to any preceding Claim, wherein the central unit is an 8-bit Z80 microprocessor.

6. An interface device between a computer and a telex line and/or local teleprinter, substantially as described and illustrated.