GB2103456A - Digital data transmission systems - Google Patents

Abstract

Serial data bits are formed into parallel bit groups X1-X6 and a sub-group of bits X1, X2 determines the quadrant in which the phase of a carrier is to lie while the remaining bits X3-X6 of the group determine the phase and/or the amplitude of the carrier within the selected quadrant. The quadrants have a degree of rotational symmetry, and data signal combinations giving rise to adjacent amplitude/phase values differ from one another in accordance with a Gray code. An encoding and a decoding gating network are given. Two carriers in phase quadrature may be modulated. <IMAGE>

Description

SPECIFICATION Digital data transmission systems The present invention relates to digital data transmission systems.

In particular although not exclusively the invention relates to encoding arrangements for use in digital data transmission systems.

According to the present invention an encoding arrangement for use in a digital data transmission system in which data signal values are represented in transmission by a succession of values of phase and amplitude of a carrier signal in a succession of time intervals, the digital data signals are distributed to a plurality of parallel input paths of said encoding arrangement, and there are provided gating means responsive to data signal values on a first group of said input paths arranged selectively differentially to shift the phase of said carrier signal by one or more of a plurality of phase intervals between one time interval and the next, and responsive to respective combinations of data signal values on the remainder of said plurality of input paths to set the amplitude of said carrier signal and/or its relative phase within any one of said phase intervals to respective predetermined values.

Preferably said phase intervals are each 90 , and said gating means is arranged to modulate two carrier signals in phase quadrature to determine the differential phase shift between time intervals and to determine the amplitude and the relative phase within a quadrant. The amplitudes and relative phases within a quadrant may be assigned to the respective combinations of data signal values on the remainder of said input paths such that combinations giving rise to adjacent amplitude and relative phase values differ from one another in accordance with a Gray code.

A digital data transmission system including an encoding arrangement in accordance with the present invention will now be described by way of example with reference to the accompanying drawings, of which : Figure 1 shows the transmitter and receiver of the system schematically, Figure 2 shows schematically an encoder forming part of the transmitter of the system shown in Figure 1, Figure 3 shows schematically a decoder forming part of the receiver of the system shown in Figure 1, and Figure 4 shows diagrammatically the coding scheme provided by the encoder shown in Figure 2.

Referring first to Figure 1 a stream of digitally encoded data bits at up to, say, 140 M bits/sec on a path 1 are distributed by means of a splitter arrangement 2 to six paths X1 to X6 such as to presend the data bits in six parallel streams, at a correspondingly lower bit rate, to an encoder3. The values of the data bits on the paths X1 and X2 are first differentially coded (not shown) and are used as will be described below to determine into which of the four quadrants the phase of a carrier signal is next shifted.

Referring also to Figures 2 and 4 the encoder 3 and modulator driving logic circuits 4 provide two three-bit binary coded outputs A and B by means of which the amplitude and phase of two quadrature carrier signals are controlled in a modulator 5. For example the value 000 forthe output A may define maximum amplitude for one of those carrier signals in one sense and the value 111 for the output A may define maximum amplitude of that one of the carrier signals in the opposite sense, with intermediate values of the output A defining intermediate carrier amplitudes between the two extremes.

At the receiver the amplitude and phase values of the two quadrature carriers are recovered in a synchronous detector (not shown) and are applied to a demodulator 6. The demodulator 6 comprises respective sets of seven threshold circuits which provide outputs A' and B' in accordance with the values of the received signals, and these outputs A' and B' are applied to decoder logic circuits 7 as shown in Figure 3. The decoder logic provides six parallel outputs Z corresponding to the original data signals on the paths X, these outputs Z being combined in sequence to provide the output data stream.

As shown in Figure 4the values 00 for the digits X1 and X2 are arranged to define the top left phase quadrant, the values 01 the top right quadrant,11 the lower right quadrant and 10 the lower left quadrant.

The values for the remaining four digits X3 to X6 are used to define sixteen amplitude/phase combinations within a quadrant, these amplitude/phase combinations being in the same relative positions in each quadrant. For example, where the four digits X3 to X6 have the values 0000 the two quadrature carriers both have maximum amplitude and the effective transmitted carrier phase is in the middle of whichever quadrant it is shifted in response to the digits X1 and X2.

The coding scheme shown in Figure 4 provides for sixty four distinguishable phase/amplitude combinations, defined by six-bit values derived from the data stream to be transmitted. By using the paths X, and X2 with just two of the paths X3 to X6 the central group of sixteen phase/amplitude combinations can be utilised, with the data bits being divded into groups of four.

By means of switches 8 and 9 in the encoder and decoder respectively a set of thirty-two phase/amplitude combinations may be used, these combinations lying within the dashed line in Figure 4.

Because of this capability the coder and decoder described above are particularly useful for test purposes.

It will be seen from Figure 1 that in general the six bit groups in each phase quadrant differ from adjacent groups in one digit, so that the effects of errors in transmission are minimal.

1. An encoding arrangement for use in a digital

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (4)

**WARNING** start of CLMS field may overlap end of DESC **. SPECIFICATION Digital data transmission systems The present invention relates to digital data transmission systems. In particular although not exclusively the invention relates to encoding arrangements for use in digital data transmission systems. According to the present invention an encoding arrangement for use in a digital data transmission system in which data signal values are represented in transmission by a succession of values of phase and amplitude of a carrier signal in a succession of time intervals, the digital data signals are distributed to a plurality of parallel input paths of said encoding arrangement, and there are provided gating means responsive to data signal values on a first group of said input paths arranged selectively differentially to shift the phase of said carrier signal by one or more of a plurality of phase intervals between one time interval and the next, and responsive to respective combinations of data signal values on the remainder of said plurality of input paths to set the amplitude of said carrier signal and/or its relative phase within any one of said phase intervals to respective predetermined values. Preferably said phase intervals are each 90 , and said gating means is arranged to modulate two carrier signals in phase quadrature to determine the differential phase shift between time intervals and to determine the amplitude and the relative phase within a quadrant. The amplitudes and relative phases within a quadrant may be assigned to the respective combinations of data signal values on the remainder of said input paths such that combinations giving rise to adjacent amplitude and relative phase values differ from one another in accordance with a Gray code. A digital data transmission system including an encoding arrangement in accordance with the present invention will now be described by way of example with reference to the accompanying drawings, of which : Figure 1 shows the transmitter and receiver of the system schematically, Figure 2 shows schematically an encoder forming part of the transmitter of the system shown in Figure 1, Figure 3 shows schematically a decoder forming part of the receiver of the system shown in Figure 1, and Figure 4 shows diagrammatically the coding scheme provided by the encoder shown in Figure 2. Referring first to Figure 1 a stream of digitally encoded data bits at up to, say, 140 M bits/sec on a path 1 are distributed by means of a splitter arrangement 2 to six paths X1 to X6 such as to presend the data bits in six parallel streams, at a correspondingly lower bit rate, to an encoder3. The values of the data bits on the paths X1 and X2 are first differentially coded (not shown) and are used as will be described below to determine into which of the four quadrants the phase of a carrier signal is next shifted. Referring also to Figures 2 and 4 the encoder 3 and modulator driving logic circuits 4 provide two three-bit binary coded outputs A and B by means of which the amplitude and phase of two quadrature carrier signals are controlled in a modulator 5. For example the value 000 forthe output A may define maximum amplitude for one of those carrier signals in one sense and the value 111 for the output A may define maximum amplitude of that one of the carrier signals in the opposite sense, with intermediate values of the output A defining intermediate carrier amplitudes between the two extremes. At the receiver the amplitude and phase values of the two quadrature carriers are recovered in a synchronous detector (not shown) and are applied to a demodulator 6. The demodulator 6 comprises respective sets of seven threshold circuits which provide outputs A' and B' in accordance with the values of the received signals, and these outputs A' and B' are applied to decoder logic circuits 7 as shown in Figure 3. The decoder logic provides six parallel outputs Z corresponding to the original data signals on the paths X, these outputs Z being combined in sequence to provide the output data stream. As shown in Figure 4the values 00 for the digits X1 and X2 are arranged to define the top left phase quadrant, the values 01 the top right quadrant,11 the lower right quadrant and 10 the lower left quadrant. The values for the remaining four digits X3 to X6 are used to define sixteen amplitude/phase combinations within a quadrant, these amplitude/phase combinations being in the same relative positions in each quadrant. For example, where the four digits X3 to X6 have the values 0000 the two quadrature carriers both have maximum amplitude and the effective transmitted carrier phase is in the middle of whichever quadrant it is shifted in response to the digits X1 and X2. The coding scheme shown in Figure 4 provides for sixty four distinguishable phase/amplitude combinations, defined by six-bit values derived from the data stream to be transmitted. By using the paths X, and X2 with just two of the paths X3 to X6 the central group of sixteen phase/amplitude combinations can be utilised, with the data bits being divded into groups of four. By means of switches 8 and 9 in the encoder and decoder respectively a set of thirty-two phase/amplitude combinations may be used, these combinations lying within the dashed line in Figure 4. Because of this capability the coder and decoder described above are particularly useful for test purposes. It will be seen from Figure 1 that in general the six bit groups in each phase quadrant differ from adjacent groups in one digit, so that the effects of errors in transmission are minimal. CLAIMS

1. An encoding arrangement for use in a digital data transmission system in which digital data signal values are represented in transmission by a succession of values of phase and amplitude of a carrier signal in a succession of time intervals, wherein the digital data signals are distributed to a plurality of parallel input paths of said encoding arrangement, and there are provided gating means responsive to data signal values on a first group of said input paths arranged selectively differentially to shift the phase of said carrier signal by one or more of a plurality of phase intervals between one time interval and the next, and responsive to respective combinations of data signal values on the remainder of said plurality of input paths to set the amplitude of said carrier signal and/or its relative phase within any one of said phase intervals to respective predetermined values.

2. An encoding arrangement in accordance with Claim 1 wherein said phase intervals are each 90 , and said gating means is arranged to modulate two carrier signals in phase quadrature to determine the differential phase shift between time intervals and to determine the amplitude and the relative phase within a quadrant.

3. An encoding arrangement in accordance with Claim 2 wherein the amplitudes and relative phases within a quadrant are assigned to the respective combinations of data signal values on the remainder of said input paths such that combinations giving rise to adjacent amplitude and relative phase values differ from one another in accordance with a Gray code.

4. An encoding arrangement substantially as hereinbefore described with reference to the accompanying drawings.