GB2103398A - Microcomputer apparatus for use with a video display - Google Patents

Abstract

Microcomputer apparatus includes a Zilog Registered Trade Mark Z80A-CPU central processing unit 1 operable with 8-bit data and 16-bit address information, an upper 8-bit address bus 5H, a lower 8-bit address bus 5L, an 8-bit data bus 4, a ROM 2 for storing a monitor program and/or a BASIC interpreter and connected to the central processing unit 1 through the address buses 5H, 5L and the data bus 4, a first RAM 3 for a work area connected to the central processing unit 1 through the address buses 5H, 5L and the data bus 4, a second separate video buffer RAM 12 for video display connected to the central processing unit 1 through the address buses 5H, 5L and the data bus 4 and accessed by I/O instructions from the central processing unit 1, and a cathode ray tube display 23 for displaying a video picture in response to video data stored in the video RAM 12. <IMAGE>

Description

SPECIFICATION Microcomputer apparatus for use witha video display This invention relates to microcomputer apparatus for use with a video display.

Recently, desk top microcomputer apparatus has become available comprising an 8-bit central processing unit (CPU) which uses 16-bit addresses, such that the CPU can directly access a memory area of 64K locations, that is, from 0000H to FFFFH, with each address location including 8-bits (one byte) of data.

Accordingly, with a personal computer of this type which uses an 8-bit CPU, 32K, for example, of the address of the memory area may be used as a read only memory (ROM) area for storing a monitor program and/or BASIC interpreter, and the remaining 32K addresses can be used as a random access memory (RAM) area.

However, when using the microcomputer apparatus with a cathode ray tube monitor or display, it is necessary to provide a video RAM area. For example, if a graphic or video display of 640 x 400 dots is provided, with one bit being assigned to one dot, a video RAM of 32K bytes or less is required. As a result, there may be little or no RAM area for user programming. In order to expand the memory area to avoid such problems, it has been proposed to provide a plurality of memory banks selectively connected to the CPU under the control of the system software. However, since change-over of the different memory banks must be carried out in accordance with the software program, such change-over is troublesome and the processing speed of the program is lowered. In addition, the writing of such a program is relatively complicated and extremely careful attention is necessary to prevent errors.

According to the present invention there is provided microcomputer apparatus comprising: central processing means operable with n-bit data dn m-bit address information; bus means; read only memory means for storing a monitor program and connected to said central processing means through said bus means; first random access memory means for a work area connected to said central processing means through said bus means; and second separate random access memory means for a video disply and connected to said control processing means through said bus means and arrange to be accessed by l/O instructions from said central processing means.

The invention will now be described by way of example with reference to the accompanying drawings, in which: Figures 1A and 18 are schematic diagrams used to explain the operation of a CPU for microcomputer apparatus according to the invention; Figure 2 is a block diagram of an embodiment of microcomputer apparatus according to the invention; Figures 3A and 3B are schematic diagrams used to explain the memory address allocation in the microcomputer apparatus of Figure 2; and Figures 4A to 4D are schematic diagrams used to explain the connection between the CPU and a video buffer memory.

Referring initially to Figure 2, microcomputer apparatus according to one embodiment of the invention includes a CPU 1 which may, for example, be a Z80A-CPU designed by Zilog, Registered Trade Mark Incorporated or an NSC-800 CPU designed by National Semiconductor. Hereinafter, all reference to the CPU 1 will be directed to a Z80A-CPU which will be used for explanatory purposes only. The microcomputer apparatus also includes a ROM 2 which stores a monitor program and a BASIC interpreter program, and which, for example, includes 32K 8-bit address locations from 0000H to 7FFFH, as shown in Figure 3A. The microcomputer apparatus also includes a RAM 3 in which a user program can be written and which also serves as a work area for the CPU 1. As shown in Figure 3B, the RAM 3 also includes 32K 8-bit address locations from 8000H to FFFFH.It is to be appreciated that the above numbers of 8-bit address locations are given only for illustrative purposes, and the invention is not limited to the specific numbers used. An 8-bit data bus 4, a lower 8-bit address bus 5L and an upper 8-bit address bus 5H are connected to corresponding data terminals Do to D7, address terminals Ao to A7 and address terminals A8 to A15, respectively of the CPU 1, the ROM 2 and the RAM 3 for transferring information therebetween.

To control the reading of information from the ROM 2 and the RAM 3, the CPU 1 supplies a memory request signal MREQ and/or a read signal RD to respective inputs of an OR circuit 6 to derive a memory read signal MEMR which is supplied to respective read terminals R of each of the ROM 2 and the RAM 3. In like manner, to perform a writing operation with respect to the RAM 3, a write signal WR is generated by the CPU 1, and the write signal WR and/or the memory request signal MREQ are supplied to respective inputs of an OR circuit 7. The OR circuit 7 in turn produces a memory write signal MEMW which is supplied to a write terminal W of the RAM 3.

With the microcomputer apparatus of Figure 2, a maximum of 256 external I/O ports 11 can be connected to the CPU 1, each being designated by a port number n from 00H to FFH. However, fewer than 256 1/O ports 11 can be provided. For example, the ports numbered 80H to FFH can be provided. A plurality of external I/O devices, such as a keyboard 21 and a magnetic tape cassette 22 can be connected to each I/O port 11, with a maximum of 256 external I/O devides being connected to each port. For ease of understanding the embodiment, only the one I/O port 11 shown in Figure 2 will be described hereinafter. The I/O port 11 includes the data terminals Do to D7 connected to the data bus 4, and the address terminals Ao to A7 connected to the lower address bus 5L.In the same manner as previously discussed with regard to the ROM 2 and the RAM 3, the CPU 1 controls the reading and writing of information from and to the I/O port Thus, the CPU 1 generates an I/O request signal.lORQ, and the I/O request signal and/or the read signal RD are supplied to respective inputs of an OR circuit 8 which, in turn, supplies an I/O read signal IOR to a read terminal R of the I/O port 11. In like manner, the I/O request signal IORQ and/or the write signal WR are supplied by the CPU 1 to respective inputs of an OR circuit 9 which, in turn, supplies an I/O write signal iOW to a write terminal W of the I/O port 11. In this manner, reading and writing of information between the I/O port 11 and the CPU 1 can be effected.

By way of example only, operating instructions for a Z80A-CPU will now be discussed for transferring data between an external I/O port 11 and the CPU 1 (and consequently, the RAM 3). It is first to be noted that the Z80A-CPU includes at least A,B,C,D,E,H and L general purpose registers and the transfer of 8-bit data between an external I/O port 11 and one or more of these registers occurs through the data bus line 4.

Corresponding address information is transferred through the 16-bit address bus line comprising the upper 8-bit address bus line 5H and the lower 8-bit address bus line 5L. In particular, the following I/O instructions can be used: 1-1 IN A, n This instruction transfers 8-bit data at an input port designated by a port number n (n = 0 to 255) to the A register of the CPU 1.

1-2 OUT n, A This instruction transfers 8-bit data from the A register of the CPU 1 to an output port designated by the port number n. It is to be appreciated that, with these instructions, the 8-bit data from the A register appears both on the data terminals Do to D7 and on the address terminals A8 to As5. In this case, the lower 8-bit address terminals Ao to A7 are supplied with address information and indicate the port number n, as shown in Figure 1A.

11-1 IN r, (C) This instruction transfers data at a port (identified by the port number n) designated by the BC register pair of an r register, where the r is one of the A, B, C, D, E, H and L registers.

11-2 OUT (C), r This instruction transfers data from the r register to the port (identified by the port number n) designated by the BC register pair. In Figure 1 B, data for the r register appears at the data terminals Do to D7, the C register contains information from the address terminals Ao to A7 corresponding to the port number n, and B register contains information from the address terminals A8 to A18 corresponding to the I/O device connected to the designated port. Since eight bits of information are provided in the C register, a maximum of 256 (0 to 255) I/O devices can be connected to each port, as previously mentioned.

As will be apparent from the discussion hereinafter, the following block transfer instructions are also used with the CPU 1: 111-1 INIR, INDR With these instructions, a plurality of bytes of data, that is, a block of data, can be transferred from a port n to the main memory. In this case, the BC register pair is used to determine the port number (C register) and the number of bytes to be transferred (B register). The data block is transferred to a memory location, the address of which is determined by the HL register pair. For example, the last address location to which the data is to be transferred is stored in the HL register pair. The B register is then used as a counter and counts down to zero. In particular, the value in the B register is continuously decremented by one, and during each decrement of one, one byte of the block is transferred. When the value stored in the register B is equal to zero, all of the bytes of the block of data have been transferred from the respective I/O port designated by the C register.

111-2 OTIR, OTDR With these instructions, a data block can be transferred from the main memory to an I/O port designated by the C register. The HL register pair and the B register are used in a similar manner to that described above.

As an example of the above instructions, the following program can be used to effect such transfer: LD HL, 08FFH LD BC, FF03H OTDR With this program, the last address in the main memory at which the data is stored is loaded into the HL register pair by the load instruction LD, that is, the last address 08FFH. The port number n is loaded into the C register, that is 03H, and the number of bytes to be transferred is loaded into the B register, that is, FFH. The value loaded into the B register is then continuously decremented by one until it equals zero, and during each decrement of one, one byte of the block of data located at addresses 0800H to 08FFH of the main memory is transferred to the port designated by the port number 03H. When the value stored in the B register equals zero, all of the bytes of the block of data have been transferred.

A separate video RAM 12 is provided as a buffer memory for use in displaying the processed results and, as shown in Figure 3B, is allocated a 32K address memory having addresses 0000H to 7FFFH, for example.

For ease of transfer of data between the video RAM 12 and the Z80A-CPU, as shown in Figure 2, the lower 8-bit address terminals Ao to A7 of the video RAM 12 are connected to the upper address bus 5H corresponding to the upper 8-bit address terminals A8 to A15 of the CPU 1, the ROM 2 and the RAM 3. In like manner, the upper 8-bit address terminals A8 to A15 of the video RAM 12 are connected to the lower address bus 5L corresponding to the lower 8-bit address terminals Ao to A7 of the CPU 1, the ROM 2 and the RAM 3. In addition, the I/O read signal IOR and the I/O write signal lOW from the OR circuits 8 and 9, respectively, are supplied to a read terminal R and a write terminal W respectively of the video RAM 12 for controlling the reading and writing operations thereof.The data terminals Do to D7 of the video RAM 12 are also connected to the data bus 4. To display the contents of the video RAM 12, a cathode ray tube (CRT) controller 13 is connected to the video RAM 12 for sequentially reading the data from the video RAM 12 and supplying it to a CRT display 23.

With the embodiment of Figure 2, the ROM 2 and the RAM 3 are assigned to respective memory control areas of the CPU 1, while the video RAM 12 is assigned to an I/O area thereof. In this manner, the video RAM 12 can be addressed by the BC register pair of the CPU 1 in response to I/O instructions, as discussed previously with regard, for example, to the instructions 11-1 and 11-2. Accordingly, as a result of such allocation with respect to the ROM 2, the RAM 3 and the RAM 12, the programmable or work area that can be used in the RAM 3 is not reduced by a video RAM area so that a larger program area is provided for the user.

Moreover, since the area of the video RAM 12 can be made as large as 32K bytes, a graphic function having high resolution, for example, 640 x 400 dots, can be achieved. It is to be appreciated that the instructions or commands given by the CPU 1 for the ROM 2 and the RAM 3 can be similar to those used in conventional microcomputer apparatus, while the I/O instructions or commands 1-1, 1-2,11-1,11-2,111-1 and 111-2 can easily be used for the video RAM 12. In other words, it is important that a separate video RAM 12 is provided which is accessed by I/O instructions from the CPU 1. Accordingly, the video RAM 12 can be considered as another l/O port or I/O device.

It is to be appreciated, as previously discussed, that the connections between the lower 8-bit address terminals Ao to A7 and the upper 8-bit address terminals A8 to A15 of the video RAM 12 are reversed or interchanged from those of the CPU 1, the ROM 2 and the RAM 3, as shown in Figures 4A to 4C, at least for the case where the CPU 1 is a Z80A-CPU. Accordingly, block transfer of a 256-byte unit can be achived between the RAM 3 and the video RAM 12 in response to the I/O instructions 111-1 and 111-2. For example, the aforementioned OTDR program can be used to achieve such transfer. In this case, the value stored in the C register designates the video RAM 12. With such a program, data from the RAM 3 can readily be transferred directly to the video RAM 12 without any buffer memory. As shown in Figure 4D, the lower 8-bit addresses Ao to A7 of the CPU 1 stored in the C register thereof correspond to respective address locations of the I/O port 11, orthevideo RAM 12, wherebythe I/O instructions 1-1, 1-2,11-1,11-2,111-land 111-2 can be used with the video RAM 12 in a manner similar to that of a conventional microcomputer.

It is to be appreciated that, with the embodiment, it is unnecessary first to select a memory bank and then access that memory bank. Accordingly, the speed of carrying out the program is not lowered and the programmer need not prepare a complex program.

Claims (9)

1. Microcomputer apparatus comprising: central processing means operable with n-bit data and m-bit address information; bus means; read only memory means for storing a monitor program and connected to said central processing means through said bus means; first random access memory means for a work area connected to said central processing means through said bus means; and second separate random access memory means for a video display and connected to said control processing means through said bus means and arranged to be accessed by I/O instructions from said central processing means.

2. Apparatus according to claim 1 wherein n equals eight and m equals sixteen.

3. Apparatus according to claim 2 wherein said central processing means is a Zilog, Incorporated Z80A-CPU.

4. Apparatus according to claim 3 wherein said bus means includes address bus means, said central processing means includes upper 8-bit address terminals and lower 8-bit address terminals, and said second random access memory means includes upper 8-bit address terminals connected to said lower 8-bit address terminals of said central processing means through said address bus means and lower 8-bit address terminals connected to said upper 8-bit address terminals of said central processing means through said address bus means.

5. Apparatus according to claim 4 wherein said address bus means includes an upper 8-bit address bus for connecting the upper 8-bit address terminals of said central processing means with the lower 8-bit address terminals of said second random access memory means, and a lower 8-bit address bus for connecting the lower 8-bit address terminals of said central processing means with the upper 8-bit address terminals of said second random access memory means.

6. Apparatus according to claim 1 wherein said bus means includes data bus means, said central processing means includes data terminals, and said second random access memory means includes data terminals connected to the data terminals of said central processing means through said data bus means.

7. Apparatus according to claim 1 further comprising display means for displaying a video picture in response to video data stored in said second random access memory means.

8. Apparatus according to claim 7 wherein said display means is a cathode ray tube.

9. Microcomputer apparatus substantially as herein before described with reference to Figure 2 of the accompanying drawings.