GB2100534A - Frequency synthesiser - Google Patents

Abstract

The operation of a multi-stage frequency synthesiser is simulated one stage at a time by simulating each stage sequentially for a limited period. An offset frequency for each stage and related to an interim frequency produced in the preceding stage, or to a reference frequency is stored via a delay line (35) for a suitable period. A modulo-N divider (36) is stepped to each digit in turn of a required frequency (or each of an appropriate sequence of ratios) starting with the least significant digit. When the complete frequency has been achieved by the first loop (29-39) a second voltage controlled oscillator (V.C.O.2) is switched in to store the complete frequency, after which the frequency is resynthesised using the first voltage controlled oscillator V.C.O.1). The delayed offset frequency is obtained by means of the fixed ratio divider (34) and the delay line (35). A further indirect synthesis arrangement is described with respect to Figures 7 and 8, and a direct synthesis arrangement is described with respect to Figures 9 and 10. <IMAGE>

Description

SPECIFICATION Frequency synthesiser This invention relates to methods of synthesising desired frequencies, and circuits for use therein, which are suitable for direct or indirect synthesis.

Frequency synthesis is a means by which a range of frequencies may be generated that are related mathematically to a reference frequency and hence exhibit all or some of the stability and spectral purity characteristics of the reference frequency.

One known synthesiser circuit comprises a multistage (multi-loop) indirect frequency synthesiser employing digital phase-locked loop synthesis. Multi-loop synthesisers, particularly for radio frequencies, necessarily involve the use of large amounts of costly circuitry.

According to one aspect of the present invention there is provided a method of synthesising a desired frequency comprising simulating the operation of a conventional multi-stage synthesiser one stage at a time by simulating each stage sequentially for a limited period to provide a respective interim frequency, and wherein a frequency related to the interim frequency, or a reference frequency, is stored via a delay line and applied as an offset frequency to the next simulated stage and within the respective period.

According to a further aspect of the present invention there is provided a frequency synthesiser including a phase-locked loop comprising a voltage controlled oscillator, a mixer to one input of which the output of the voltage controlled oscillator is applied, a fixed ratio divider to which the output of the voltage controlled oscillator is also applied, a delay line arranged between the output of the fixed ratio divider and another input of the mixer whereby to provide an offset frequency signal related to the output of said voltage controlled oscillator, a variable modulus divider having an input connected to an output of the mixer, a phase/frequency detector connected to an output of the variable modulus divider, a reference frequency source connected to the phase/frequency detector, a loop filter connected between an output of the phase/frequency detector and the first voltage controlled oscillator, and means for varying the modulus of the variable modulus divider in accordance with a predetermined sequence of values, whereby each value is held for a time period equal to the delay time of the delay line, and repeating the sequence, the output frequency of the voltage controlled oscillator at the end of each sequence being a predetermined frequency.

According to another aspect of the present invention there is provided a frequency synthesiser including a voltage controlled oscillator, first and second variable modulus dividers connectible to an output of the voltage controlled oscillator, a phase/ frequency detector having one input connected to the output of the first divider, a reference frequency source, a mixer having inputs connected to the reference frequency source and the second divider, a two-position switch, the mixer output being connected to a fixed ratio divider input in one position of the switch, the output of the fixed ratio divider being connected via a delay line to another input of the detector, whereby to provide an offset frequency signal therefor which is related to the output of said voltage controlled oscillator, the reference source being directly connectible to the input of the fixed ratio divider in the other position of the switch, the detector output being connectible to the voltage controlled oscillator to control the output thereof to a corresponding frequency, means for varying the modulus of the dividers in accordance with a predetermined sequence of values, whereby each value is held for a time period equal to the delay time of the delay line, and for repeating the sequence, the value set in the second divider being one step in the sequence ahead of the value set in the first divider at any time, the modulus varying means being such as to change the switch to its second position during the last step in each sequence for the first divider whereby to provide an offset frequency signal for the detector which is related to the reference frequency for the first step of each sequence for the first divider, the output frequency of the voltage controlled oscillator at the end of each sequence being a predetermined frequency.

According to yet another aspect of the present invention there is provided a frequency synthesiser including a controllable signal source, a mixer, means to connect each of a sequence of fixed frequency values generated by the source in turn and for a time period equal to the delay time of the delay line to an input of the mixer and to repeat the sequence, a filter whose input is connected from the mixer output, a delay line whose input is connected from the mixer output, a divider whose input is connected to the delay line output, the output of the divider being connected to another input of the mixer, via a first two-position switch in one position thereof, to provide an offset frequency related to the interim frequency at the delay line output, the switch being controlled in dependence on the sequence whereby it is in the one position for each frequency value in the sequence other than the first frequency value thereof, and being in the other position for the first frequency value, the output frequency at the delay line output for the first frequency value in each sequence, other than the first sequence, being a predetermined frequency.

Embodiments of the present invention will now be described with reference to the accompanying drawings, in which: Figure lisa known simple form of indirect frequency synthesiser; Figure 2 is another known form of indirect frequency synthesiser; Figure 3 shows, schematically a known multi-loop synthesiser; Figure 4shows a block circuit diagram of a basic form of frequency synthesiser according to the present invention; Figure 5 illustrates the one form of operation of the arrangement of Figure 4; Figure 6 illustrates another form of operation of the arrangement of Figure 4; Figure 7 shows a block circuit diagram of a more specific form of frequency synthesiser than Figure 4, which synthesiser is applicable to U.H.F. frequencies;; Figure 8 illustrates the operation of the arrange- ment of Figure 7; Figure 9 shows a block circuit diagram of a direct frequency synthesiser according to the present invention, and Figure 10 illustrates the operation of the arrangement of Figure 9.

In the simple form of known frequency synthesiser shown in Figure 1 the output of a voltage controlled oscillator (V.C.O.) 1 is divided by a digital frequency divider 2, the division factorn of which can be set as required. The output of the divider 2 is applied to a phase detector 3 together with a reference frequency 3 obtained from a reference oscillator 4. The phase detector output is applied, via a loop filter 5, to the voltage control connection of the voltage controlled oscillator 1. By way of example, if the value of n is set to 90 and the reference frequency is 100 KHz, then when the frequency of the voltage controlled oscillator is 9 MHz the divided voltage controlled oscillator output and the reference frequency will be equal.

The output of the phase detector will be proportional to the phase difference and can be arranged to correct for any tendency of the voltage controlled oscillatorfrequencyto drift, thus locking the oscillator to 9 MHz. There is thus provided a phase-locked loop. If the divisional ration is changed to 91, then the oscillator will lock to 9.1 MHz.

In a modified arrangement of the basic synthesiser outlined above additional circuitry (in the inner dashed box) is provided to include an offset to the synthesised frequency, proportional to an input frequencyf2, as shown in Figure 2. In the arrangement of Figure 2, the output f, of a V.C.O. 10 is divided by a divider 11 and the resultant frequency is compared with a reference frequency frfrom a reference oscillator 12 in a phase detector 13. The difference signal is fed via a loop filter 14 to a second V.C.O. 15, running at frequency f3. The output of V.C.O. 15 is applied as one input to a second phase detector 16. The output of V.C.O. 10 is also applied to a mixer 17 where it is mixed with an offset frequency (f2).The resultant signal from mixer 17 is fed to the other input of phase detector 16, the output signal of which is used as a control signal for V.C.O. 10. In this arrangementf, = n x fr and f3 = (n X fr) + f2. For example, ffr = 100 KHz and n = 91 then f, = 9.1 MHz.Assumingf2= 1.1 MHzthenf3= 10.2MHz.

If the output f3 of the synthesiser shown in Figure 2 is divided by 10 and fed to a further similar synthesiser as the offset frequency h for that further synthesiser, then a decade of resolution can be achieved. For example, consider the arrangement of Figure 3 in which six synthesiser blocks 21 to 26 are cascaded, each block being the equivalent of that part of Figure 2 shown within the outer dashed box.

In each case, except the extreme left block, the offset frequency h is the f3 output of the previous block divided by 10. All the blocks share the same reference frequency oscillator 20. In block 21, n = 9 so that the output f3 = 0.9 MHz. When divided this provides an offsetfrequencyf2 = 0.09 MHzforblock 22, in which n = 6. The output f3 from block 22 is thus 0.69 MHz, which gives an offset frequency f2 = 0.069 MHzfor block 23 and soon. Thus if n in the six blocks is 9, 6, 5, 1,3 and 7 respectively, the final output frequency from block 26 will be 0.731569 MHz.

The multi-stage arrangement of Figure 3 thus comprises a multi-loop (phase-locked loops) indirect frequency synthesiser, which of necessity employs large amounts of circuitry by virtue of employing a plurality of offset synthesiser circuits.

Our co-pending Application No. 7924877 (Serial No. 2055519) (D.F.G. Dwyer 5-2-1) discloses a synthesiser arrangement which employs a single offset synthesiser circuit, as shown in Figure 2, to produce as many decades of resolution as are required. In this known synthesiser arrangement the divider 11 is programmable and automatically and repeatedly stepped through a sequence of division ratios.

The output f3 from V.C.O. 15 is fed to a frequency increment store comprising, in series, an incremental phase detector, a first sample and hold circuit and an incremental voltage controlled oscillator. The output of the incremental V.C.O. is fed back to the incremental phase detector and to a divide-by-ten circuit, whose output becomes the offset frequency for mixer 17. The output f3 from V.C.O. 15 is also fed to an output frequency store comprising, in series, an output phase detector, a second sample and hold circuit and an output voltage controlled oscillator, the output of which is fed back to the output phase detector. The first and second sample and hold circuits are operated under the control of the same control circuit that sets the division ratio of divider 11.The first sample and hold circuit is operated after each step in the division sequence, whereas the second sample and hold circuit is operated at the end of each sequence and is such as to hold the output of the frequency synthesiser until the end of the next sequence.

The arrangements of the present invention as illustrated in Figures 4 to 10 produce a required output frequency in a somewhat similar basic mannerto that disclosed in our co-pending application, that is by simulating each loop of a multi-loop system sequentially, but with greatly simplified circuitry which still results in high accuracy synthesis.

The basic synthesiser circuit according to the present invention shown in Figure 4 comprises two similar voltage controlled oscillators V.C.O. 1 and V.C.O. 2, switches 29,30 and 31 having switching positions A and B and controlled by a switch control 32, a subtractive mixer 33, a frequency divider 34, a delay line 35, a frequency divider 36, a phase/ frequency detector 37, a source of reference frequency (reference oscillator) 38, a low-pass loop filter 39, a sample/hold circuit 40, a sequence generator 41 and a set frequency circuit 42. The delay line may, for example, comprise an acoustic delay line, such as a surface acoustic wave device.

The voltage controlled oscillator V.C.O. 1, variable modulus divider 36, phase/frequency detector 37, reference frequency source 38 and loop filter com prise, when switches 30 and 31 are in switching position A and when mixer 33, switch 29, divider 34 and delay line 35 are omitted, a single digital phase-locked loop. The division ratio of divider 36 can be set to different values in sequence in accordance with instructions generated by sequence generator 41 in response to a desired frequency set in circuit 42. See the following examples. In order that the single phase-locked loop can function as (simulate) a multi-loop synthesiser, for each division ratio of divider 36 a suitable offset frequency must be generated. This is achieved by divider 34 and delay line 35 in combination with mixer 33 when switch 29 is in position A.The division ratio set in divider 36 is maintained there for a time period equal to the delay T provided by delay line 35. The output frequency f5 of V.C.O. 1 is supplied to one input of mixer 33 and to divider 34. The output frequency f6 of dividier 34 is delayed by time X in delay line 35 and supplied to the other input of mixer 33, by which time the division ratio of divider 36 and the output frequency of V.C.O. 1 have been changed and the next loop of a multi-loop system is being simulated.

Thus the offset signal required for each loop simulated is obtained by dividing and delaying the frequency signal of the preceding loop simulated.

The output frequency f7 of mixer is divided by divider 36 compared with a reference frequency in phase detector 37 and via loop filter 39 is applied to control V.C.O. 1. When the divider 36 has been set to the last division ratio of a sequence and V.C.O. 1 has a corresponding output frequency f8, switches 29, 30 and 31 are switched by control 32 to switch position B, thus V.C.O. 2 is locked via sample/hold circuit 40 to produce a continuous output with frequency f8.

Switches 29,30 and 31 are then reset to position A and V.C.O. 1 resimulates each of the loops again in accordance with the instructions of sequence generator 41 to generate another frequency output f8, which is then supplied as a continuous output by V.C.O. 2 and so on. V.C.O. 2 comprises a storage voltage controlled oscillator.

Thus with the system synthesising in decade steps, for every synthesis sequence each decade generated is of increasing significance. V.C.O. 2 is locked at the most significant decade while V.C.O. 1 performs the functions of simulating all other decades sequentially.

Figure 5 illustrates the operation of the arrangement of Figure 4, with a division ratio of ten provided by divider 34, a reference frequency of 1 MHz, the division ratio n of 36 being settable between zero and nine, and a frequency to be synthesised of 5.33106 MHz. The sequence generator 41 sets n = 6 (the least significant digit of the required frequency) in a first step for a time between 0 and T. Since there was no preceding value for f5 (assuming the operation is from start-up) f7 and f5 are both 6 MHz. In the time period between T and 2t, n = O, f6 is 0.6 MHz and thus the synthesiser frequency f5, which is (f6 + f7), is 0.6 MHz.During the sixth step, between time period 5t and 6r, f5 is the required frequency 5.33106 MHz, the switch positions are changed to B and V.C.O. 2 is locked tio f8 which is then the required frequency.

The frequency to be synthesised can alteratively be built up in a binary or mixed number base sequence. In the case of a binary synthesiser only two values of n, the division ratio of divider 36, are required together with a fixed division ratio of two for divider 34, but twenty steps would be required to achieve a resolution of one part per million.

Figure 6 illustrates the use of a mixed number base sequence for division ration. The selection of a suitable series of division ratios for a limited number of frequencies can be accomplished by simple arithmetic operations carried out for example on a programmable calculator or computer and stored in a PROM (programmable read only memory). Alternatively, a single chip processor could be incorporated within the synthesiser to carry out this and other house-keeping functions. In the Figure 6 example the reference frequency is 1MHz, the delay time T iS 631l seconds, the division ratio of divider 34 is ten, the variable division ratio n of divider 36 is between thirty and sixty and the frequency to be synthesised is 45.678 MHz.

The sequence shown in Figure 6 will be repeated indefinitely at an update rate of 3.96 KHz corresponding to the reciprocal of the time taken to complete four steps lasting 631l seconds. In the example shown in Figure 6 the continuous output V.C.O. 2 is assumed to lock precisely within the fourth step.

This is not essential, however, and several sequences can be allowed for this to occur.

Figure 7 shows an alternative synthesiser arrangement according to the present invention. The arrangement of Figure 7 is similar to that of Figure 4, except that the offset frequency is introduced through the reference chain, and the same reference numerals are employed when applicable. A divider 50 is arranged to divide the output of V.C.O. 1 by the number corresponding to the step ahead of divider 36. That is when divider 36 is dividing by the ratio for step 1, divider 50 is dividing by the ratio for step 2.

Using this arrangement three steps are necessary in each sequence in order to generate a frequency of the required resolution.

Figure 8 illustrates the synthesis of a signal frequency 309.025 MHz with the arrangement of Figure 7 in which the reference frequency is 200 MHz, the output frequency range of V.C.O. 1 and V.C.O. 2 is to be 225 - 400 MHz with a channel spacing of 25 KHz, a stabilisation time to + 500 Hz from any channel of 1 oxy seconds and a switching rate of multiples of 1 00u seconds. The sequence generator 41 is such as to set values of n between 100 and 200 and divider 34 has a division ratio of one hundred. Whilst, for example, divider 36 is dividing by 125 (step 1) divider 50 is dividing by 150 (step 2).

To provide an un-offset reference for step 1, the divider 34 is switched to the 200 MHz reference source 38 during step 3. A step time T of 33 3 seconds will result in a tota cycle time of 1 00u seconds. As well as a loop filter 39, a sample and hold circuit 51 is employed. Locking occurs when f5 = nf7. The mixer 52 is additive.

The variety of possible synthesis strategies is increased by the opportunity to generate frequencies using a greater number of simulated states than would otherwise be practical. In a simple implementation the choice of strategy chosen to meet a particular requirement is limited by the stabilisation timeTofV.C.O. 1 and the time t. The maximum number of simulated loops available for synthesis will be T/T. In the Example of Figure 8, a maximum of 10 seconds would be available for T, however this constrain could be removed, for example by the application of 'hold' on V.C.O. 1 for a period following stabilisation.

The arrangements of the present invention which have been described above can be supplied to spread spectrum communication, in which case the storage voltage controlled oscillatorV.C.O. 2 is not required. The series of frequencies generated by V.C.O. 1 and each held for time T will be a pseudo- random sequence provided that the sequence of numbers n applied is also pseudo-random. The advantage of this system lies in the fact that each frequency generated is dependent not only on the pseudo-random number applied during its generation but also with reducing significance on the previous numbers applied, thus the frequencies generated have potentially infinitesimal spacings.

This system gives continuous spectrum fill over a band defined by the values of n. The system is simple to implement and the frequencies generated are theoretically exact. One means of applying modulation would be by offsetting the reference at a bit rat equal to 1/l.

Thus there is provided a method of synthesising desired frequencies with a single loop circuit arrangement which is caused to operate as, or simulate, a multi-loop synthesiser and thus employs considerably less circuitry than a multi-loop synth esiserwhilst providing high accuracy. The circuits described above operate in an alternative manner to the synthesiser disclosed in our co-pending Application No. 7924877 referred to above, and have the advantages of further simplification and ease of implementation thereover.

Whereas the invention has so far been described with reference to indirect synthesis it is alternatively applicable to direct synthesis. Figure 9 illustrates one example of a direct frequency synthesiser, which comprises a reference frequency (standard) source 60 from which a fixed frequency generator 51 derives a range of frequencies, shown as 97 to 107 MHz, for operation according to Figure 10 to synthesise a frequency of 118.275 MHz. The source 60 and the generator 61 comprise a controllable signal source. A selector 62 is arranged to connect selected derived frequencies f7 in turn to a mixer 63 which adds an offset frequency f6 thereto.

The output of mixer 63 is applied to a filter 64 and a delay 65 in series. The delay line 65 delays the output signal f8 by a time which is equal to the duration of each step in Figure 10, that is the time for which the selector 62 connects a particular frequency f7 to the mixer 63. The output signal f8 available at the delay line output terminal during step 2 is divided by ten in a divider 66 and, when a switch 67 is in position A, applied as the offset frequency f6 to mixer 63.

During step 1 the switch 67 is in position B and no offset frequency is applied to the mixer 63. In steps 2, 3 and 4 the switch 67 is in position A and an offset frequency, comprising the divider delayed output signal of the mixer for the preceding step, is applied to the mixer.

With the circuitry of Figure 9 described so far, the complete frequency to be synthesised (118.275 MHz) is only available at the delay line output during step 1 of each sequence of steps (other than the first sequence), that is when switch 67 is in position B.

In order to provide a continuous synthesised frequency as the previous embodiments, a frequency storage loop 68 is connected to the output of the delay line via a two position switch 69, when the latter is in position B. The frequency storage loop 68 is similar to that used in the above described indirect synthesisers, and comprises a phase detector 70, a sample/hold circuit 71, a loop filter 73 and a voltage controlled oscillator (V.C.O.) 174. The sample/hold circuit 71 is in the "hold" mode when the switch is in the B position. The switches 67, 69 and 72 are controlled by a common switch control (not shown) which also controls the selector 62.

Thus when the complete frequency f8 has been synthesised the switches 67, 69 and 72 are in position B (Step 1) so that the complete frequency is applied to one output of phase detector 70. The sample/hold circuit is in the sample mode and the V.C.O. 74 adjusted as necessary as in the previously described arrangements to produce an output equal to the complete synthesised frequency. For the following steps 2,3 and 4 the switches 67,69 and 72 are in position A, the sample/hold circuit 71 is in the hold mode and the complete synthesised frequency is continuously available at the output ofV.C.O. 74.

This complete synthesised frequency is updated during step 1 of every succeeding sequence of steps.

The delay line 65 and the filter 64, shown within the smaller dashed box of Figure 9, may be combined into a single element by the application of S.A.W. (Surface Acoutic Wave) technology.

Claims (19)

1. A method of synthesising a desired frequency comprising simulating the operation of a conventional multi-stage synthesiser one stage at a time by simulating each stage sequentially for a limited period to provide a respective interim frequency, and wherein a frequency related to the interim frequency, or a reference frequency, is stored via a delay line and applied as an offset frequency to the next simulated stage and within the respective period.

2. A method as claimed in claim 1 in which the synthesis is direct and in which the output of a controllable signal source is mixed and divided.

3. A method as claimed in claim 1, wherein the synthesis is indirect and wherein the output of a controllable signal source is fed to a divider in a phase/frequency lock loop, each stage being a phase lock loop.

4. A method as claimed in claim 3 wherein in each stage the output of the controllable signal source is fed to the divider after mixing with a respective offset signal, which respective offset signal comprises the output of the controllable signal source from the preceding stage after division by a fixed ratio and storage in the delay line.

5. A method as claimed in claim 3 or 4 wherein the division ratio of the divider is variable and wherein the frequency of the output of the divider is compared with a reference frequency in a phase/ frequency detector before being fed to the controllable signal source.

6. A method as claimed in claim 5, wherein when the desired frequency has been simulated in one sequence of stages of the output of the phase/ frequency detector is applied to a storage controllable signal source via a sample and hold circuit, which storage controllable signal source supplies an output signal of the desired frequency until up-dated by the desired frequency as simulated in the next sequence of stages.

7. A method as claimed in claim 6 wherein the value of the division ratio of the divider is varied in accordance with a predetermined sequence by a sequence generator, each value of the division ratio being maintained for the predetermined time, and wherein the sequence generator controls a switch connecting the output of the phase/frequency detector to the controllable signal source or the storage controllable signal source.

8. A method as claimed in claim 3, wherein in each stage the output of the divider is compared with an offset frequency in a phase/frequency detector, the output of which is connectible to the controllable signal source for one position of a switch and connectible to a storage controllable signal source for another position of the switch, wherein for simulation the division ratio of the divider is set for each stage in accordance with a predetermined sequence of values each of which is held for the limited period, wherein the offset frequency for one stage is obtained during the preceding stage by dividing the then interim frequency by the division ratio associated with the one stage, mixing the resiting frequency with a reference frequency, dividing the mixed frequency by a fixed ratio and storing the divided mixing frequency in the delay line until the next stage, and wherein when the desired frequency has been simulated in one sequence of stages the output of the phase/frequency detector is connected to the storage controlled signal source, which supplies an output signal of the desired frequency until up-dated by the desired frequency as simulated in the next sequence of stages.

9. A method as claimed in any one of the preceding claims wherein the delay line is an acoustic delay line.

10. A frequency synthesiser including a phaselocked loop comprising a voltage controlled oscillator, a mixer to one input of which the output of the voltage controlled oscillator is applied, a fixed ratio divider to which the output of the voltage controlled oscillator is also applied, a delay line arranged between the output of the fixed ratio divider and another input of the mixer whereby to provide an offset frequency signal related to the output of said voltage controlled oscillator, a variable modulus divider having an input connected to an output of the mixer, a phase/frequency detector connected to an output of the variable modulus divider, a reference frequency source connected to the phase/frequency detector, a loop filter connected between an output of the phase/frequency detector and the first voltage controlled oscillator, and means for varying the modulus of the variable modulus divider in accord ante with a predetermined sequence of values, whereby each value is held for a time period equal to the delay time of the delay line and repeating the sequence, the output frequency of the voltage controlled oscillator at the end of each sequence being a predetermined frequency.

11. A frequency synthesiser as claimed in claim 11, including first, second and third two-position switches, a second voltage controlled oscillator and a sample and hold circuit, wherein in one position of the first switch the said voltage controlled oscillator is connected to the one mixer input, wherein in the other position of the first switch the second voltage controlled oscillator is connected to the one mixer input, wherein in one position of the second switch the detector output is connected in the phase-locked loop to control the said voltage controlled oscillator, wherein in the other position of the second switch the detector output is connected via the sample and hold circuit to control the second voltage controlled oscillator, wherein the output of the voltage controlled oscillator is applied to the fixed ratio divider in one position of the third switch and disconnected therefrom in the other position of the third switch, and wherein the modulus varying means is such as to change the first, second and third switches to their other positions during the last step of each sequence whereby the output of the second voltage controlled oscillator is locked to the predetermined frequency synthesised by the phase-locked loop during one sequence of values for the variable divider whilst the phase-locked loop resynthesises the predetermined frequency from the following sequence of values.

12. Afrequency synthesiser including a voltage controlled oscillator, first and second variable modulus dividers connectible to an output of the voltage control led oscillator, a phase/frequency detector having one input connected to the output of the first divider, a reference frequency soaurce, a mixer having inputs connected to the reference frequency source and the second divider, a two-position switch, the mixer output being connected to a fixed ratio divider input in one position of the switch, the output of the fixed ratio divider being connected via a delay line to another input of the detector, whereby to provide an offset frequency signal therefor which is related to the output of said voltage controlled oscillator, the reference source being directly connectible to the input of the fixed ratio divider in the other position of the switch, the detector output being connectible to the voltage controlled oscillator to control the output thereof to a corresponding frequency, means for varying the modulus of the dividers in accordance with a predetermined sequence of values, whereby each value is held for a time period equal to the delay time of the delay line, and for repeating the sequence, the value set in the second divider being one step in the sequence ahead of the value set in the first divider at any time, the modulus varying means being such as to change the switch to its second position during the last step in each sequence for the first divider whereby to provide an offset frequency signal for the detector which is related to the reference frequency for the first step of each sequence for the first divider, the output frequency of the voltage controlled oscillator at the end of each sequence being a predetermined frequency.

13. A frequency synthesiser as claimed in claim 12, including second and third two-position switches, a second voltage controlled oscillator and first and second sample and hold circuits, wherein the output of the said voltage controlled oscillator is connected to the first variable modulus divider in one position of the second two-position switch, wherein the output of the detector is connected to the said voltage controlled oscillator via the first sample and hold circuit when the third switch is in one position and connected to the second voltage controlled oscillator via the second sample and hold circuit when the third switch is in the other position, and wherein the output of the second voltage controlled oscillator is connected to the input of the first variable modulus divider when the second switch is in the other position, the second and third switches being changed between their one and other positions simultaneously with the changing of the first switch between its one and other position, the output of the second voltage controlled oscillator being locked to the predetermined frequency synthesised by the phase-lock loop including the said voltage controlled oscillator during one sequence of values for the ratio of the first divider whilst the phase-lock loop resynthesises the predetermined frequency from the following sequence of values.

14. A frequency synthesiser including a controllable signal source, a mixer, means to connect each of a sequence of fixed frequency values generated by the source in turn and for a time period equal to the delay time of the delay line to an input of the mixer and to repeat the sequence, a filter whose input is connected from the mixer output, a delay line whose input is connected from the mixer output, a divider whose input is connected to the delay line output, the output of the divider being connected to another input of the mixer, via a first two-position switch in one position thereof, to provide an offset frequency related to the interim frequency at the delay line output, the switch being controlled in dependence on the sequence whereby it is in the one position for each frequency value in the sequence other than the first frequency value thereof, and being in the other position for the first frequency value, the output frequency at the delay line output for the first frequency value in each sequence, other than the first sequence, being a predetermined frequency.

15. A frequency synthesiser as claimed in claim 14 and including storage means whereby to derive a continuous output at the predetermined frequency.

16. Afrequencysynthesiserasclaimed in claim 15 wherein the storage means is connectible to the delay line output via a second two-position switch and includes a voltage controlled oscillator at whose output the predetermined frequency is continuously available, the second switch being controlled in dependence on the sequence whereby to connect the delay line output to the storage means for the first frequency value in each sequence, and to disconnect the delay line output from the storage means for all other frequency values in each sequence.

17. A frequency synthesiser as claimed in claim 16, wherein the storage means further includes a phase detector having one input connected to the output of the voltage controlled oscillator and another input connectible to the delay line output via the second switch, a sample/hold circuit connected from the output of the phase detector, and a loop filter connected between the sample/hold circuit and the voltage controlled oscillator, the sample/hold circuit being in the "hold" made when the first switch is in the one position and the "sample" mode when the first switch is in the other position.

18. A method of synthesising a desired frequency substantially as herein described with reference to and as illustrated in Figures 4 to 6, Figures 7 and 8 or Figures 9 and 10 of the accompanying drawings.

19. A frequency synthesiser substantially as herein described with reference to and as illustrated in Figures 4to 6, Figures 7 and 8 or Figures 9 and 10 of the accompanying drawings.