GB2097188A

GB2097188A - Field effect semiconductor device

Info

Publication number: GB2097188A
Application number: GB8211030A
Authority: GB
Original assignee: GTE Laboratories Inc
Current assignee: Verizon Laboratories Inc
Priority date: 1981-04-17
Filing date: 1982-04-15
Publication date: 1982-10-27
Also published as: JPS57181171A; DE3213772A1; IT8220692A0; IT1150836B

Abstract

A high frequency, high power field effect semi-conductor device adapted for use in the common gate circuit configuration includes an ohmic source region (14) and an ohmic drain region (12) formed in the top surface of a high resistivity layer (10) of semiconductor material. A planar gate region (16), including a rectifying gate junction (18), is formed on the bottom surface of the high resistivity layer. A current barrier (28), formed in the high resistivity layer between the source and drain regions, restricts current flowing between the source and drain regions to a portion of the high resistivity layer near the gate junction. The device exhibits unsaturated operating characteristics similar to those of the static induction transistor. The current barrier may comprise an unfilled V- shaped groove, a thick locally oxidized region, or a very high resistivity region produced by implantation of hydrogen or by radiation damage of the semiconductor. The gate may be a PN junction or a Schottky contact. <IMAGE>

Description

SPECIFICATION Field effect semiconductor device This invention relates to high frequency field effect semiconductor devices and, more particularly, to a field effect semiconductor device structure adapted for use in the common gate configuration.

The static induction transistor is a field effect semiconductor device which exhibits excellent high power and high frequency capabilities. These devices are characterized by relatively short, high resistivity channels and operate with the channel depleted of carriers.

The current-voltage characteristics of the static induction transistor are similar to those of an unsaturated triode. The conventional static induction transistor utilizes a vertical geometry. Source and drain contacts are placed on opposite sides of a thin high resistivity layer of one conductivity type. Gate regions of the opposite conductivity type are diffused into the high resistivity layer on opposite sides of the source. When a reverse bias voltage is applied to the gate junctions, the depetion region associated therewith extends underneath the source and pinches off the channel between the source and drain.

In order to achieve good field effect transistor performance at high frequencies, it is frequently advantageous to ultilize a common gate circuit configuration. The gate electrode of the transistor is connected to circuit ground, which is commonly the chassis on which the circuit is mounted. Power semiconductor devices require thermal connection to a heat sink for operation at or near their rated power level. Typically, the case of the power device is thermally coupled to the equipment chassis. However, the drain electrode of a static induction transistor having vertical geometry is internally connected to the case of the device. Therefore, the device must be electrically insulated from the chassis. The requirement for electrical insulation between the semiconductor device and the equipment chassis makes heat sinking of the semiconductor device difficult.

It is, therefore, desirable to provide a field effect semiconductor device with good high frequency, high power performance characteristics adapted for use in the common gate configuration.

According to the present invention, there is provided a field effect semiconductor device comprising a high resistivity layer of semiconductor material of one conductivity type with a low resistivity ohmic drain region and a low resistivity ohmic source region formed on a first surface thereof and a gate region including a rectifying gate junction formed on a second surface of the high resistivity layer.

The high resistivity layer between the source and the drain regions defines a channel for conducting current therebetween. The yate junction adjacent the channel controls the current in the channel responsive to a bias voltage applied to the gate junction. The device further includes means disposed between the source and the drain regions for restricting current in the channel to a portion of the high resistivity layer near the gate junction whereby the current can be controlled by the gate voltage. The gate region can include a layer of semiconductor material of the opposite conductivity type contiguous to the second surface of the high resistivity layer. Alternatively, the gate region can include a first metal layer which forms a metal-to-semiconductor rectifying junction contiguous to the second surface of the high resistivity layer.The means for restricting current can include a groove or depression in the first surface of the high resistivity layer.

The invention is illustrated by way of example in the.accompanying drawings, in which; Figure 1 is a schematic cross-sectional view of a field effect semiconductor device according to the present invention; Figure 2 is a graph illustrating the drain current versus drain voltage characteristics of a field effect semiconductor device according to the present invention; Figure 3 is a cross-sectional view of a field effect semiconductor device according to the present invention illustrating a V-groove current barrier; Figures 4 and 5 are cross-sectional views illustrating the fabrication of the field effect semiconductor device shown in Fig.3; Figure 6 is a cross-sectional view of another embodiment of a field effect semiconductor device according to the present invention;; Figures 7 and 8 are cross-sectional views illustrating the fabrication of the field effect semiconductor device shown in Fig. 6; Figure 9 is a cross-sectional view illustrating an alternative gate structure which can be used in the field effect semiconductor device according to the present invention; and Figure 10 is a top view of a field effect semiconductor device according to the present invention illustrating an interdigitated source and drain structure.

In the figures, the various elements are not drawn to scale. Certain dimensions are exaggerated in relation to other dimensions in order to present a clearer understanding of the invention.

For a better understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the following disclosure and appended claims in connection with the above-described drawings.

A field effect semiconductor device according to the present invention is shown by way of example in Fig. 1. A high resistivity layer 10 of semiconductor material of one conductivity type has a low resistivity ohmic drain region 12 and a low resistivity ohmic source region 14 formed in a first, or top, surface thereof. The drain region 12 and the source region 14 are typically formed as spacedapart, parallel stripes on the high resistivity layer 10. A planar gate region 16, including a rectifying gate junction 18, is contiguous to a second, or bottom, surface of the high resistivity layer 10. The gate region 16 generally covers the bottom surface of the high resistivity layer 10 opposite the drain region 12 and the source region 14. A drain contact 20 and a source contact 22 are formed on the drain region 12 and the source region 14, respectively.A gate contact 24 is formed on the gate region 16. The portion of the high resistivity layer 10 between the source region 14 and the drain region 12 defines a channel 26 for conducting current between the source region 14 and the drain region 12. A current barrier 28, configured to restrict the current in the channel 26 to a portion of the high resistivity layer 10 near the gate junction 18.

is located in the upper portion of the high resistivity layer 10 between the source region 14 and the drain region 12. The current barrier 28 is typically formed as an elongated element parallel to the drain region 12 and the source region 14.

The operation of the device shown in Fig. 1 is described with reference to the operating characteristics shown in Fig. 2. As noted hereinabove, the static induction transistor is characterized by a short channel length and a high resistivity channel and exhibits triode-like operating characteristics. The device shown in Fig. 1, while having a totally different geometry from a static induction transistor, exhibits operating characteristics similar to those of the static induction transistor. In normal operation, a reverse bias voltage is applied to the gate contact 24. The reverse biased gate junction 18 has an associated depletion layer which extends into and pinches off the channel 26 and creates a potential barrier to current flow.When the source-to-drain and gate-to-drain distances are sufficiently small, the height of the potential barrier can be modified by changing either the gate potential or the drain potential. The result is a non-sa turating operating characteristic such as that shown in Fig. 2. Drain current is plotted on the vertical axis in Fig. 2 as a function of drain voltage on the horizontal axis for various values of gate voltage. Curve 30 represents a low value of reverse bias gate voltage while curves 32 and 34 represent successively higher values of reverse bias gate voltage. It can be seen that increasing the value of the reverse bias gate voltage has the general effect of increasing the drain voltage which must be applied to the device in order to cause drain current flow.

The function of the current barrier 28 can be described with reference to Fig.1. During normal operation, current flows between the source region 14 and the drain region 1 2 through the channel 26, as indicated by the arrows in Fig.1. In the absence of the current barrier 28, the flow would be concentrated near the upper surface of the high resistivity layer 10 and control of the current by the gate region 16 would be relatively difficult.

The current barrier 28 causes the current flowing through the channel 26 to follow a path through the high resistivity layer 10 around the current barrier 28 and close to the gate junction 18. Thus, the current passes through a portion of the channel 26 in which the gate region 16 has a high degree of influence and the gate region 16 can control current flowing in the channel 26 when a relatively small reverse bias voltage is applied thereto.

A specific embodiment of a field effect semiconductor device according to the present invention is illustrated in Fig. 3. The current barrier 28 is a groove 40 formed in the first surface of the high resistivity layer 10 between the source region 14 and the drain region 12. Thus, current flow through the channel 26 is restricted to a portion of the high resistivity layer 10 near the gate junction 18.

The fabrication of the device shown in Fig.

3 is illustrated in Figs. 4 and 5. The substrate is a silicon semiconductor wafer of one conductivity type and of moderate resistivity. The substrate forms the gate region 16 of the device and can have a resistivity of about one to five ohm centimeters. The epitaxial, high resistivity layer 10 of the opposite conductivity type is grown on the substrate, or gate region 16. In the present embodiment, the gate region 16 provides mechanical support for the device and can be about 200 micrometers in thickness while the high resistivity layer 10 is about 5 to 12 micrometers in thickness and has a resistivity of at least 20 ohm centimeters. The thickness of the high resistivity layer 10 depends upon the required breakdown voltage and the maximum operating frequency of the device. Since the difference between the resistivity of the substrate and the resistivity of the high resistivity layer 10 is relatively small, lattice mismatch is small and high quality dislocation-free layers can be grown without difficulty.

A silicon dioxide layer 42 is grown on top surface of the high resistivity layer 10 by known methods, such as exposing the semiconductor wafer to an oxygen and steam ambient at about 1100 C. In the next step, a source window 43, a drain window 44 and a current barrier window 45 are formed in the oxide layer 42 using conventional photolithographic techniques. Silicon nitrate is deposited and patterned to protect the source and drain windows 43, 44. A typical method of depositing the silicon nitrate is by chemical vapor deposition from ammonia and silane at about 800 C. The silicon nitride layers 46 protect the high resistivity layer 10 during formation of the current barrier in the current barrier window 45.

The groove 40 is formed in the first surface of the high resistivity layer 10 in the current barrier window 45. While grooves of any shape can be utilized to provide a current barrier, V-shaped grooves are typically utilized. V-shaped grooves can be conveniently etched in silicon monocrystals when the wafer has a surface orientation of (100). The mask is oriented in reference to the (110) wafer flat which is indicative of the (110) crystal direction. When an equimolar mixture of N2H4 and H20 is used, the etching process will produce self stopping grooves with an angle of 54.7 from the surface. The depth of the groove depends only on the etching window dimension. The depth of the V-shaped groove 40 in the device of the present invention is typically in the range of 30% to 70% of the thickness of the high resistivity layer 10.

Next, a second silicon dioxide layer, in reality a continuation of the growth of the silicon dioxide layer 42, is grown on the surface of the high resistivity layer 10. The additional silicon dioxide layer protects the surface of the groove 40. The silicon nitride layers 46 are then removed from the wafer to provide access to the source and drain windows 43, 44. The silicon nitride layer 46 can be removed by known methods, such as exposure to phosphoric acid at about 180 C or plasma etching. Referring again to Fig. 3, the shallow drain region 12 is formed in the drain window 44 and the shallow source region 14 is formed in the source window 43 by ion implantation or diffusion of impurities.The drain region 12 and the source region 14 have low resistivity and are of the same conductivity type as the high resistivity layer 10, thereby providing ohmic contacts to the high resistivity layer 10. Because short diffusion times are required, negligible impurity redistribution occurs at the gate junction 1 8.

Contact metal is deposited on the top surface of the wafer and the drain contact 20 and the source contact 22 are patterned using conventional photolithographic techniques. Finally, the bottom surface of the substrate is metallized, thus forming the gate contact 24.

In one example of a field effect semiconductor device according to the present invention, the high resistivity layer 10 is 6 to 8 micrometers in thickness. The source and drain regions are separated by about 4 micrometers and the source and drain windows are about 2 micrometers in width. The groove 40 is 1.5 micrometers wide and 2.5 micrometers deep.

Another embodiment of a field effect semiconductor device according to the present invention is shown in Fig. 6. A high resistivity layer 50 of semiconductor material of one conductivity type has a low resistivity ohmic drain region 52 and a low resistivity ohmic source region 54 formed in a first, or top, surface thereof. The drain region 52 and the source region 54 are typically formed as par alley stripes on the high resistivity layer 10. A planar gate region 56, including a rectifying gate junction 58, is contiguous to a second, or bottom, surface of the high resistivity layer 50. The gate region 56 generally covers the bottom surface of the high resistivity layer 50 opposite the drain region 52 and the source region 54. A drain contact 60 and a source contact 62 are formed on the drain region 52 and the source region 54, respectfully.A gate contact 64 is formed on the gate region 56.

The portion of the high resistivity layer 50 between the source region 54 and the drain region 52 defines a channel 66 for conducting current between the source region 54 and the drain region 52.

The device shown in Fig. 6 differs from the device shown in Fig. 3 principally in the configuration of the current barrier 28. In the device shown in Fig. 6, the current barrier 28 is a depression 70 in the high resistivity layer 50 between the drain region 52 and the source region 54. The depression 70 in the high resistivity layer, in effect, reduces the thickness of the channel 66 and causes current to flow through the channel 66 close to the gate junction 58. In the presence of the depression 70, the drain region 52 and the source region 54 are, in effect, elevated in relation to the remainder of the high resistivity layer 50.

The fabrication of the field effect semiconductor device shown in Fig. 6 is illustrated in Figs. 7 and 8. The epitaxial, high resistivity layer 50 of semiconductor material of one conductivity type is grown on a moderate resistivity substrate of semiconductor material of the opposite conductivity type. The substrate forms the gate region 56 of the device.

The resistivities and thicknesses of the high resistivity layer 50 and the substrate can correspond with those described hereinabove in connection with Fig. 3. Next, a thin layer of silicon nitride is deposited on the first or upper surface of the high resistivity layer 50.

The silicon nitride is masked and etched using convention photolithographic techniques so as to leave protective silicon nitride layers 76 over areas 77, 78 of the high resistivity layer 50. Next, the semiconductor wafer is oxidized and a thick silicon dioxide layer 80 is grown in unprotected areas. No oxide grows in the areas 77, 78 protected by the silicon nitride layer 76. The silicon dioxide layer 80 is permitted to grow to the extent that the high resistivity layer 50 is reduced in thickness by 30% to 70% in the unprotected areas of the wafer.

The silicon nitride layers 76 are removed from the areas 77, 78 and shallow, low resistivity regions of the same conductivity type as the high resistivity layer 50 are diffused or implanted in the areas 77, 78 ther eby forming the drain region 52 and the source region 54. Referring again to Fig. 6, metal is desposited over the upper surface of the wafer and the drain contact 60 and the source contact 62 are patterned using conventional photolithographic techniques. Finally, metal is deposited over the bottom surface of the substrate to form the gate contact 64.

The current barriers shown in the devices of Figs. 3 and 6 are formed by removing material from the upper surface of the high resistivity layer. An alternative approach is to form a region of very high resistivity within the high resistivity layer. Referring again to Fig. 1, when the current barrier 28 is a region of extremely high resistivity, the current in the channel 26 takes the path indicated by the arrows, having lower resistivity. The current barrier of very high resistivity can be formed by implanation of hydrogen, thus increasing the resistivity of the semiconductor material in the current barrier region, or can be formed by radiation damage of the semiconductor wafer.

An alternative gate region structure, which can be used in the field effect semiconductor devices illustrated in Figs. 3 and 6, is shown in Fig. 9. Only the gate region and part of the high resistivity layer are shown in Fig. 9. The device is constructed on a semiconductor wafer 90 of high resistivity monocrystalline silicon of one conductivity type. The source and drain regions and the current barrier are fabricated in wafer 90 as shown and described hereinabove in connection with Figs.

3-5 and 6-8. Then, the bottom surface of the wafer 90 is chemically thinned to the thickness required of the high resistivity layer of the device. The thinned wafer forms the high resistivity layer of the device. Next, a metal layer 92 such as aluminum, chromium, nickel or tungsten, which forms a Schottky barrier, or metal-to-semiconductor rectifying contact, is deposited on the bottom surface of the wafer 90. Finally, in order to provide a path of low thermal resistance from the device and to provide mechanical support for the device, a thick metal layer 94 is electroplated over the layer 92.

High power capability can be achieved in the field effect semiconductor device of the present invention by repeating the structure shown in Fig. 3 or Fig. 6 in an interdigitated structure. An interdigitated structure is illustrated in Fig. 10, which shows a top view of a portion of a device having the structure shown in Fig. 3. The drain contacts 20 and the source contacts 22 are formed as elongated strips which can be about 100 micrometers long. The grooves 40 are disposed between the drain contacts 20 and the source contacts 22. The drain contacts 20 are interconnected at one side of the device by a drain metallization 100. The source contacts 22 are interconnected at the opposite side of the device by a source metallization 102. Leads are connected to the relatively large metallizations 100, 102.The structure shown in Fig. 10 can be repeated many times to increase device power handling capability.

The field effect semiconductor devices described hereinabove are most conveniently and efficiently utilized in a common gate circuit configuration, that is, with the gate of the device connected to ground. The gate contact is connected directly to the case of the package, thereby providing good heat sinking and improving the maximum power dissipation of the device. When the device is required to be used in circuit configurations other than common gate, a thermally conductive isolator is employed for mounting the semiconductor chip into the package.

Thus there is provided by the present invention a field effect semiconductor device for high frequency, high power applications. The disclosed device is most advantageously utilized in a common gate circuit configuration.

The processing of the device is relatively simple.

While there has been shown and described what is at present considered the preferred embodiments of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the scope of the invention as defined by the appended claims.

Claims

1. A field effect semiconductor device comprising: a low resistivity ohmic drain region; a low resistivity ohmic source region; a high resistivity layer of semiconductor material of one conductivity type, said high resistivity layer including a first surface with said drain region and said source region formed therein such that said high resistivity layer between said source and said drain regions defines a channel for conducting current therebetween; a gate region including a rectifying gate junction formed on a second surface of said high resistivity layer adjacent to said channel for controlling the current in said channel responsive to a bias voltage applied to said gate junction; and means disposed between said source and said drain regions for restricting current in said channel to a portion of said high resistivity layer near said gate junction.

2. The field effect semiconductor device as defined in claim 1 wherein said means for restricting current includes a groove in said first surface of said high resistivity layer.

3. The field effect semiconductor device as defined in claim 2 wherein said groove is V-shaped and has a depth which is 30 to 70 percent of the thickness of said high resistivity layer.

4. The field effect semiconductor device as defined in claim 1 wherein said means for restricting current includes a depression in the first surface of said high resistivity layer, said depression reducing the thickness of said high resistivity layer between said source and said drain regions.

5. The field effect semiconductor device as defined in claim 4 wherein said depression has a depth which is 30 to 70 percent of the thickness of said high resistivity layer.

6. The field effect semiconductor device as defined in claim 1 wherein said means for restricting current includes a portion of said high resistivity layer near the first surface thereof having higher resistivity than the remainder of said high resistivity layer.

7. The field effect semiconductor device as defined in claim 1 wherein said gate region has sufficiently thickness to provide mechanical support for said device.

8. A field effect semiconductor device comprising: a low resistivity ohmic drain region; a low resistivity ohmic source region; a high resistivity layer of semiconductor material of one conductivity type, said high resistivity layer including a first surface with said drain region and said source region formed therein such that said high resistivity layer between said source and said drain region defines a channel for conducting current therebetween, said channel having sufficiently high resistivity and sufficiently short length to provide unsaturated drain currentvoltage characteristics; a planar gate region including a rectifying gate junction formed on a second surface of said high resistivity layer adjacent said channel for controlling the current in said channel responsive to a bias voltage applied to said gate junction; and current barrier means disposed between said source and said drain region and associated with the first surface of said high resistivity layer for restricting the current in said channel to a portion thereof near said gate region whereby said current can be controlled by the gate voltage.

9. The field effect semiconductor device as defined in claim 8 wherein said gate region includes a layer of semiconductor material of the opposite conductivity type contiguous to the second surface of said high resistivity layer and having lower resistivity than said high resistivity layer.

10. The field effect semiconductor device as defined in claim 9 wherein said layer of semiconductor material of the opposite conductivity type has sufficient thickness to act as a substrate which provides mechanical support for said device.

11. The field effect semiconductor device as defined in claim 10 wherein said high resistivity layer has a resistivity of at least 20 ohm centimeters.

12. The field effect semiconductor device as defined in claim 8 wherein said gate region includes a first metal layer, which forms a metal-to-semiconductor rectifying junction, contiguous to the second surface of said high resistivity layer.

13. The field effect semiconductor device as defined in claim 12 further including a second metal layer contiguous to said first metal layer, said second metal layer having sufficient thickness to provide mechanical support for said device and to provide a path of low thermal resistance from said device.

14. The field effect semiconductor device as defined in claim 13 wherein said high resistivity layer has a resistivity of at least 20 ohm centimeters.

15. A field effect semiconductor device substantially as described herein with reference to Fig. 3 or 6 of the accompanying drawings, or either one of Figs. 3 and 6 taken in conjunction with one or both of Figs. 9 and 10 of the accompanying drawings.

16. The features as herein described, or their equivalents, in any novel selection.