GB2095442A - Refreshing dynamic MOS memories - Google Patents

Abstract

In order to avoid having to inhibit access to a dynamic MOS memory during a refresh cycle, in its simplest embodiment the memory is formed by two blocks (10, 12) each with its own refresh counter (28, 30). By interleaving the addressing of the two blocks (10, 12), when access is being made to one block for reading/writing, the other block is being refreshed or is available to be refreshed, and vice versa. A fail safe timer is included to institute a refresh cycle in the event of one or other block not having been refreshed within a predetermined time, say 2 milliseconds. <IMAGE>

Description

SPECIFICATION Refreshing dynamic MOS memories The present invention relates to refreshing dynamic MOS memories, for example dynamic MOS RAMs, which may be used for example as frame stores.

With MOS memories information is stored as a charge between the gate and substrate of an MOS transistor. This charge will leak away and the information lost unless it is refreshed about every 2 milliseconds (mS). When writing-in or reading-out from an MOS memory of a matrix type then the row containing the data in question is automatically refreshed. However, there are occasions when memory blocks forming the memory are not accessed and a refresh cycle has to be applied to the entire memory.

In the case of the Intel 8202 Dynamic RAM Controller, an automatic refresh sequence is initiated by a refresh timer. The refresh timer instructs an arbiter, which decides on the priority of the possible external input signals, such as write, read and refresh, to the RAM, to apply a suitable input signal to a timing and control circuit which in turn steps a refresh counter which produces a row addressing signal which is applied viaa multiplexer to the RAM.

A drawback of this refreshing technique is that for the time dudng which the memory is being refreshed then access to the memory for reading and writing is inhibited. This means that the RAM cannot be exploited to its maximum and this has particular problems with high capacity stores such as frame stores when access to the memory and refresh requirements conflict.

It is an object of the present invention to be able to refresh a dynamic MOS memory in a manner which mitigates this conflict with existing memories.

According to the present invention there is provided a method of refreshing a dynamic MOS semiconductor memory formed by at least two memory blocks or at least two groups of memory blocks which, whilst one block or groups of blocks is being accessed, the other block(s) or group(s) of blocks is (are) being refreshed.

By means of the method in accordance with the present invention the refreshing of the memory does not inhibit access to the memory and in consequence a much greater access to the memory is possible than is possible with a unitary memory.

Furthermore in the case of processing picture information stored in a dynamic frame store then it is possible to ensure refreshing of all the information stored whilst only accessing part of it, e.g. when keyhole scanning a frame orzooming-in on a portion of a frame.

By interleaving the blocks or groups of blocks, for example by having odd-numbered addresses in one and even-numbered addresses in the other, the statistical probability of the successive access of alternate blocks or groups of blocks is maximised and thereby also the refreshing of the non-accessed block or group of blocks. In the event of there being no opportunity to refresh a block for a predetermined time a fail safe refresh sequence is initiated. This would only be necessary if for example even addresses only were accessed for more than approximately 93% of a 2 mS period.

The present invention also provides a dynamic MOS semiconductor memory comprising at least two memory blocks or at least two groups of memory blocks, each of the blocks or groups having a respective incrementing address counter providing a row address to its associated memory block or group and means for controlling the outputs of address counters so that when one of the blocks of groups of blocks is being accessed, the other block(s) or group(s) of blocks is (are) available for refreshing.

The present invention will now be described, by way of example, with reference to the single Figure of the accompanying drawing, which Figure illustrates a block schematic form a video frame store which is refreshable in accordance with the method of the present invention.

In the drawing only those elements have been shown which facilitate the understanding of the invention, accordingly read/write data buses and those control and timing buses which are not relevant have been omitted.

The illustrated frame store comprises two 16K by 12 bits memory blocks 10,1 12. Each block 10, 1 2 comprises a row/column matrix of memory elements. Any one of the elements can be located by a 14 bit address, 7 of the bits identifying a row and the remaining 7 bits a column. The blocks are interleaved so that one of the blocks contains all the odd-numbered rows and the other of the blocks contains all the even-numbered rows. Each block in this example comprises 256 rows. In order to access a location or memory element in either block 10, 12 a 15 bit read/write address is applied via an input 14 to a latch 16 which comprises a 15 bit multiplexer.Of the 15 bit read/write address the least significant bit identifies which of the two blocks is to be addressed for example a "0" indicates the block 10 and a "1" the block 12, whilst the remaining 14 bits relate to the row/column address of the memory element to be accessed.

The address output from the latch 16 is connected to transparent latches 18,20 whose outputs are connected to the blocks 10, 12 respectively. A transparent latch as a tri-state output and acts as a selector in that its output follows its input as long as its strobe line is high, when the output inhibit line 22 or 24 from timing and control logic 26 goes low then the output is inhibited. Seven bit refresh counters 28,30 are connected via respective transparent latches 32,34to the memory blocks 10, 12 respectively. Each of the transparent latches 32,34 has its inhibit line 36,38. A pair of transparent latches is equivalent to TWO-WIDE AND-OR gates.

In operation, when refreshing it is carried out a row at a time so that one is only interested in the 7 bit row address. The purpose of the refresh counters 28,30 is to provide a seven bit address of the next row in its associated memory blocks to be refreshed and to increment itself to the next row address when a row has been refreshed.

Taking a frame store as an example, as successive lines of data are received to be stored then the latch 16 assigns the data to a particular row of memory elements in one of the memory blocks 10, 12 which is selected in accordance with the least significant bit in the simultaneously received address signals on the input 14. Whilst access to say an odd-numbered row in the block 10 is being obtained, the block 12 is idle and accordingly the refresh counter 30 applies a row address to the block 12 via the transparent latch 34 so that the selected row is refreshed. A memory cycle period, say 400 nS, later the next row of data is to be stored in an even-numbered row so that a row in the block 10 is refreshed. This sequence also applies when reading.

The alorithms for the refreshing of blocks 10 and 12 respectively are: REFRESH 10 = (READING . WRiTING) + ADDRESS 12 REFRESH 12 = (READING . WRITING) + ADDRESS 12 where READING and WRITING are the latched access requests and ADDRESS 12 is the least significant address bit.

As is apparent in the case of sequential addressing there is a maximum utilisation of the store because at no time is it necessary to inhibit reading or writing every 2 mS to carry out a refresh cycle.

In the case of non-sequential addressing which may occur during picture processing the above algorithms still apply. However in the case of say addressing one of the blocks 10, 12 several times in succession then on each clock pulse or memory cycle period the refresh counter associated with the other store refreshes successive rows of the non-addressed block. From calculations made, it is believed that with the worst case non-sequential addressing pattern i.e. access to odd or even addresses only, one would have access to the store for at least 93% of the maximum accessing frequency.

Other advantages of the method in accordance with the present invention over the known refreshing method are that one can have direct memory access, usually executed in a block of characters, without having to carry an overhead in refresh time. Also data storage systems where refresh cannot be hidden (such as video memories and pipeline processors) do not suffer a bottleneck due to routine refresh of the memory.

The timing and control logic 26 includes a fail safe timer which serves to ensure the refreshing of the blocks every 2 mS if there has been no opportunity for refresh. Conveniently, this can be done by inhibiting the transparent latches 18,20 thereby enabling the outputs of the refresh counters 28,30 to be applied to their respective memory blocks 10, 12.

If the store should comprise more than 2 blocks, then either they should be arranged in two groups of blocks so that at any one time when one of the groups is being accessed the other is being refreshed and vice versa, or each block has its own address counter so that when one block is being accessed the remaining blocks are being refreshed. In the case of having 3 or more blocks (or groups of blocks) then the least significant bits are used for addressing them.

In order to maximise the probability of satisfactory refresh, the blocks must be grouped on the basis of the least significant bit or bits of the memory address.

Claims (7)

1. A method of refreshing a dynamic MOS semiconductor memory formed by at least two memory blocks or at least two groups of memory blocks which, whilst one block or group of blocks is being accessed, the other block(s) or group(s) of blocks is (are) being refreshed.

2. A method as claimed in Claim 1, further comprising a fail safe refreshing sequence which refreshes all the memory elements in a block or group of blocks in the event of no access being made thereto after a predetermined time.

3. A method as claimed in Claim 1 or 2, wherein the case of having two memory blocks or two groups of memory blocks, the least significant bit of the memory address is used for identifying the block or group to be accessed.

4. A method of refreshing a dynamic MOS semiconductor memory, substantially as hereinbefore described with reference to the accompanying drawings.

5. A dynamic MOS semiconductor memory comprising at least two memory blocks or at least two groups of memory blocks, each of the blocks or groups having a respective incrementing address counter providing a row address to its associated memory block or group and means for controlling the outputs of address counters so that when one of the blocks or groups of blocks is being accessed, the other block(s) or group(s) of blocks is (are) available for refreshing.

6. A memory as claimed in Claim 5, further comprising a timer for initiating a refresh cycle if there has been no access to a memory block or a group of memory blocks for a predetermined time.

7. A dynamic MOS semiconductor memory constructed and arranged to operate substantially as hereinbefore described with reference to the accompanying drawing.